1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/types.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/rwlock.h> 43 #include <sys/sx.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <net/ethernet.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_media.h> 55 #include <netinet/in.h> 56 #include <netinet/tcp_lro.h> 57 58 #include "offload.h" 59 #include "t4_ioctl.h" 60 #include "common/t4_msg.h" 61 #include "firmware/t4fw_interface.h" 62 63 #define KTR_CXGBE KTR_SPARE3 64 MALLOC_DECLARE(M_CXGBE); 65 #define CXGBE_UNIMPLEMENTED(s) \ 66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 67 68 #if defined(__i386__) || defined(__amd64__) 69 static __inline void 70 prefetch(void *x) 71 { 72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 73 } 74 #else 75 #define prefetch(x) __builtin_prefetch(x) 76 #endif 77 78 #ifndef SYSCTL_ADD_UQUAD 79 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 80 #define sysctl_handle_64 sysctl_handle_quad 81 #define CTLTYPE_U64 CTLTYPE_QUAD 82 #endif 83 84 struct adapter; 85 typedef struct adapter adapter_t; 86 87 enum { 88 /* 89 * All ingress queues use this entry size. Note that the firmware event 90 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 91 * be at least 64. 92 */ 93 IQ_ESIZE = 64, 94 95 /* Default queue sizes for all kinds of ingress queues */ 96 FW_IQ_QSIZE = 256, 97 RX_IQ_QSIZE = 1024, 98 99 /* All egress queues use this entry size */ 100 EQ_ESIZE = 64, 101 102 /* Default queue sizes for all kinds of egress queues */ 103 CTRL_EQ_QSIZE = 128, 104 TX_EQ_QSIZE = 1024, 105 106 #if MJUMPAGESIZE != MCLBYTES 107 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 108 #else 109 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 110 #endif 111 CL_METADATA_SIZE = CACHE_LINE_SIZE, 112 113 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 114 TX_SGL_SEGS = 39, 115 TX_SGL_SEGS_TSO = 38, 116 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 117 }; 118 119 enum { 120 /* adapter intr_type */ 121 INTR_INTX = (1 << 0), 122 INTR_MSI = (1 << 1), 123 INTR_MSIX = (1 << 2) 124 }; 125 126 enum { 127 XGMAC_MTU = (1 << 0), 128 XGMAC_PROMISC = (1 << 1), 129 XGMAC_ALLMULTI = (1 << 2), 130 XGMAC_VLANEX = (1 << 3), 131 XGMAC_UCADDR = (1 << 4), 132 XGMAC_MCADDRS = (1 << 5), 133 134 XGMAC_ALL = 0xffff 135 }; 136 137 enum { 138 /* flags understood by begin_synchronized_op */ 139 HOLD_LOCK = (1 << 0), 140 SLEEP_OK = (1 << 1), 141 INTR_OK = (1 << 2), 142 143 /* flags understood by end_synchronized_op */ 144 LOCK_HELD = HOLD_LOCK, 145 }; 146 147 enum { 148 /* adapter flags */ 149 FULL_INIT_DONE = (1 << 0), 150 FW_OK = (1 << 1), 151 CHK_MBOX_ACCESS = (1 << 2), 152 MASTER_PF = (1 << 3), 153 ADAP_SYSCTL_CTX = (1 << 4), 154 /* TOM_INIT_DONE= (1 << 5), No longer used */ 155 BUF_PACKING_OK = (1 << 6), 156 IS_VF = (1 << 7), 157 158 CXGBE_BUSY = (1 << 9), 159 160 /* port flags */ 161 HAS_TRACEQ = (1 << 3), 162 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 163 164 /* VI flags */ 165 DOOMED = (1 << 0), 166 VI_INIT_DONE = (1 << 1), 167 VI_SYSCTL_CTX = (1 << 2), 168 169 /* adapter debug_flags */ 170 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 171 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 172 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 173 }; 174 175 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 176 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 177 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 178 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 179 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 180 181 struct vi_info { 182 device_t dev; 183 struct port_info *pi; 184 185 struct ifnet *ifp; 186 187 unsigned long flags; 188 int if_flags; 189 190 uint16_t *rss, *nm_rss; 191 int smt_idx; /* for convenience */ 192 uint16_t viid; 193 int16_t xact_addr_filt;/* index of exact MAC address filter */ 194 uint16_t rss_size; /* size of VI's RSS table slice */ 195 uint16_t rss_base; /* start of VI's RSS table slice */ 196 197 eventhandler_tag vlan_c; 198 199 int nintr; 200 int first_intr; 201 202 /* These need to be int as they are used in sysctl */ 203 int ntxq; /* # of tx queues */ 204 int first_txq; /* index of first tx queue */ 205 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 206 int nrxq; /* # of rx queues */ 207 int first_rxq; /* index of first rx queue */ 208 int nofldtxq; /* # of offload tx queues */ 209 int first_ofld_txq; /* index of first offload tx queue */ 210 int nofldrxq; /* # of offload rx queues */ 211 int first_ofld_rxq; /* index of first offload rx queue */ 212 int nnmtxq; 213 int first_nm_txq; 214 int nnmrxq; 215 int first_nm_rxq; 216 int tmr_idx; 217 int ofld_tmr_idx; 218 int pktc_idx; 219 int ofld_pktc_idx; 220 int qsize_rxq; 221 int qsize_txq; 222 223 struct timeval last_refreshed; 224 struct fw_vi_stats_vf stats; 225 226 struct callout tick; 227 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 228 229 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 230 }; 231 232 struct tx_ch_rl_params { 233 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 234 uint32_t maxrate; 235 }; 236 237 enum { 238 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 239 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 240 }; 241 242 struct tx_cl_rl_params { 243 int refcount; 244 u_int flags; 245 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 246 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 247 enum fw_sched_params_mode mode; /* aggr or per-flow */ 248 uint32_t maxrate; 249 uint16_t pktsize; 250 }; 251 252 /* Tx scheduler parameters for a channel/port */ 253 struct tx_sched_params { 254 /* Channel Rate Limiter */ 255 struct tx_ch_rl_params ch_rl; 256 257 /* Class WRR */ 258 /* XXX */ 259 260 /* Class Rate Limiter */ 261 struct tx_cl_rl_params cl_rl[]; 262 }; 263 264 struct port_info { 265 device_t dev; 266 struct adapter *adapter; 267 268 struct vi_info *vi; 269 int nvi; 270 int up_vis; 271 int uld_vis; 272 273 struct tx_sched_params *sched_params; 274 275 struct mtx pi_lock; 276 char lockname[16]; 277 unsigned long flags; 278 279 uint8_t lport; /* associated offload logical port */ 280 int8_t mdio_addr; 281 uint8_t port_type; 282 uint8_t mod_type; 283 uint8_t port_id; 284 uint8_t tx_chan; 285 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 286 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 287 288 struct link_config link_cfg; 289 struct link_config old_link_cfg; 290 struct ifmedia media; 291 292 struct timeval last_refreshed; 293 struct port_stats stats; 294 u_int tnl_cong_drops; 295 u_int tx_parse_error; 296 u_long tx_tls_records; 297 u_long tx_tls_octets; 298 u_long rx_tls_records; 299 u_long rx_tls_octets; 300 301 struct callout tick; 302 }; 303 304 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 305 306 /* Where the cluster came from, how it has been carved up. */ 307 struct cluster_layout { 308 int8_t zidx; 309 int8_t hwidx; 310 uint16_t region1; /* mbufs laid out within this region */ 311 /* region2 is the DMA region */ 312 uint16_t region3; /* cluster_metadata within this region */ 313 }; 314 315 struct cluster_metadata { 316 u_int refcount; 317 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 318 }; 319 320 struct fl_sdesc { 321 caddr_t cl; 322 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 323 struct cluster_layout cll; 324 }; 325 326 struct tx_desc { 327 __be64 flit[8]; 328 }; 329 330 struct tx_sdesc { 331 struct mbuf *m; /* m_nextpkt linked chain of frames */ 332 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 333 }; 334 335 336 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 337 struct iq_desc { 338 struct rss_header rss; 339 uint8_t cpl[IQ_PAD]; 340 struct rsp_ctrl rsp; 341 }; 342 #undef IQ_PAD 343 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 344 345 enum { 346 /* iq flags */ 347 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 348 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 349 /* 1 << 2 Used to be IQ_INTR */ 350 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 351 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 352 353 /* iq state */ 354 IQS_DISABLED = 0, 355 IQS_BUSY = 1, 356 IQS_IDLE = 2, 357 358 /* netmap related flags */ 359 NM_OFF = 0, 360 NM_ON = 1, 361 NM_BUSY = 2, 362 }; 363 364 enum { 365 CPL_COOKIE_RESERVED = 0, 366 CPL_COOKIE_FILTER, 367 CPL_COOKIE_DDP0, 368 CPL_COOKIE_DDP1, 369 CPL_COOKIE_TOM, 370 CPL_COOKIE_HASHFILTER, 371 CPL_COOKIE_ETHOFLD, 372 CPL_COOKIE_AVAILABLE3, 373 374 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 375 }; 376 377 struct sge_iq; 378 struct rss_header; 379 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 380 struct mbuf *); 381 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 382 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 383 384 /* 385 * Ingress Queue: T4 is producer, driver is consumer. 386 */ 387 struct sge_iq { 388 uint32_t flags; 389 volatile int state; 390 struct adapter *adapter; 391 struct iq_desc *desc; /* KVA of descriptor ring */ 392 int8_t intr_pktc_idx; /* packet count threshold index */ 393 uint8_t gen; /* generation bit */ 394 uint8_t intr_params; /* interrupt holdoff parameters */ 395 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 396 uint16_t qsize; /* size (# of entries) of the queue */ 397 uint16_t sidx; /* index of the entry with the status page */ 398 uint16_t cidx; /* consumer index */ 399 uint16_t cntxt_id; /* SGE context id for the iq */ 400 uint16_t abs_id; /* absolute SGE id for the iq */ 401 402 STAILQ_ENTRY(sge_iq) link; 403 404 bus_dma_tag_t desc_tag; 405 bus_dmamap_t desc_map; 406 bus_addr_t ba; /* bus address of descriptor ring */ 407 }; 408 409 enum { 410 EQ_CTRL = 1, 411 EQ_ETH = 2, 412 EQ_OFLD = 3, 413 414 /* eq flags */ 415 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 416 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 417 EQ_ENABLED = (1 << 3), /* open for business */ 418 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 419 }; 420 421 /* Listed in order of preference. Update t4_sysctls too if you change these */ 422 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 423 424 /* 425 * Egress Queue: driver is producer, T4 is consumer. 426 * 427 * Note: A free list is an egress queue (driver produces the buffers and T4 428 * consumes them) but it's special enough to have its own struct (see sge_fl). 429 */ 430 struct sge_eq { 431 unsigned int flags; /* MUST be first */ 432 unsigned int cntxt_id; /* SGE context id for the eq */ 433 unsigned int abs_id; /* absolute SGE id for the eq */ 434 struct mtx eq_lock; 435 436 struct tx_desc *desc; /* KVA of descriptor ring */ 437 uint8_t doorbells; 438 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 439 u_int udb_qid; /* relative qid within the doorbell page */ 440 uint16_t sidx; /* index of the entry with the status page */ 441 uint16_t cidx; /* consumer idx (desc idx) */ 442 uint16_t pidx; /* producer idx (desc idx) */ 443 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 444 uint16_t dbidx; /* pidx of the most recent doorbell */ 445 uint16_t iqid; /* iq that gets egr_update for the eq */ 446 uint8_t tx_chan; /* tx channel used by the eq */ 447 volatile u_int equiq; /* EQUIQ outstanding */ 448 449 bus_dma_tag_t desc_tag; 450 bus_dmamap_t desc_map; 451 bus_addr_t ba; /* bus address of descriptor ring */ 452 char lockname[16]; 453 }; 454 455 struct sw_zone_info { 456 uma_zone_t zone; /* zone that this cluster comes from */ 457 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 458 int type; /* EXT_xxx type of the cluster */ 459 int8_t head_hwidx; 460 int8_t tail_hwidx; 461 }; 462 463 struct hw_buf_info { 464 int8_t zidx; /* backpointer to zone; -ve means unused */ 465 int8_t next; /* next hwidx for this zone; -1 means no more */ 466 int size; 467 }; 468 469 enum { 470 NUM_MEMWIN = 3, 471 472 MEMWIN0_APERTURE = 2048, 473 MEMWIN0_BASE = 0x1b800, 474 475 MEMWIN1_APERTURE = 32768, 476 MEMWIN1_BASE = 0x28000, 477 478 MEMWIN2_APERTURE_T4 = 65536, 479 MEMWIN2_BASE_T4 = 0x30000, 480 481 MEMWIN2_APERTURE_T5 = 128 * 1024, 482 MEMWIN2_BASE_T5 = 0x60000, 483 }; 484 485 struct memwin { 486 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 487 uint32_t mw_base; /* constant after setup_memwin */ 488 uint32_t mw_aperture; /* ditto */ 489 uint32_t mw_curpos; /* protected by mw_lock */ 490 }; 491 492 enum { 493 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 494 FL_DOOMED = (1 << 1), /* about to be destroyed */ 495 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 496 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 497 }; 498 499 #define FL_RUNNING_LOW(fl) \ 500 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 501 #define FL_NOT_RUNNING_LOW(fl) \ 502 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 503 504 struct sge_fl { 505 struct mtx fl_lock; 506 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 507 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 508 struct cluster_layout cll_def; /* default refill zone, layout */ 509 uint16_t lowat; /* # of buffers <= this means fl needs help */ 510 int flags; 511 uint16_t buf_boundary; 512 513 /* The 16b idx all deal with hw descriptors */ 514 uint16_t dbidx; /* hw pidx after last doorbell */ 515 uint16_t sidx; /* index of status page */ 516 volatile uint16_t hw_cidx; 517 518 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 519 uint32_t cidx; /* consumer index */ 520 uint32_t pidx; /* producer index */ 521 522 uint32_t dbval; 523 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 524 volatile uint32_t *udb; 525 526 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 527 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 528 uint64_t cl_allocated; /* # of clusters allocated */ 529 uint64_t cl_recycled; /* # of clusters recycled */ 530 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 531 532 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 533 struct mbuf *m0; 534 struct mbuf **pnext; 535 u_int remaining; 536 537 uint16_t qsize; /* # of hw descriptors (status page included) */ 538 uint16_t cntxt_id; /* SGE context id for the freelist */ 539 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 540 bus_dma_tag_t desc_tag; 541 bus_dmamap_t desc_map; 542 char lockname[16]; 543 bus_addr_t ba; /* bus address of descriptor ring */ 544 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 545 }; 546 547 struct mp_ring; 548 549 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 550 struct sge_txq { 551 struct sge_eq eq; /* MUST be first */ 552 553 struct ifnet *ifp; /* the interface this txq belongs to */ 554 struct mp_ring *r; /* tx software ring */ 555 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 556 struct sglist *gl; 557 __be32 cpl_ctrl0; /* for convenience */ 558 int tc_idx; /* traffic class */ 559 560 struct task tx_reclaim_task; 561 /* stats for common events first */ 562 563 uint64_t txcsum; /* # of times hardware assisted with checksum */ 564 uint64_t tso_wrs; /* # of TSO work requests */ 565 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 566 uint64_t imm_wrs; /* # of work requests with immediate data */ 567 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 568 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 569 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 570 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 571 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 572 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 573 574 /* stats for not-that-common events */ 575 } __aligned(CACHE_LINE_SIZE); 576 577 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 578 struct sge_rxq { 579 struct sge_iq iq; /* MUST be first */ 580 struct sge_fl fl; /* MUST follow iq */ 581 582 struct ifnet *ifp; /* the interface this rxq belongs to */ 583 #if defined(INET) || defined(INET6) 584 struct lro_ctrl lro; /* LRO state */ 585 #endif 586 587 /* stats for common events first */ 588 589 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 590 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 591 592 /* stats for not-that-common events */ 593 594 } __aligned(CACHE_LINE_SIZE); 595 596 static inline struct sge_rxq * 597 iq_to_rxq(struct sge_iq *iq) 598 { 599 600 return (__containerof(iq, struct sge_rxq, iq)); 601 } 602 603 604 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 605 struct sge_ofld_rxq { 606 struct sge_iq iq; /* MUST be first */ 607 struct sge_fl fl; /* MUST follow iq */ 608 } __aligned(CACHE_LINE_SIZE); 609 610 static inline struct sge_ofld_rxq * 611 iq_to_ofld_rxq(struct sge_iq *iq) 612 { 613 614 return (__containerof(iq, struct sge_ofld_rxq, iq)); 615 } 616 617 struct wrqe { 618 STAILQ_ENTRY(wrqe) link; 619 struct sge_wrq *wrq; 620 int wr_len; 621 char wr[] __aligned(16); 622 }; 623 624 struct wrq_cookie { 625 TAILQ_ENTRY(wrq_cookie) link; 626 int ndesc; 627 int pidx; 628 }; 629 630 /* 631 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 632 * and offload tx queues are of this type. 633 */ 634 struct sge_wrq { 635 struct sge_eq eq; /* MUST be first */ 636 637 struct adapter *adapter; 638 struct task wrq_tx_task; 639 640 /* Tx desc reserved but WR not "committed" yet. */ 641 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 642 643 /* List of WRs ready to go out as soon as descriptors are available. */ 644 STAILQ_HEAD(, wrqe) wr_list; 645 u_int nwr_pending; 646 u_int ndesc_needed; 647 648 /* stats for common events first */ 649 650 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 651 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 652 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 653 654 /* stats for not-that-common events */ 655 656 /* 657 * Scratch space for work requests that wrap around after reaching the 658 * status page, and some information about the last WR that used it. 659 */ 660 uint16_t ss_pidx; 661 uint16_t ss_len; 662 uint8_t ss[SGE_MAX_WR_LEN]; 663 664 } __aligned(CACHE_LINE_SIZE); 665 666 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 667 struct sge_nm_rxq { 668 struct vi_info *vi; 669 670 struct iq_desc *iq_desc; 671 uint16_t iq_abs_id; 672 uint16_t iq_cntxt_id; 673 uint16_t iq_cidx; 674 uint16_t iq_sidx; 675 uint8_t iq_gen; 676 677 __be64 *fl_desc; 678 uint16_t fl_cntxt_id; 679 uint32_t fl_cidx; 680 uint32_t fl_pidx; 681 uint32_t fl_sidx; 682 uint32_t fl_db_val; 683 u_int fl_hwidx:4; 684 685 u_int nid; /* netmap ring # for this queue */ 686 687 /* infrequently used items after this */ 688 689 bus_dma_tag_t iq_desc_tag; 690 bus_dmamap_t iq_desc_map; 691 bus_addr_t iq_ba; 692 int intr_idx; 693 694 bus_dma_tag_t fl_desc_tag; 695 bus_dmamap_t fl_desc_map; 696 bus_addr_t fl_ba; 697 } __aligned(CACHE_LINE_SIZE); 698 699 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 700 struct sge_nm_txq { 701 struct tx_desc *desc; 702 uint16_t cidx; 703 uint16_t pidx; 704 uint16_t sidx; 705 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 706 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 707 uint16_t dbidx; /* pidx of the most recent doorbell */ 708 uint8_t doorbells; 709 volatile uint32_t *udb; 710 u_int udb_qid; 711 u_int cntxt_id; 712 __be32 cpl_ctrl0; /* for convenience */ 713 u_int nid; /* netmap ring # for this queue */ 714 715 /* infrequently used items after this */ 716 717 bus_dma_tag_t desc_tag; 718 bus_dmamap_t desc_map; 719 bus_addr_t ba; 720 int iqidx; 721 } __aligned(CACHE_LINE_SIZE); 722 723 struct sge { 724 int nrxq; /* total # of Ethernet rx queues */ 725 int ntxq; /* total # of Ethernet tx queues */ 726 int nofldrxq; /* total # of TOE rx queues */ 727 int nofldtxq; /* total # of TOE tx queues */ 728 int nnmrxq; /* total # of netmap rx queues */ 729 int nnmtxq; /* total # of netmap tx queues */ 730 int niq; /* total # of ingress queues */ 731 int neq; /* total # of egress queues */ 732 733 struct sge_iq fwq; /* Firmware event queue */ 734 struct sge_wrq mgmtq; /* Management queue (control queue) */ 735 struct sge_wrq *ctrlq; /* Control queues */ 736 struct sge_txq *txq; /* NIC tx queues */ 737 struct sge_rxq *rxq; /* NIC rx queues */ 738 struct sge_wrq *ofld_txq; /* TOE tx queues */ 739 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 740 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 741 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 742 743 uint16_t iq_start; /* first cntxt_id */ 744 uint16_t iq_base; /* first abs_id */ 745 int eq_start; /* first cntxt_id */ 746 int eq_base; /* first abs_id */ 747 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 748 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 749 750 int8_t safe_hwidx1; /* may not have room for metadata */ 751 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 752 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 753 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 754 }; 755 756 struct devnames { 757 const char *nexus_name; 758 const char *ifnet_name; 759 const char *vi_ifnet_name; 760 const char *pf03_drv_name; 761 const char *vf_nexus_name; 762 const char *vf_ifnet_name; 763 }; 764 765 struct adapter { 766 SLIST_ENTRY(adapter) link; 767 device_t dev; 768 struct cdev *cdev; 769 const struct devnames *names; 770 771 /* PCIe register resources */ 772 int regs_rid; 773 struct resource *regs_res; 774 int msix_rid; 775 struct resource *msix_res; 776 bus_space_handle_t bh; 777 bus_space_tag_t bt; 778 bus_size_t mmio_len; 779 int udbs_rid; 780 struct resource *udbs_res; 781 volatile uint8_t *udbs_base; 782 783 unsigned int pf; 784 unsigned int mbox; 785 unsigned int vpd_busy; 786 unsigned int vpd_flag; 787 788 /* Interrupt information */ 789 int intr_type; 790 int intr_count; 791 struct irq { 792 struct resource *res; 793 int rid; 794 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 795 void *tag; 796 struct sge_rxq *rxq; 797 struct sge_nm_rxq *nm_rxq; 798 } __aligned(CACHE_LINE_SIZE) *irq; 799 int sge_gts_reg; 800 int sge_kdoorbell_reg; 801 802 bus_dma_tag_t dmat; /* Parent DMA tag */ 803 804 struct sge sge; 805 int lro_timeout; 806 int sc_do_rxcopy; 807 808 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 809 struct port_info *port[MAX_NPORTS]; 810 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 811 812 void *tom_softc; /* (struct tom_data *) */ 813 struct tom_tunables tt; 814 struct t4_offload_policy *policy; 815 struct rwlock policy_lock; 816 817 void *iwarp_softc; /* (struct c4iw_dev *) */ 818 struct iw_tunables iwt; 819 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 820 void *ccr_softc; /* (struct ccr_softc *) */ 821 struct l2t_data *l2t; /* L2 table */ 822 struct smt_data *smt; /* Source MAC Table */ 823 struct tid_info tids; 824 825 uint8_t doorbells; 826 int offload_map; /* ports with IFCAP_TOE enabled */ 827 int active_ulds; /* ULDs activated on this adapter */ 828 int flags; 829 int debug_flags; 830 831 char ifp_lockname[16]; 832 struct mtx ifp_lock; 833 struct ifnet *ifp; /* tracer ifp */ 834 struct ifmedia media; 835 int traceq; /* iq used by all tracers, -1 if none */ 836 int tracer_valid; /* bitmap of valid tracers */ 837 int tracer_enabled; /* bitmap of enabled tracers */ 838 839 char fw_version[16]; 840 char tp_version[16]; 841 char er_version[16]; 842 char bs_version[16]; 843 char cfg_file[32]; 844 u_int cfcsum; 845 struct adapter_params params; 846 const struct chip_params *chip_params; 847 struct t4_virt_res vres; 848 849 uint16_t nbmcaps; 850 uint16_t linkcaps; 851 uint16_t switchcaps; 852 uint16_t niccaps; 853 uint16_t toecaps; 854 uint16_t rdmacaps; 855 uint16_t cryptocaps; 856 uint16_t iscsicaps; 857 uint16_t fcoecaps; 858 859 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 860 861 struct mtx sc_lock; 862 char lockname[16]; 863 864 /* Starving free lists */ 865 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 866 TAILQ_HEAD(, sge_fl) sfl; 867 struct callout sfl_callout; 868 869 struct mtx reg_lock; /* for indirect register access */ 870 871 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 872 873 struct mtx tc_lock; 874 struct task tc_task; 875 876 const char *last_op; 877 const void *last_op_thr; 878 int last_op_flags; 879 }; 880 881 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 882 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 883 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 884 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 885 886 #define ASSERT_SYNCHRONIZED_OP(sc) \ 887 KASSERT(IS_BUSY(sc) && \ 888 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 889 ("%s: operation not synchronized.", __func__)) 890 891 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 892 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 893 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 894 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 895 896 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 897 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 898 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 899 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 900 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 901 902 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 903 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 904 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 905 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 906 907 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 908 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 909 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 910 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 911 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 912 913 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 914 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 915 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 916 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 917 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 918 919 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 920 do { \ 921 if (sc->debug_flags & DF_DUMP_MBOX) { \ 922 log(LOG_NOTICE, \ 923 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 924 "%016llx %016llx %016llx %016llx\n", \ 925 device_get_nameunit(sc->dev), mbox, \ 926 (unsigned long long)t4_read_reg64(sc, data_reg), \ 927 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 928 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 929 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 930 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 931 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 932 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 933 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 934 } \ 935 } while (0) 936 937 #define for_each_txq(vi, iter, q) \ 938 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 939 iter < vi->ntxq; ++iter, ++q) 940 #define for_each_rxq(vi, iter, q) \ 941 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 942 iter < vi->nrxq; ++iter, ++q) 943 #define for_each_ofld_txq(vi, iter, q) \ 944 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 945 iter < vi->nofldtxq; ++iter, ++q) 946 #define for_each_ofld_rxq(vi, iter, q) \ 947 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 948 iter < vi->nofldrxq; ++iter, ++q) 949 #define for_each_nm_txq(vi, iter, q) \ 950 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 951 iter < vi->nnmtxq; ++iter, ++q) 952 #define for_each_nm_rxq(vi, iter, q) \ 953 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 954 iter < vi->nnmrxq; ++iter, ++q) 955 #define for_each_vi(_pi, _iter, _vi) \ 956 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 957 ++(_iter), ++(_vi)) 958 959 #define IDXINCR(idx, incr, wrap) do { \ 960 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 961 } while (0) 962 #define IDXDIFF(head, tail, wrap) \ 963 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 964 965 /* One for errors, one for firmware events */ 966 #define T4_EXTRA_INTR 2 967 968 /* One for firmware events */ 969 #define T4VF_EXTRA_INTR 1 970 971 static inline int 972 forwarding_intr_to_fwq(struct adapter *sc) 973 { 974 975 return (sc->intr_count == 1); 976 } 977 978 static inline uint32_t 979 t4_read_reg(struct adapter *sc, uint32_t reg) 980 { 981 982 return bus_space_read_4(sc->bt, sc->bh, reg); 983 } 984 985 static inline void 986 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 987 { 988 989 bus_space_write_4(sc->bt, sc->bh, reg, val); 990 } 991 992 static inline uint64_t 993 t4_read_reg64(struct adapter *sc, uint32_t reg) 994 { 995 996 #ifdef __LP64__ 997 return bus_space_read_8(sc->bt, sc->bh, reg); 998 #else 999 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1000 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1001 1002 #endif 1003 } 1004 1005 static inline void 1006 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1007 { 1008 1009 #ifdef __LP64__ 1010 bus_space_write_8(sc->bt, sc->bh, reg, val); 1011 #else 1012 bus_space_write_4(sc->bt, sc->bh, reg, val); 1013 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1014 #endif 1015 } 1016 1017 static inline void 1018 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1019 { 1020 1021 *val = pci_read_config(sc->dev, reg, 1); 1022 } 1023 1024 static inline void 1025 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1026 { 1027 1028 pci_write_config(sc->dev, reg, val, 1); 1029 } 1030 1031 static inline void 1032 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1033 { 1034 1035 *val = pci_read_config(sc->dev, reg, 2); 1036 } 1037 1038 static inline void 1039 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1040 { 1041 1042 pci_write_config(sc->dev, reg, val, 2); 1043 } 1044 1045 static inline void 1046 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1047 { 1048 1049 *val = pci_read_config(sc->dev, reg, 4); 1050 } 1051 1052 static inline void 1053 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1054 { 1055 1056 pci_write_config(sc->dev, reg, val, 4); 1057 } 1058 1059 static inline struct port_info * 1060 adap2pinfo(struct adapter *sc, int idx) 1061 { 1062 1063 return (sc->port[idx]); 1064 } 1065 1066 static inline void 1067 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1068 { 1069 1070 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1071 } 1072 1073 static inline bool 1074 is_10G_port(const struct port_info *pi) 1075 { 1076 1077 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1078 } 1079 1080 static inline bool 1081 is_25G_port(const struct port_info *pi) 1082 { 1083 1084 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1085 } 1086 1087 static inline bool 1088 is_40G_port(const struct port_info *pi) 1089 { 1090 1091 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1092 } 1093 1094 static inline bool 1095 is_100G_port(const struct port_info *pi) 1096 { 1097 1098 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1099 } 1100 1101 static inline int 1102 port_top_speed(const struct port_info *pi) 1103 { 1104 1105 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1106 return (100); 1107 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1108 return (40); 1109 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1110 return (25); 1111 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1112 return (10); 1113 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1114 return (1); 1115 1116 return (0); 1117 } 1118 1119 static inline int 1120 tx_resume_threshold(struct sge_eq *eq) 1121 { 1122 1123 /* not quite the same as qsize / 4, but this will do. */ 1124 return (eq->sidx / 4); 1125 } 1126 1127 static inline int 1128 t4_use_ldst(struct adapter *sc) 1129 { 1130 1131 #ifdef notyet 1132 return (sc->flags & FW_OK || !sc->use_bd); 1133 #else 1134 return (0); 1135 #endif 1136 } 1137 1138 /* t4_main.c */ 1139 extern int t4_ntxq; 1140 extern int t4_nrxq; 1141 extern int t4_intr_types; 1142 extern int t4_tmr_idx; 1143 extern int t4_pktc_idx; 1144 extern unsigned int t4_qsize_rxq; 1145 extern unsigned int t4_qsize_txq; 1146 extern device_method_t cxgbe_methods[]; 1147 1148 int t4_os_find_pci_capability(struct adapter *, int); 1149 int t4_os_pci_save_state(struct adapter *); 1150 int t4_os_pci_restore_state(struct adapter *); 1151 void t4_os_portmod_changed(struct port_info *); 1152 void t4_os_link_changed(struct port_info *); 1153 void t4_iterate(void (*)(struct adapter *, void *), void *); 1154 void t4_init_devnames(struct adapter *); 1155 void t4_add_adapter(struct adapter *); 1156 void t4_aes_getdeckey(void *, const void *, unsigned int); 1157 int t4_detach_common(device_t); 1158 int t4_map_bars_0_and_4(struct adapter *); 1159 int t4_map_bar_2(struct adapter *); 1160 int t4_setup_intr_handlers(struct adapter *); 1161 void t4_sysctls(struct adapter *); 1162 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1163 void doom_vi(struct adapter *, struct vi_info *); 1164 void end_synchronized_op(struct adapter *, int); 1165 int update_mac_settings(struct ifnet *, int); 1166 int adapter_full_init(struct adapter *); 1167 int adapter_full_uninit(struct adapter *); 1168 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1169 int vi_full_init(struct vi_info *); 1170 int vi_full_uninit(struct vi_info *); 1171 void vi_sysctls(struct vi_info *); 1172 void vi_tick(void *); 1173 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1174 int alloc_atid_tab(struct tid_info *, int); 1175 void free_atid_tab(struct tid_info *); 1176 int alloc_atid(struct adapter *, void *); 1177 void *lookup_atid(struct adapter *, int); 1178 void free_atid(struct adapter *, int); 1179 void release_tid(struct adapter *, int, struct sge_wrq *); 1180 1181 #ifdef DEV_NETMAP 1182 /* t4_netmap.c */ 1183 void cxgbe_nm_attach(struct vi_info *); 1184 void cxgbe_nm_detach(struct vi_info *); 1185 void t4_nm_intr(void *); 1186 #endif 1187 1188 /* t4_sge.c */ 1189 void t4_sge_modload(void); 1190 void t4_sge_modunload(void); 1191 uint64_t t4_sge_extfree_refs(void); 1192 void t4_tweak_chip_settings(struct adapter *); 1193 int t4_read_chip_settings(struct adapter *); 1194 int t4_create_dma_tag(struct adapter *); 1195 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1196 struct sysctl_oid_list *); 1197 int t4_destroy_dma_tag(struct adapter *); 1198 int t4_setup_adapter_queues(struct adapter *); 1199 int t4_teardown_adapter_queues(struct adapter *); 1200 int t4_setup_vi_queues(struct vi_info *); 1201 int t4_teardown_vi_queues(struct vi_info *); 1202 void t4_intr_all(void *); 1203 void t4_intr(void *); 1204 void t4_vi_intr(void *); 1205 void t4_intr_err(void *); 1206 void t4_intr_evt(void *); 1207 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1208 void t4_update_fl_bufsize(struct ifnet *); 1209 int parse_pkt(struct adapter *, struct mbuf **); 1210 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1211 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1212 int tnl_cong(struct port_info *, int); 1213 void t4_register_an_handler(an_handler_t); 1214 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1215 void t4_register_cpl_handler(int, cpl_handler_t); 1216 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1217 #ifdef RATELIMIT 1218 int ethofld_transmit(struct ifnet *, struct mbuf *); 1219 void send_etid_flush_wr(struct cxgbe_snd_tag *); 1220 #endif 1221 1222 /* t4_tracer.c */ 1223 struct t4_tracer; 1224 void t4_tracer_modload(void); 1225 void t4_tracer_modunload(void); 1226 void t4_tracer_port_detach(struct adapter *); 1227 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1228 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1229 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1230 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1231 1232 /* t4_sched.c */ 1233 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1234 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1235 int t4_init_tx_sched(struct adapter *); 1236 int t4_free_tx_sched(struct adapter *); 1237 void t4_update_tx_sched(struct adapter *); 1238 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1239 void t4_release_cl_rl_kbps(struct adapter *, int, int); 1240 #ifdef RATELIMIT 1241 void t4_init_etid_table(struct adapter *); 1242 void t4_free_etid_table(struct adapter *); 1243 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int); 1244 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1245 struct m_snd_tag **); 1246 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1247 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1248 void cxgbe_snd_tag_free(struct m_snd_tag *); 1249 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *); 1250 #endif 1251 1252 /* t4_filter.c */ 1253 int get_filter_mode(struct adapter *, uint32_t *); 1254 int set_filter_mode(struct adapter *, uint32_t); 1255 int get_filter(struct adapter *, struct t4_filter *); 1256 int set_filter(struct adapter *, struct t4_filter *); 1257 int del_filter(struct adapter *, struct t4_filter *); 1258 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1259 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1260 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1261 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1262 1263 static inline struct wrqe * 1264 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1265 { 1266 int len = offsetof(struct wrqe, wr) + wr_len; 1267 struct wrqe *wr; 1268 1269 wr = malloc(len, M_CXGBE, M_NOWAIT); 1270 if (__predict_false(wr == NULL)) 1271 return (NULL); 1272 wr->wr_len = wr_len; 1273 wr->wrq = wrq; 1274 return (wr); 1275 } 1276 1277 static inline void * 1278 wrtod(struct wrqe *wr) 1279 { 1280 return (&wr->wr[0]); 1281 } 1282 1283 static inline void 1284 free_wrqe(struct wrqe *wr) 1285 { 1286 free(wr, M_CXGBE); 1287 } 1288 1289 static inline void 1290 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1291 { 1292 struct sge_wrq *wrq = wr->wrq; 1293 1294 TXQ_LOCK(wrq); 1295 t4_wrq_tx_locked(sc, wrq, wr); 1296 TXQ_UNLOCK(wrq); 1297 } 1298 1299 static inline int 1300 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1301 int len) 1302 { 1303 1304 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1305 } 1306 1307 static inline int 1308 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1309 const uint32_t *val, int len) 1310 { 1311 1312 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1313 } 1314 #endif 1315