1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/counter.h> 37 #include <sys/rman.h> 38 #include <sys/types.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/rwlock.h> 42 #include <sys/seqc.h> 43 #include <sys/sx.h> 44 #include <sys/vmem.h> 45 #include <vm/uma.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <machine/bus.h> 50 #include <sys/socket.h> 51 #include <sys/sysctl.h> 52 #include <sys/taskqueue.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 /* 72 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 73 * LIST_HEAD when building iw_cxgbe. 74 */ 75 #define CXGBE_LIST_HEAD(name, type) \ 76 struct name { \ 77 struct type *lh_first; /* first element */ \ 78 } 79 80 #ifndef SYSCTL_ADD_UQUAD 81 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 82 #define sysctl_handle_64 sysctl_handle_quad 83 #define CTLTYPE_U64 CTLTYPE_QUAD 84 #endif 85 86 SYSCTL_DECL(_hw_cxgbe); 87 88 struct adapter; 89 typedef struct adapter adapter_t; 90 91 enum { 92 /* 93 * All ingress queues use this entry size. Note that the firmware event 94 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 95 * be at least 64. 96 */ 97 IQ_ESIZE = 64, 98 99 /* Default queue sizes for all kinds of ingress queues */ 100 FW_IQ_QSIZE = 256, 101 RX_IQ_QSIZE = 1024, 102 103 /* All egress queues use this entry size */ 104 EQ_ESIZE = 64, 105 106 /* Default queue sizes for all kinds of egress queues */ 107 CTRL_EQ_QSIZE = 1024, 108 TX_EQ_QSIZE = 1024, 109 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 CL_METADATA_SIZE = CACHE_LINE_SIZE, 112 113 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 114 TX_SGL_SEGS = 39, 115 TX_SGL_SEGS_TSO = 38, 116 TX_SGL_SEGS_VM = 38, 117 TX_SGL_SEGS_VM_TSO = 37, 118 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 119 TX_SGL_SEGS_VXLAN_TSO = 37, 120 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 121 }; 122 123 enum { 124 /* adapter intr_type */ 125 INTR_INTX = (1 << 0), 126 INTR_MSI = (1 << 1), 127 INTR_MSIX = (1 << 2) 128 }; 129 130 enum { 131 XGMAC_MTU = (1 << 0), 132 XGMAC_PROMISC = (1 << 1), 133 XGMAC_ALLMULTI = (1 << 2), 134 XGMAC_VLANEX = (1 << 3), 135 XGMAC_UCADDR = (1 << 4), 136 XGMAC_MCADDRS = (1 << 5), 137 138 XGMAC_ALL = 0xffff 139 }; 140 141 enum { 142 /* flags understood by begin_synchronized_op */ 143 HOLD_LOCK = (1 << 0), 144 SLEEP_OK = (1 << 1), 145 INTR_OK = (1 << 2), 146 147 /* flags understood by end_synchronized_op */ 148 LOCK_HELD = HOLD_LOCK, 149 }; 150 151 enum { 152 /* adapter flags. synch_op or adapter_lock. */ 153 FULL_INIT_DONE = (1 << 0), 154 FW_OK = (1 << 1), 155 CHK_MBOX_ACCESS = (1 << 2), 156 MASTER_PF = (1 << 3), 157 BUF_PACKING_OK = (1 << 6), 158 IS_VF = (1 << 7), 159 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 160 CXGBE_BUSY = (1 << 9), 161 162 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 163 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 164 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 165 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 166 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 167 168 /* port flags */ 169 HAS_TRACEQ = (1 << 3), 170 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 171 172 /* VI flags */ 173 VI_DETACHING = (1 << 0), 174 VI_INIT_DONE = (1 << 1), 175 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 176 TX_USES_VM_WR = (1 << 3), 177 VI_SKIP_STATS = (1 << 4), 178 179 /* adapter debug_flags */ 180 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 181 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 182 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 183 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 184 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 185 }; 186 187 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING) 188 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0) 189 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0) 190 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 191 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 192 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 193 194 struct vi_info { 195 device_t dev; 196 struct port_info *pi; 197 struct adapter *adapter; 198 199 if_t ifp; 200 struct pfil_head *pfil; 201 202 unsigned long flags; 203 int if_flags; 204 205 uint16_t *rss, *nm_rss; 206 uint16_t viid; /* opaque VI identifier */ 207 uint16_t smt_idx; 208 uint16_t vin; 209 uint8_t vfvld; 210 int16_t xact_addr_filt;/* index of exact MAC address filter */ 211 uint16_t rss_size; /* size of VI's RSS table slice */ 212 uint16_t rss_base; /* start of VI's RSS table slice */ 213 int hashen; 214 215 int nintr; 216 int first_intr; 217 218 /* These need to be int as they are used in sysctl */ 219 int ntxq; /* # of tx queues */ 220 int first_txq; /* index of first tx queue */ 221 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 222 int nrxq; /* # of rx queues */ 223 int first_rxq; /* index of first rx queue */ 224 int nofldtxq; /* # of offload tx queues */ 225 int first_ofld_txq; /* index of first offload tx queue */ 226 int nofldrxq; /* # of offload rx queues */ 227 int first_ofld_rxq; /* index of first offload rx queue */ 228 int nnmtxq; 229 int first_nm_txq; 230 int nnmrxq; 231 int first_nm_rxq; 232 int tmr_idx; 233 int ofld_tmr_idx; 234 int pktc_idx; 235 int ofld_pktc_idx; 236 int qsize_rxq; 237 int qsize_txq; 238 239 struct timeval last_refreshed; 240 struct fw_vi_stats_vf stats; 241 struct mtx tick_mtx; 242 struct callout tick; 243 244 struct sysctl_ctx_list ctx; 245 struct sysctl_oid *rxq_oid; 246 struct sysctl_oid *txq_oid; 247 struct sysctl_oid *nm_rxq_oid; 248 struct sysctl_oid *nm_txq_oid; 249 struct sysctl_oid *ofld_rxq_oid; 250 struct sysctl_oid *ofld_txq_oid; 251 252 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 253 u_int txq_rr; 254 u_int rxq_rr; 255 }; 256 257 struct tx_ch_rl_params { 258 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 259 uint32_t maxrate; 260 }; 261 262 /* CLRL state */ 263 enum clrl_state { 264 CS_UNINITIALIZED = 0, 265 CS_PARAMS_SET, /* sw parameters have been set. */ 266 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 267 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 268 CS_HW_CONFIGURED /* configured in the hardware. */ 269 }; 270 271 /* CLRL flags */ 272 enum { 273 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 274 }; 275 276 struct tx_cl_rl_params { 277 enum clrl_state state; 278 int refcount; 279 uint8_t flags; 280 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 281 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 282 enum fw_sched_params_mode mode; /* aggr or per-flow */ 283 uint32_t maxrate; 284 uint16_t pktsize; 285 uint16_t burstsize; 286 }; 287 288 /* Tx scheduler parameters for a channel/port */ 289 struct tx_sched_params { 290 /* Channel Rate Limiter */ 291 struct tx_ch_rl_params ch_rl; 292 293 /* Class WRR */ 294 /* XXX */ 295 296 /* Class Rate Limiter (including the default pktsize and burstsize). */ 297 int pktsize; 298 int burstsize; 299 struct tx_cl_rl_params cl_rl[]; 300 }; 301 302 struct port_info { 303 device_t dev; 304 struct adapter *adapter; 305 306 struct vi_info *vi; 307 int nvi; 308 int up_vis; 309 int uld_vis; 310 bool vxlan_tcam_entry; 311 312 struct tx_sched_params *sched_params; 313 314 struct mtx pi_lock; 315 char lockname[16]; 316 unsigned long flags; 317 318 uint8_t lport; /* associated offload logical port */ 319 int8_t mdio_addr; 320 uint8_t port_type; 321 uint8_t mod_type; 322 uint8_t port_id; 323 uint8_t tx_chan; 324 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 325 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 326 uint8_t rx_c_chan; /* rx TP c-channel */ 327 328 struct link_config link_cfg; 329 struct ifmedia media; 330 331 struct port_stats stats; 332 u_int tnl_cong_drops; 333 u_int tx_parse_error; 334 int fcs_reg; 335 uint64_t fcs_base; 336 337 struct sysctl_ctx_list ctx; 338 }; 339 340 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 341 342 struct cluster_metadata { 343 uma_zone_t zone; 344 caddr_t cl; 345 u_int refcount; 346 }; 347 348 struct fl_sdesc { 349 caddr_t cl; 350 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 351 int16_t moff; /* offset of metadata from cl */ 352 uint8_t zidx; 353 }; 354 355 struct tx_desc { 356 __be64 flit[8]; 357 }; 358 359 struct tx_sdesc { 360 struct mbuf *m; /* m_nextpkt linked chain of frames */ 361 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 362 }; 363 364 365 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 366 struct iq_desc { 367 struct rss_header rss; 368 uint8_t cpl[IQ_PAD]; 369 struct rsp_ctrl rsp; 370 }; 371 #undef IQ_PAD 372 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 373 374 enum { 375 /* iq type */ 376 IQ_OTHER = FW_IQ_IQTYPE_OTHER, 377 IQ_ETH = FW_IQ_IQTYPE_NIC, 378 IQ_OFLD = FW_IQ_IQTYPE_OFLD, 379 380 /* iq flags */ 381 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 382 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 383 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 384 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 385 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 386 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 387 388 /* iq state */ 389 IQS_DISABLED = 0, 390 IQS_BUSY = 1, 391 IQS_IDLE = 2, 392 393 /* netmap related flags */ 394 NM_OFF = 0, 395 NM_ON = 1, 396 NM_BUSY = 2, 397 }; 398 399 enum { 400 CPL_COOKIE_RESERVED = 0, 401 CPL_COOKIE_FILTER, 402 CPL_COOKIE_DDP0, 403 CPL_COOKIE_DDP1, 404 CPL_COOKIE_TOM, 405 CPL_COOKIE_HASHFILTER, 406 CPL_COOKIE_ETHOFLD, 407 CPL_COOKIE_KERN_TLS, 408 409 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 410 }; 411 412 struct sge_iq; 413 struct rss_header; 414 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 415 struct mbuf *); 416 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 417 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 418 419 /* 420 * Ingress Queue: T4 is producer, driver is consumer. 421 */ 422 struct sge_iq { 423 uint16_t flags; 424 uint8_t qtype; 425 volatile int state; 426 struct adapter *adapter; 427 struct iq_desc *desc; /* KVA of descriptor ring */ 428 int8_t intr_pktc_idx; /* packet count threshold index */ 429 uint8_t gen; /* generation bit */ 430 uint8_t intr_params; /* interrupt holdoff parameters */ 431 int8_t cong_drop; /* congestion drop settings for the queue */ 432 uint16_t qsize; /* size (# of entries) of the queue */ 433 uint16_t sidx; /* index of the entry with the status page */ 434 uint16_t cidx; /* consumer index */ 435 uint16_t cntxt_id; /* SGE context id for the iq */ 436 uint16_t abs_id; /* absolute SGE id for the iq */ 437 int16_t intr_idx; /* interrupt used by the queue */ 438 439 STAILQ_ENTRY(sge_iq) link; 440 441 bus_dma_tag_t desc_tag; 442 bus_dmamap_t desc_map; 443 bus_addr_t ba; /* bus address of descriptor ring */ 444 }; 445 446 enum { 447 /* eq type */ 448 EQ_CTRL = 1, 449 EQ_ETH = 2, 450 EQ_OFLD = 3, 451 452 /* eq flags */ 453 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 454 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 455 EQ_ENABLED = (1 << 3), /* open for business */ 456 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 457 }; 458 459 /* Listed in order of preference. Update t4_sysctls too if you change these */ 460 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 461 462 /* 463 * Egress Queue: driver is producer, T4 is consumer. 464 * 465 * Note: A free list is an egress queue (driver produces the buffers and T4 466 * consumes them) but it's special enough to have its own struct (see sge_fl). 467 */ 468 struct sge_eq { 469 unsigned int flags; /* MUST be first */ 470 unsigned int cntxt_id; /* SGE context id for the eq */ 471 unsigned int abs_id; /* absolute SGE id for the eq */ 472 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 473 uint8_t doorbells; 474 uint8_t tx_chan; /* tx channel used by the eq */ 475 struct mtx eq_lock; 476 477 struct tx_desc *desc; /* KVA of descriptor ring */ 478 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 479 u_int udb_qid; /* relative qid within the doorbell page */ 480 uint16_t sidx; /* index of the entry with the status page */ 481 uint16_t cidx; /* consumer idx (desc idx) */ 482 uint16_t pidx; /* producer idx (desc idx) */ 483 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 484 uint16_t dbidx; /* pidx of the most recent doorbell */ 485 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 486 volatile u_int equiq; /* EQUIQ outstanding */ 487 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 488 489 bus_dma_tag_t desc_tag; 490 bus_dmamap_t desc_map; 491 bus_addr_t ba; /* bus address of descriptor ring */ 492 char lockname[16]; 493 }; 494 495 struct rx_buf_info { 496 uma_zone_t zone; /* zone that this cluster comes from */ 497 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 498 * hwsize[hwidx1] = size1. No spare. */ 499 uint16_t size2; /* hwsize[hwidx2] = size2. 500 * spare in cluster = size1 - size2. */ 501 int8_t hwidx1; /* SGE bufsize idx for size1 */ 502 int8_t hwidx2; /* SGE bufsize idx for size2 */ 503 uint8_t type; /* EXT_xxx type of the cluster */ 504 }; 505 506 enum { 507 NUM_MEMWIN = 3, 508 509 MEMWIN0_APERTURE = 2048, 510 MEMWIN0_BASE = 0x1b800, 511 512 MEMWIN1_APERTURE = 32768, 513 MEMWIN1_BASE = 0x28000, 514 515 MEMWIN2_APERTURE_T4 = 65536, 516 MEMWIN2_BASE_T4 = 0x30000, 517 518 MEMWIN2_APERTURE_T5 = 128 * 1024, 519 MEMWIN2_BASE_T5 = 0x60000, 520 }; 521 522 struct memwin { 523 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 524 uint32_t mw_base; /* constant after setup_memwin */ 525 uint32_t mw_aperture; /* ditto */ 526 uint32_t mw_curpos; /* protected by mw_lock */ 527 }; 528 529 enum { 530 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 531 FL_DOOMED = (1 << 1), /* about to be destroyed */ 532 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 533 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 534 }; 535 536 #define FL_RUNNING_LOW(fl) \ 537 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 538 #define FL_NOT_RUNNING_LOW(fl) \ 539 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 540 541 struct sge_fl { 542 struct mtx fl_lock; 543 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 544 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 545 uint16_t zidx; /* refill zone idx */ 546 uint16_t safe_zidx; 547 uint16_t lowat; /* # of buffers <= this means fl needs help */ 548 int flags; 549 uint16_t buf_boundary; 550 551 /* The 16b idx all deal with hw descriptors */ 552 uint16_t dbidx; /* hw pidx after last doorbell */ 553 uint16_t sidx; /* index of status page */ 554 volatile uint16_t hw_cidx; 555 556 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 557 uint32_t cidx; /* consumer index */ 558 uint32_t pidx; /* producer index */ 559 560 uint32_t dbval; 561 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 562 volatile uint32_t *udb; 563 564 uint64_t cl_allocated; /* # of clusters allocated */ 565 uint64_t cl_recycled; /* # of clusters recycled */ 566 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 567 568 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 569 struct mbuf *m0; 570 struct mbuf **pnext; 571 u_int remaining; 572 573 uint16_t qsize; /* # of hw descriptors (status page included) */ 574 uint16_t cntxt_id; /* SGE context id for the freelist */ 575 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 576 bus_dma_tag_t desc_tag; 577 bus_dmamap_t desc_map; 578 char lockname[16]; 579 bus_addr_t ba; /* bus address of descriptor ring */ 580 }; 581 582 struct mp_ring; 583 584 struct txpkts { 585 uint8_t wr_type; /* type 0 or type 1 */ 586 uint8_t npkt; /* # of packets in this work request */ 587 uint8_t len16; /* # of 16B pieces used by this work request */ 588 uint8_t score; 589 uint8_t max_npkt; /* maximum number of packets allowed */ 590 uint16_t plen; /* total payload (sum of all packets) */ 591 592 /* straight from fw_eth_tx_pkts_vm_wr. */ 593 __u8 ethmacdst[6]; 594 __u8 ethmacsrc[6]; 595 __be16 ethtype; 596 __be16 vlantci; 597 598 struct mbuf *mb[15]; 599 }; 600 601 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 602 struct sge_txq { 603 struct sge_eq eq; /* MUST be first */ 604 605 if_t ifp; /* the interface this txq belongs to */ 606 struct mp_ring *r; /* tx software ring */ 607 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 608 struct sglist *gl; 609 __be32 cpl_ctrl0; /* for convenience */ 610 int tc_idx; /* traffic class */ 611 uint64_t last_tx; /* cycle count when eth_tx was last called */ 612 struct txpkts txp; 613 614 struct task tx_reclaim_task; 615 /* stats for common events first */ 616 617 uint64_t txcsum; /* # of times hardware assisted with checksum */ 618 uint64_t tso_wrs; /* # of TSO work requests */ 619 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 620 uint64_t imm_wrs; /* # of work requests with immediate data */ 621 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 622 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 623 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 624 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 625 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 626 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 627 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 628 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 629 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 630 uint64_t vxlan_txcsum; 631 632 uint64_t kern_tls_records; 633 uint64_t kern_tls_short; 634 uint64_t kern_tls_partial; 635 uint64_t kern_tls_full; 636 uint64_t kern_tls_octets; 637 uint64_t kern_tls_waste; 638 uint64_t kern_tls_options; 639 uint64_t kern_tls_header; 640 uint64_t kern_tls_fin; 641 uint64_t kern_tls_fin_short; 642 uint64_t kern_tls_cbc; 643 uint64_t kern_tls_gcm; 644 645 /* stats for not-that-common events */ 646 647 /* Optional scratch space for constructing work requests. */ 648 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 649 } __aligned(CACHE_LINE_SIZE); 650 651 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 652 struct sge_rxq { 653 struct sge_iq iq; /* MUST be first */ 654 struct sge_fl fl; /* MUST follow iq */ 655 656 if_t ifp; /* the interface this rxq belongs to */ 657 struct lro_ctrl lro; /* LRO state */ 658 659 /* stats for common events first */ 660 661 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 662 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 663 uint64_t vxlan_rxcsum; 664 665 /* stats for not-that-common events */ 666 667 } __aligned(CACHE_LINE_SIZE); 668 669 static inline struct sge_rxq * 670 iq_to_rxq(struct sge_iq *iq) 671 { 672 673 return (__containerof(iq, struct sge_rxq, iq)); 674 } 675 676 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 677 struct sge_ofld_rxq { 678 struct sge_iq iq; /* MUST be first */ 679 struct sge_fl fl; /* MUST follow iq */ 680 counter_u64_t rx_iscsi_ddp_setup_ok; 681 counter_u64_t rx_iscsi_ddp_setup_error; 682 uint64_t rx_iscsi_ddp_pdus; 683 uint64_t rx_iscsi_ddp_octets; 684 uint64_t rx_iscsi_fl_pdus; 685 uint64_t rx_iscsi_fl_octets; 686 uint64_t rx_iscsi_padding_errors; 687 uint64_t rx_iscsi_header_digest_errors; 688 uint64_t rx_iscsi_data_digest_errors; 689 uint64_t rx_aio_ddp_jobs; 690 uint64_t rx_aio_ddp_octets; 691 u_long rx_toe_tls_records; 692 u_long rx_toe_tls_octets; 693 } __aligned(CACHE_LINE_SIZE); 694 695 static inline struct sge_ofld_rxq * 696 iq_to_ofld_rxq(struct sge_iq *iq) 697 { 698 699 return (__containerof(iq, struct sge_ofld_rxq, iq)); 700 } 701 702 struct wrqe { 703 STAILQ_ENTRY(wrqe) link; 704 struct sge_wrq *wrq; 705 int wr_len; 706 char wr[] __aligned(16); 707 }; 708 709 struct wrq_cookie { 710 TAILQ_ENTRY(wrq_cookie) link; 711 int ndesc; 712 int pidx; 713 }; 714 715 /* 716 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 717 * are of this type. 718 */ 719 struct sge_wrq { 720 struct sge_eq eq; /* MUST be first */ 721 722 struct adapter *adapter; 723 struct task wrq_tx_task; 724 725 /* Tx desc reserved but WR not "committed" yet. */ 726 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 727 728 /* List of WRs ready to go out as soon as descriptors are available. */ 729 STAILQ_HEAD(, wrqe) wr_list; 730 u_int nwr_pending; 731 u_int ndesc_needed; 732 733 /* stats for common events first */ 734 735 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 736 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 737 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 738 739 /* stats for not-that-common events */ 740 741 /* 742 * Scratch space for work requests that wrap around after reaching the 743 * status page, and some information about the last WR that used it. 744 */ 745 uint16_t ss_pidx; 746 uint16_t ss_len; 747 uint8_t ss[SGE_MAX_WR_LEN]; 748 749 } __aligned(CACHE_LINE_SIZE); 750 751 /* ofld_txq: SGE egress queue + miscellaneous items */ 752 struct sge_ofld_txq { 753 struct sge_wrq wrq; 754 counter_u64_t tx_iscsi_pdus; 755 counter_u64_t tx_iscsi_octets; 756 counter_u64_t tx_iscsi_iso_wrs; 757 counter_u64_t tx_aio_jobs; 758 counter_u64_t tx_aio_octets; 759 counter_u64_t tx_toe_tls_records; 760 counter_u64_t tx_toe_tls_octets; 761 } __aligned(CACHE_LINE_SIZE); 762 763 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 764 struct sge_nm_rxq { 765 /* Items used by the driver rx ithread are in this cacheline. */ 766 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 767 u_int nid; /* netmap ring # for this queue */ 768 struct vi_info *vi; 769 770 struct iq_desc *iq_desc; 771 uint16_t iq_abs_id; 772 uint16_t iq_cntxt_id; 773 uint16_t iq_cidx; 774 uint16_t iq_sidx; 775 uint8_t iq_gen; 776 uint32_t fl_sidx; 777 778 /* Items used by netmap rxsync are in this cacheline. */ 779 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 780 uint16_t fl_cntxt_id; 781 uint32_t fl_pidx; 782 uint32_t fl_sidx2; /* copy of fl_sidx */ 783 uint32_t fl_db_val; 784 u_int fl_db_saved; 785 u_int fl_db_threshold; /* in descriptors */ 786 u_int fl_hwidx:4; 787 788 /* 789 * fl_cidx is used by both the ithread and rxsync, the rest are not used 790 * in the rx fast path. 791 */ 792 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 793 794 bus_dma_tag_t iq_desc_tag; 795 bus_dmamap_t iq_desc_map; 796 bus_addr_t iq_ba; 797 int intr_idx; 798 799 bus_dma_tag_t fl_desc_tag; 800 bus_dmamap_t fl_desc_map; 801 bus_addr_t fl_ba; 802 }; 803 804 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 805 struct sge_nm_txq { 806 struct tx_desc *desc; 807 uint16_t cidx; 808 uint16_t pidx; 809 uint16_t sidx; 810 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 811 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 812 uint16_t dbidx; /* pidx of the most recent doorbell */ 813 uint8_t doorbells; 814 volatile uint32_t *udb; 815 u_int udb_qid; 816 u_int cntxt_id; 817 __be32 cpl_ctrl0; /* for convenience */ 818 __be32 op_pkd; /* ditto */ 819 u_int nid; /* netmap ring # for this queue */ 820 821 /* infrequently used items after this */ 822 823 bus_dma_tag_t desc_tag; 824 bus_dmamap_t desc_map; 825 bus_addr_t ba; 826 int iqidx; 827 } __aligned(CACHE_LINE_SIZE); 828 829 struct sge { 830 int nrxq; /* total # of Ethernet rx queues */ 831 int ntxq; /* total # of Ethernet tx queues */ 832 int nofldrxq; /* total # of TOE rx queues */ 833 int nofldtxq; /* total # of TOE tx queues */ 834 int nnmrxq; /* total # of netmap rx queues */ 835 int nnmtxq; /* total # of netmap tx queues */ 836 int niq; /* total # of ingress queues */ 837 int neq; /* total # of egress queues */ 838 839 struct sge_iq fwq; /* Firmware event queue */ 840 struct sge_wrq *ctrlq; /* Control queues */ 841 struct sge_txq *txq; /* NIC tx queues */ 842 struct sge_rxq *rxq; /* NIC rx queues */ 843 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 844 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 845 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 846 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 847 848 uint16_t iq_start; /* first cntxt_id */ 849 uint16_t iq_base; /* first abs_id */ 850 int eq_start; /* first cntxt_id */ 851 int eq_base; /* first abs_id */ 852 int iqmap_sz; 853 int eqmap_sz; 854 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 855 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 856 857 int8_t safe_zidx; 858 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 859 }; 860 861 struct devnames { 862 const char *nexus_name; 863 const char *ifnet_name; 864 const char *vi_ifnet_name; 865 const char *pf03_drv_name; 866 const char *vf_nexus_name; 867 const char *vf_ifnet_name; 868 }; 869 870 struct clip_entry; 871 872 #define CNT_CAL_INFO 3 873 struct clock_sync { 874 uint64_t hw_cur; 875 uint64_t hw_prev; 876 sbintime_t sbt_cur; 877 sbintime_t sbt_prev; 878 seqc_t gen; 879 }; 880 881 struct adapter { 882 SLIST_ENTRY(adapter) link; 883 device_t dev; 884 struct cdev *cdev; 885 const struct devnames *names; 886 887 /* PCIe register resources */ 888 int regs_rid; 889 struct resource *regs_res; 890 int msix_rid; 891 struct resource *msix_res; 892 bus_space_handle_t bh; 893 bus_space_tag_t bt; 894 bus_size_t mmio_len; 895 int udbs_rid; 896 struct resource *udbs_res; 897 volatile uint8_t *udbs_base; 898 899 unsigned int pf; 900 unsigned int mbox; 901 unsigned int vpd_busy; 902 unsigned int vpd_flag; 903 904 /* Interrupt information */ 905 int intr_type; 906 int intr_count; 907 struct irq { 908 struct resource *res; 909 int rid; 910 void *tag; 911 struct sge_rxq *rxq; 912 struct sge_nm_rxq *nm_rxq; 913 } __aligned(CACHE_LINE_SIZE) *irq; 914 int sge_gts_reg; 915 int sge_kdoorbell_reg; 916 917 bus_dma_tag_t dmat; /* Parent DMA tag */ 918 919 struct sge sge; 920 int lro_timeout; 921 int sc_do_rxcopy; 922 923 int vxlan_port; 924 u_int vxlan_refcount; 925 int rawf_base; 926 int nrawf; 927 928 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 929 struct port_info *port[MAX_NPORTS]; 930 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 931 932 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 933 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 934 u_long clip_mask; 935 int clip_gen; 936 struct timeout_task clip_task; 937 938 void *tom_softc; /* (struct tom_data *) */ 939 struct tom_tunables tt; 940 struct t4_offload_policy *policy; 941 struct rwlock policy_lock; 942 943 void *iwarp_softc; /* (struct c4iw_dev *) */ 944 struct iw_tunables iwt; 945 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 946 struct l2t_data *l2t; /* L2 table */ 947 struct smt_data *smt; /* Source MAC Table */ 948 struct tid_info tids; 949 vmem_t *key_map; 950 struct tls_tunables tlst; 951 952 uint8_t doorbells; 953 int offload_map; /* port_id's with IFCAP_TOE enabled */ 954 int bt_map; /* tx_chan's with BASE-T */ 955 int active_ulds; /* ULDs activated on this adapter */ 956 int flags; 957 int debug_flags; 958 int error_flags; /* Used by error handler and live reset. */ 959 960 char ifp_lockname[16]; 961 struct mtx ifp_lock; 962 if_t ifp; /* tracer ifp */ 963 struct ifmedia media; 964 int traceq; /* iq used by all tracers, -1 if none */ 965 int tracer_valid; /* bitmap of valid tracers */ 966 int tracer_enabled; /* bitmap of enabled tracers */ 967 968 char fw_version[16]; 969 char tp_version[16]; 970 char er_version[16]; 971 char bs_version[16]; 972 char cfg_file[32]; 973 u_int cfcsum; 974 struct adapter_params params; 975 const struct chip_params *chip_params; 976 struct t4_virt_res vres; 977 978 uint16_t nbmcaps; 979 uint16_t linkcaps; 980 uint16_t switchcaps; 981 uint16_t niccaps; 982 uint16_t toecaps; 983 uint16_t rdmacaps; 984 uint16_t cryptocaps; 985 uint16_t iscsicaps; 986 uint16_t fcoecaps; 987 988 struct sysctl_ctx_list ctx; 989 struct sysctl_oid *ctrlq_oid; 990 struct sysctl_oid *fwq_oid; 991 992 struct mtx sc_lock; 993 char lockname[16]; 994 995 /* Starving free lists */ 996 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 997 TAILQ_HEAD(, sge_fl) sfl; 998 struct callout sfl_callout; 999 struct callout cal_callout; 1000 struct clock_sync cal_info[CNT_CAL_INFO]; 1001 int cal_current; 1002 int cal_count; 1003 uint32_t cal_gen; 1004 1005 /* 1006 * Driver code that can run when the adapter is suspended must use this 1007 * lock or a synchronized_op and check for HW_OFF_LIMITS before 1008 * accessing hardware. 1009 * 1010 * XXX: could be changed to rwlock. wlock in suspend/resume and for 1011 * indirect register access, rlock everywhere else. 1012 */ 1013 struct mtx reg_lock; 1014 1015 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 1016 1017 struct mtx tc_lock; 1018 struct task tc_task; 1019 1020 struct task fatal_error_task; 1021 struct task reset_task; 1022 const void *reset_thread; 1023 int num_resets; 1024 int incarnation; 1025 1026 const char *last_op; 1027 const void *last_op_thr; 1028 int last_op_flags; 1029 1030 int swintr; 1031 int sensor_resets; 1032 1033 struct callout ktls_tick; 1034 }; 1035 1036 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1037 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1038 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1039 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1040 1041 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1042 KASSERT(IS_BUSY(sc) && \ 1043 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1044 ("%s: operation not synchronized.", __func__)) 1045 1046 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1047 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1048 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1049 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1050 1051 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1052 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1053 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1054 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1055 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1056 1057 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1058 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1059 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1060 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1061 1062 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1063 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1064 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1065 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1066 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1067 1068 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1069 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1070 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1071 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1072 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1073 1074 #define for_each_txq(vi, iter, q) \ 1075 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1076 iter < vi->ntxq; ++iter, ++q) 1077 #define for_each_rxq(vi, iter, q) \ 1078 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1079 iter < vi->nrxq; ++iter, ++q) 1080 #define for_each_ofld_txq(vi, iter, q) \ 1081 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1082 iter < vi->nofldtxq; ++iter, ++q) 1083 #define for_each_ofld_rxq(vi, iter, q) \ 1084 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1085 iter < vi->nofldrxq; ++iter, ++q) 1086 #define for_each_nm_txq(vi, iter, q) \ 1087 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1088 iter < vi->nnmtxq; ++iter, ++q) 1089 #define for_each_nm_rxq(vi, iter, q) \ 1090 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1091 iter < vi->nnmrxq; ++iter, ++q) 1092 #define for_each_vi(_pi, _iter, _vi) \ 1093 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1094 ++(_iter), ++(_vi)) 1095 1096 #define IDXINCR(idx, incr, wrap) do { \ 1097 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1098 } while (0) 1099 #define IDXDIFF(head, tail, wrap) \ 1100 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1101 1102 /* One for errors, one for firmware events */ 1103 #define T4_EXTRA_INTR 2 1104 1105 /* One for firmware events */ 1106 #define T4VF_EXTRA_INTR 1 1107 1108 static inline int 1109 forwarding_intr_to_fwq(struct adapter *sc) 1110 { 1111 1112 return (sc->intr_count == 1); 1113 } 1114 1115 /* Works reliably inside a sync_op or with reg_lock held. */ 1116 static inline bool 1117 hw_off_limits(struct adapter *sc) 1118 { 1119 int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1120 1121 return (__predict_false(off_limits != 0)); 1122 } 1123 1124 static inline int 1125 mbuf_nsegs(struct mbuf *m) 1126 { 1127 M_ASSERTPKTHDR(m); 1128 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 1129 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1130 1131 return (m->m_pkthdr.inner_l5hlen); 1132 } 1133 1134 static inline void 1135 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1136 { 1137 M_ASSERTPKTHDR(m); 1138 m->m_pkthdr.inner_l5hlen = nsegs; 1139 } 1140 1141 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 1142 #define MC_NOMAP 0x01 1143 #define MC_RAW_WR 0x02 1144 #define MC_TLS 0x04 1145 1146 static inline int 1147 mbuf_cflags(struct mbuf *m) 1148 { 1149 M_ASSERTPKTHDR(m); 1150 return (m->m_pkthdr.PH_loc.eight[4]); 1151 } 1152 1153 static inline void 1154 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 1155 { 1156 M_ASSERTPKTHDR(m); 1157 m->m_pkthdr.PH_loc.eight[4] = flags; 1158 } 1159 1160 static inline int 1161 mbuf_len16(struct mbuf *m) 1162 { 1163 int n; 1164 1165 M_ASSERTPKTHDR(m); 1166 n = m->m_pkthdr.PH_loc.eight[0]; 1167 if (!(mbuf_cflags(m) & MC_TLS)) 1168 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1169 1170 return (n); 1171 } 1172 1173 static inline void 1174 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1175 { 1176 M_ASSERTPKTHDR(m); 1177 if (!(mbuf_cflags(m) & MC_TLS)) 1178 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 1179 m->m_pkthdr.PH_loc.eight[0] = len16; 1180 } 1181 1182 static inline uint32_t 1183 t4_read_reg(struct adapter *sc, uint32_t reg) 1184 { 1185 if (hw_off_limits(sc)) 1186 MPASS(curthread == sc->reset_thread); 1187 return bus_space_read_4(sc->bt, sc->bh, reg); 1188 } 1189 1190 static inline void 1191 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1192 { 1193 if (hw_off_limits(sc)) 1194 MPASS(curthread == sc->reset_thread); 1195 bus_space_write_4(sc->bt, sc->bh, reg, val); 1196 } 1197 1198 static inline uint64_t 1199 t4_read_reg64(struct adapter *sc, uint32_t reg) 1200 { 1201 if (hw_off_limits(sc)) 1202 MPASS(curthread == sc->reset_thread); 1203 #ifdef __LP64__ 1204 return bus_space_read_8(sc->bt, sc->bh, reg); 1205 #else 1206 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1207 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1208 1209 #endif 1210 } 1211 1212 static inline void 1213 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1214 { 1215 if (hw_off_limits(sc)) 1216 MPASS(curthread == sc->reset_thread); 1217 #ifdef __LP64__ 1218 bus_space_write_8(sc->bt, sc->bh, reg, val); 1219 #else 1220 bus_space_write_4(sc->bt, sc->bh, reg, val); 1221 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1222 #endif 1223 } 1224 1225 static inline void 1226 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1227 { 1228 if (hw_off_limits(sc)) 1229 MPASS(curthread == sc->reset_thread); 1230 *val = pci_read_config(sc->dev, reg, 1); 1231 } 1232 1233 static inline void 1234 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1235 { 1236 if (hw_off_limits(sc)) 1237 MPASS(curthread == sc->reset_thread); 1238 pci_write_config(sc->dev, reg, val, 1); 1239 } 1240 1241 static inline void 1242 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1243 { 1244 1245 if (hw_off_limits(sc)) 1246 MPASS(curthread == sc->reset_thread); 1247 *val = pci_read_config(sc->dev, reg, 2); 1248 } 1249 1250 static inline void 1251 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1252 { 1253 if (hw_off_limits(sc)) 1254 MPASS(curthread == sc->reset_thread); 1255 pci_write_config(sc->dev, reg, val, 2); 1256 } 1257 1258 static inline void 1259 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1260 { 1261 if (hw_off_limits(sc)) 1262 MPASS(curthread == sc->reset_thread); 1263 *val = pci_read_config(sc->dev, reg, 4); 1264 } 1265 1266 static inline void 1267 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1268 { 1269 if (hw_off_limits(sc)) 1270 MPASS(curthread == sc->reset_thread); 1271 pci_write_config(sc->dev, reg, val, 4); 1272 } 1273 1274 static inline struct port_info * 1275 adap2pinfo(struct adapter *sc, int idx) 1276 { 1277 1278 return (sc->port[idx]); 1279 } 1280 1281 static inline void 1282 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1283 { 1284 1285 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1286 } 1287 1288 static inline int 1289 tx_resume_threshold(struct sge_eq *eq) 1290 { 1291 1292 /* not quite the same as qsize / 4, but this will do. */ 1293 return (eq->sidx / 4); 1294 } 1295 1296 static inline int 1297 t4_use_ldst(struct adapter *sc) 1298 { 1299 1300 #ifdef notyet 1301 return (sc->flags & FW_OK || !sc->use_bd); 1302 #else 1303 return (0); 1304 #endif 1305 } 1306 1307 static inline void 1308 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1309 const char *msg, const __be64 *const p, const bool err) 1310 { 1311 1312 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1313 return; 1314 if (p != NULL) { 1315 log(err ? LOG_ERR : LOG_DEBUG, 1316 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1317 "%016llx %016llx %016llx %016llx\n", 1318 device_get_nameunit(sc->dev), mbox, msg, 1319 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1320 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1321 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1322 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1323 } else { 1324 log(err ? LOG_ERR : LOG_DEBUG, 1325 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1326 "%016llx %016llx %016llx %016llx\n", 1327 device_get_nameunit(sc->dev), mbox, msg, 1328 (long long)t4_read_reg64(sc, reg), 1329 (long long)t4_read_reg64(sc, reg + 8), 1330 (long long)t4_read_reg64(sc, reg + 16), 1331 (long long)t4_read_reg64(sc, reg + 24), 1332 (long long)t4_read_reg64(sc, reg + 32), 1333 (long long)t4_read_reg64(sc, reg + 40), 1334 (long long)t4_read_reg64(sc, reg + 48), 1335 (long long)t4_read_reg64(sc, reg + 56)); 1336 } 1337 } 1338 1339 /* t4_main.c */ 1340 extern int t4_ntxq; 1341 extern int t4_nrxq; 1342 extern int t4_intr_types; 1343 extern int t4_tmr_idx; 1344 extern int t4_pktc_idx; 1345 extern unsigned int t4_qsize_rxq; 1346 extern unsigned int t4_qsize_txq; 1347 extern device_method_t cxgbe_methods[]; 1348 1349 int t4_os_find_pci_capability(struct adapter *, int); 1350 int t4_os_pci_save_state(struct adapter *); 1351 int t4_os_pci_restore_state(struct adapter *); 1352 void t4_os_portmod_changed(struct port_info *); 1353 void t4_os_link_changed(struct port_info *); 1354 void t4_iterate(void (*)(struct adapter *, void *), void *); 1355 void t4_init_devnames(struct adapter *); 1356 void t4_add_adapter(struct adapter *); 1357 int t4_detach_common(device_t); 1358 int t4_map_bars_0_and_4(struct adapter *); 1359 int t4_map_bar_2(struct adapter *); 1360 int t4_setup_intr_handlers(struct adapter *); 1361 void t4_sysctls(struct adapter *); 1362 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1363 void end_synchronized_op(struct adapter *, int); 1364 void begin_vi_detach(struct adapter *, struct vi_info *); 1365 void end_vi_detach(struct adapter *, struct vi_info *); 1366 int update_mac_settings(if_t, int); 1367 int adapter_init(struct adapter *); 1368 int vi_init(struct vi_info *); 1369 void vi_sysctls(struct vi_info *); 1370 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1371 int alloc_atid(struct adapter *, void *); 1372 void *lookup_atid(struct adapter *, int); 1373 void free_atid(struct adapter *, int); 1374 void release_tid(struct adapter *, int, struct sge_wrq *); 1375 int cxgbe_media_change(if_t); 1376 void cxgbe_media_status(if_t, struct ifmediareq *); 1377 void t4_os_cim_err(struct adapter *); 1378 1379 #ifdef KERN_TLS 1380 /* t6_kern_tls.c */ 1381 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1382 struct m_snd_tag **); 1383 void t6_ktls_modload(void); 1384 void t6_ktls_modunload(void); 1385 int t6_ktls_try(if_t, struct socket *, struct ktls_session *); 1386 int t6_ktls_parse_pkt(struct mbuf *); 1387 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1388 #endif 1389 1390 /* t4_keyctx.c */ 1391 struct auth_hash; 1392 union authctx; 1393 #ifdef KERN_TLS 1394 struct ktls_session; 1395 struct tls_key_req; 1396 struct tls_keyctx; 1397 #endif 1398 1399 void t4_aes_getdeckey(void *, const void *, unsigned int); 1400 void t4_copy_partial_hash(int, union authctx *, void *); 1401 void t4_init_gmac_hash(const char *, int, char *); 1402 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1403 char *); 1404 #ifdef KERN_TLS 1405 u_int t4_tls_key_info_size(const struct ktls_session *); 1406 int t4_tls_proto_ver(const struct ktls_session *); 1407 int t4_tls_cipher_mode(const struct ktls_session *); 1408 int t4_tls_auth_mode(const struct ktls_session *); 1409 int t4_tls_hmac_ctrl(const struct ktls_session *); 1410 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1411 int t4_alloc_tls_keyid(struct adapter *); 1412 void t4_free_tls_keyid(struct adapter *, int); 1413 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1414 struct tls_key_req *); 1415 #endif 1416 1417 #ifdef DEV_NETMAP 1418 /* t4_netmap.c */ 1419 struct sge_nm_rxq; 1420 void cxgbe_nm_attach(struct vi_info *); 1421 void cxgbe_nm_detach(struct vi_info *); 1422 void service_nm_rxq(struct sge_nm_rxq *); 1423 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1424 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1425 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1426 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1427 #endif 1428 1429 /* t4_sge.c */ 1430 void t4_sge_modload(void); 1431 void t4_sge_modunload(void); 1432 uint64_t t4_sge_extfree_refs(void); 1433 void t4_tweak_chip_settings(struct adapter *); 1434 int t4_verify_chip_settings(struct adapter *); 1435 void t4_init_rx_buf_info(struct adapter *); 1436 int t4_create_dma_tag(struct adapter *); 1437 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1438 struct sysctl_oid_list *); 1439 int t4_destroy_dma_tag(struct adapter *); 1440 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1441 bus_addr_t *, void **); 1442 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1443 void *); 1444 void free_fl_buffers(struct adapter *, struct sge_fl *); 1445 int t4_setup_adapter_queues(struct adapter *); 1446 int t4_teardown_adapter_queues(struct adapter *); 1447 int t4_setup_vi_queues(struct vi_info *); 1448 int t4_teardown_vi_queues(struct vi_info *); 1449 void t4_intr_all(void *); 1450 void t4_intr(void *); 1451 #ifdef DEV_NETMAP 1452 void t4_nm_intr(void *); 1453 void t4_vi_intr(void *); 1454 #endif 1455 void t4_intr_err(void *); 1456 void t4_intr_evt(void *); 1457 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1458 void t4_update_fl_bufsize(if_t); 1459 struct mbuf *alloc_wr_mbuf(int, int); 1460 int parse_pkt(struct mbuf **, bool); 1461 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1462 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1463 int t4_sge_set_conm_context(struct adapter *, int, int, int); 1464 void t4_register_an_handler(an_handler_t); 1465 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1466 void t4_register_cpl_handler(int, cpl_handler_t); 1467 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1468 #ifdef RATELIMIT 1469 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1470 #endif 1471 1472 /* t4_tracer.c */ 1473 struct t4_tracer; 1474 void t4_tracer_modload(void); 1475 void t4_tracer_modunload(void); 1476 void t4_tracer_port_detach(struct adapter *); 1477 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1478 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1479 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1480 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1481 1482 /* t4_sched.c */ 1483 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1484 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1485 int t4_init_tx_sched(struct adapter *); 1486 int t4_free_tx_sched(struct adapter *); 1487 void t4_update_tx_sched(struct adapter *); 1488 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1489 void t4_release_cl_rl(struct adapter *, int, int); 1490 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1491 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1492 #ifdef RATELIMIT 1493 void t4_init_etid_table(struct adapter *); 1494 void t4_free_etid_table(struct adapter *); 1495 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1496 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1497 struct m_snd_tag **); 1498 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1499 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *); 1500 #endif 1501 1502 /* t4_filter.c */ 1503 int get_filter_mode(struct adapter *, uint32_t *); 1504 int set_filter_mode(struct adapter *, uint32_t); 1505 int set_filter_mask(struct adapter *, uint32_t); 1506 int get_filter(struct adapter *, struct t4_filter *); 1507 int set_filter(struct adapter *, struct t4_filter *); 1508 int del_filter(struct adapter *, struct t4_filter *); 1509 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1510 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1511 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1512 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1513 void free_hftid_hash(struct tid_info *); 1514 1515 static inline struct wrqe * 1516 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1517 { 1518 int len = offsetof(struct wrqe, wr) + wr_len; 1519 struct wrqe *wr; 1520 1521 wr = malloc(len, M_CXGBE, M_NOWAIT); 1522 if (__predict_false(wr == NULL)) 1523 return (NULL); 1524 wr->wr_len = wr_len; 1525 wr->wrq = wrq; 1526 return (wr); 1527 } 1528 1529 static inline void * 1530 wrtod(struct wrqe *wr) 1531 { 1532 return (&wr->wr[0]); 1533 } 1534 1535 static inline void 1536 free_wrqe(struct wrqe *wr) 1537 { 1538 free(wr, M_CXGBE); 1539 } 1540 1541 static inline void 1542 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1543 { 1544 struct sge_wrq *wrq = wr->wrq; 1545 1546 TXQ_LOCK(wrq); 1547 t4_wrq_tx_locked(sc, wrq, wr); 1548 TXQ_UNLOCK(wrq); 1549 } 1550 1551 static inline int 1552 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1553 int len) 1554 { 1555 1556 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1557 } 1558 1559 static inline int 1560 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1561 const uint32_t *val, int len) 1562 { 1563 1564 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1565 } 1566 1567 /* Number of len16 -> number of descriptors */ 1568 static inline int 1569 tx_len16_to_desc(int len16) 1570 { 1571 1572 return (howmany(len16, EQ_ESIZE / 16)); 1573 } 1574 #endif 1575