1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/bus.h> 35 #include <sys/rman.h> 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcireg.h> 40 #include <machine/bus.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_media.h> 46 #include <netinet/tcp_lro.h> 47 48 #include "offload.h" 49 #include "common/t4fw_interface.h" 50 51 #define T4_FWNAME "t4fw" 52 53 MALLOC_DECLARE(M_CXGBE); 54 #define CXGBE_UNIMPLEMENTED(s) \ 55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56 57 #if defined(__i386__) || defined(__amd64__) 58 static __inline void 59 prefetch(void *x) 60 { 61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62 } 63 #else 64 #define prefetch(x) 65 #endif 66 67 #ifdef __amd64__ 68 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 69 static __inline uint64_t 70 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 71 bus_size_t offset) 72 { 73 KASSERT(tag == X86_BUS_SPACE_MEM, 74 ("%s: can only handle mem space", __func__)); 75 76 return (*(volatile uint64_t *)(handle + offset)); 77 } 78 79 static __inline void 80 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 81 bus_size_t offset, uint64_t value) 82 { 83 KASSERT(tag == X86_BUS_SPACE_MEM, 84 ("%s: can only handle mem space", __func__)); 85 86 *(volatile uint64_t *)(bsh + offset) = value; 87 } 88 #else 89 static __inline uint64_t 90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 91 bus_size_t offset) 92 { 93 return (uint64_t)bus_space_read_4(tag, handle, offset) + 94 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 95 } 96 97 static __inline void 98 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 99 bus_size_t offset, uint64_t value) 100 { 101 bus_space_write_4(tag, bsh, offset, value); 102 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 103 } 104 #endif 105 106 struct adapter; 107 typedef struct adapter adapter_t; 108 109 enum { 110 FW_IQ_QSIZE = 256, 111 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 112 113 CTRL_EQ_QSIZE = 128, 114 CTRL_EQ_ESIZE = 64, 115 116 RX_IQ_QSIZE = 1024, 117 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 118 119 RX_FL_ESIZE = 64, /* 8 64bit addresses */ 120 121 #if MJUMPAGESIZE != MCLBYTES 122 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 123 #else 124 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 125 #endif 126 127 TX_EQ_QSIZE = 1024, 128 TX_EQ_ESIZE = 64, 129 TX_SGL_SEGS = 36, 130 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 131 }; 132 133 enum { 134 /* adapter intr_type */ 135 INTR_INTX = (1 << 0), 136 INTR_MSI = (1 << 1), 137 INTR_MSIX = (1 << 2) 138 }; 139 140 enum { 141 /* adapter flags */ 142 FULL_INIT_DONE = (1 << 0), 143 FW_OK = (1 << 1), 144 INTR_FWD = (1 << 2), 145 146 CXGBE_BUSY = (1 << 9), 147 148 /* port flags */ 149 DOOMED = (1 << 0), 150 VI_ENABLED = (1 << 1), 151 }; 152 153 #define IS_DOOMED(pi) (pi->flags & DOOMED) 154 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 155 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 156 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 157 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 158 159 struct port_info { 160 device_t dev; 161 struct adapter *adapter; 162 163 struct ifnet *ifp; 164 struct ifmedia media; 165 166 struct mtx pi_lock; 167 char lockname[16]; 168 unsigned long flags; 169 int if_flags; 170 171 uint16_t viid; 172 int16_t xact_addr_filt;/* index of exact MAC address filter */ 173 uint16_t rss_size; /* size of VI's RSS table slice */ 174 uint8_t lport; /* associated offload logical port */ 175 int8_t mdio_addr; 176 uint8_t port_type; 177 uint8_t mod_type; 178 uint8_t port_id; 179 uint8_t tx_chan; 180 181 /* These need to be int as they are used in sysctl */ 182 int ntxq; /* # of tx queues */ 183 int first_txq; /* index of first tx queue */ 184 int nrxq; /* # of rx queues */ 185 int first_rxq; /* index of first rx queue */ 186 int tmr_idx; 187 int pktc_idx; 188 int qsize_rxq; 189 int qsize_txq; 190 191 struct link_config link_cfg; 192 struct port_stats stats; 193 194 struct taskqueue *tq; 195 struct callout tick; 196 struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */ 197 struct sysctl_oid *oid_rxq; 198 struct sysctl_oid *oid_txq; 199 200 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 201 }; 202 203 struct fl_sdesc { 204 struct mbuf *m; 205 bus_dmamap_t map; 206 caddr_t cl; 207 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 208 #ifdef INVARIANTS 209 __be64 ba_tag; 210 #endif 211 }; 212 213 struct tx_desc { 214 __be64 flit[8]; 215 }; 216 217 struct tx_map { 218 struct mbuf *m; 219 bus_dmamap_t map; 220 }; 221 222 struct tx_sdesc { 223 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 224 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 225 }; 226 227 typedef void (iq_intr_handler_t)(void *); 228 229 enum { 230 /* iq flags */ 231 IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ 232 IQ_STARTED = (1 << 2), /* started */ 233 234 /* iq state */ 235 IQS_DISABLED = 0, 236 IQS_BUSY = 1, 237 IQS_IDLE = 2, 238 }; 239 240 /* 241 * Ingress Queue: T4 is producer, driver is consumer. 242 */ 243 struct sge_iq { 244 bus_dma_tag_t desc_tag; 245 bus_dmamap_t desc_map; 246 bus_addr_t ba; /* bus address of descriptor ring */ 247 char lockname[16]; 248 uint32_t flags; 249 uint16_t abs_id; /* absolute SGE id for the iq */ 250 int8_t intr_pktc_idx; /* packet count threshold index */ 251 int8_t pad0; 252 iq_intr_handler_t *handler; 253 __be64 *desc; /* KVA of descriptor ring */ 254 255 volatile uint32_t state; 256 struct adapter *adapter; 257 const __be64 *cdesc; /* current descriptor */ 258 uint8_t gen; /* generation bit */ 259 uint8_t intr_params; /* interrupt holdoff parameters */ 260 uint8_t intr_next; /* holdoff for next interrupt */ 261 uint8_t esize; /* size (bytes) of each entry in the queue */ 262 uint16_t qsize; /* size (# of entries) of the queue */ 263 uint16_t cidx; /* consumer index */ 264 uint16_t cntxt_id; /* SGE context id for the iq */ 265 }; 266 267 enum { 268 /* eq flags */ 269 EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ 270 EQ_STARTED = (1 << 2), /* started */ 271 EQ_CRFLUSHED = (1 << 3), /* expecting an update from SGE */ 272 }; 273 274 /* 275 * Egress Queue: driver is producer, T4 is consumer. 276 * 277 * Note: A free list is an egress queue (driver produces the buffers and T4 278 * consumes them) but it's special enough to have its own struct (see sge_fl). 279 */ 280 struct sge_eq { 281 bus_dma_tag_t desc_tag; 282 bus_dmamap_t desc_map; 283 char lockname[16]; 284 unsigned int flags; 285 struct mtx eq_lock; 286 287 struct tx_desc *desc; /* KVA of descriptor ring */ 288 bus_addr_t ba; /* bus address of descriptor ring */ 289 struct sge_qstat *spg; /* status page, for convenience */ 290 uint16_t cap; /* max # of desc, for convenience */ 291 uint16_t avail; /* available descriptors, for convenience */ 292 uint16_t qsize; /* size (# of entries) of the queue */ 293 uint16_t cidx; /* consumer idx (desc idx) */ 294 uint16_t pidx; /* producer idx (desc idx) */ 295 uint16_t pending; /* # of descriptors used since last doorbell */ 296 uint16_t iqid; /* iq that gets egr_update for the eq */ 297 uint32_t cntxt_id; /* SGE context id for the eq */ 298 }; 299 300 struct sge_fl { 301 bus_dma_tag_t desc_tag; 302 bus_dmamap_t desc_map; 303 bus_dma_tag_t tag[FL_BUF_SIZES]; 304 uint8_t tag_idx; 305 struct mtx fl_lock; 306 char lockname[16]; 307 308 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 309 bus_addr_t ba; /* bus address of descriptor ring */ 310 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 311 uint32_t cap; /* max # of buffers, for convenience */ 312 uint16_t qsize; /* size (# of entries) of the queue */ 313 uint16_t cntxt_id; /* SGE context id for the freelist */ 314 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 315 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 316 uint32_t needed; /* # of buffers needed to fill up fl. */ 317 uint32_t pending; /* # of bufs allocated since last doorbell */ 318 unsigned int dmamap_failed; 319 }; 320 321 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 322 struct sge_txq { 323 struct sge_eq eq; /* MUST be first */ 324 325 struct ifnet *ifp; /* the interface this txq belongs to */ 326 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 327 struct buf_ring *br; /* tx buffer ring */ 328 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 329 struct mbuf *m; /* held up due to temporary resource shortage */ 330 struct task resume_tx; 331 332 /* DMA maps used for tx */ 333 struct tx_map *maps; 334 uint32_t map_total; /* # of DMA maps */ 335 uint32_t map_pidx; /* next map to be used */ 336 uint32_t map_cidx; /* reclaimed up to this index */ 337 uint32_t map_avail; /* # of available maps */ 338 339 /* stats for common events first */ 340 341 uint64_t txcsum; /* # of times hardware assisted with checksum */ 342 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 343 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 344 uint64_t imm_wrs; /* # of work requests with immediate data */ 345 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 346 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 347 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 348 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 349 350 /* stats for not-that-common events */ 351 352 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 353 uint32_t no_desc; /* out of hardware descriptors */ 354 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */ 355 } __aligned(CACHE_LINE_SIZE); 356 357 enum { 358 RXQ_LRO_ENABLED = (1 << 0) 359 }; 360 361 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 362 struct sge_rxq { 363 struct sge_iq iq; /* MUST be first */ 364 struct sge_fl fl; 365 366 struct ifnet *ifp; /* the interface this rxq belongs to */ 367 unsigned int flags; 368 #ifdef INET 369 struct lro_ctrl lro; /* LRO state */ 370 #endif 371 372 /* stats for common events first */ 373 374 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 375 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 376 377 /* stats for not-that-common events */ 378 379 } __aligned(CACHE_LINE_SIZE); 380 381 /* ctrlq: SGE egress queue + stats for control queue */ 382 struct sge_ctrlq { 383 struct sge_eq eq; /* MUST be first */ 384 385 /* stats for common events first */ 386 387 uint64_t total_wrs; /* # of work requests sent down this queue */ 388 389 /* stats for not-that-common events */ 390 391 uint32_t no_desc; /* out of hardware descriptors */ 392 uint32_t too_long; /* WR longer than hardware max */ 393 } __aligned(CACHE_LINE_SIZE); 394 395 struct sge { 396 uint16_t timer_val[SGE_NTIMERS]; 397 uint8_t counter_val[SGE_NCOUNTERS]; 398 399 int nrxq; /* total rx queues (all ports and the rest) */ 400 int ntxq; /* total tx queues (all ports and the rest) */ 401 int niq; /* total ingress queues */ 402 int neq; /* total egress queues */ 403 404 struct sge_iq fwq; /* Firmware event queue */ 405 struct sge_ctrlq *ctrlq;/* Control queues */ 406 struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */ 407 struct sge_txq *txq; /* NIC tx queues */ 408 struct sge_rxq *rxq; /* NIC rx queues */ 409 410 uint16_t iq_start; 411 int eq_start; 412 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 413 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 414 }; 415 416 struct adapter { 417 device_t dev; 418 struct cdev *cdev; 419 420 /* PCIe register resources */ 421 int regs_rid; 422 struct resource *regs_res; 423 int msix_rid; 424 struct resource *msix_res; 425 bus_space_handle_t bh; 426 bus_space_tag_t bt; 427 bus_size_t mmio_len; 428 429 unsigned int pf; 430 unsigned int mbox; 431 432 /* Interrupt information */ 433 int intr_type; 434 int intr_count; 435 struct irq { 436 struct resource *res; 437 int rid; 438 void *tag; 439 } *irq; 440 441 bus_dma_tag_t dmat; /* Parent DMA tag */ 442 443 struct sge sge; 444 445 struct port_info *port[MAX_NPORTS]; 446 uint8_t chan_map[NCHAN]; 447 448 struct tid_info tids; 449 450 int registered_device_map; 451 int open_device_map; 452 int flags; 453 454 char fw_version[32]; 455 struct adapter_params params; 456 struct t4_virt_res vres; 457 458 struct sysctl_ctx_list ctx; /* from first_port_up to last_port_down */ 459 struct sysctl_oid *oid_ctrlq; 460 461 struct mtx sc_lock; 462 char lockname[16]; 463 }; 464 465 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 466 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 467 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 468 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 469 470 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 471 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 472 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 473 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 474 475 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 476 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 477 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 478 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 479 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 480 481 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 482 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 483 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 484 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 485 486 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 487 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 488 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 489 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 490 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 491 492 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 493 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 494 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 495 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 496 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 497 498 #define for_each_txq(pi, iter, txq) \ 499 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 500 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 501 #define for_each_rxq(pi, iter, rxq) \ 502 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 503 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 504 505 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 506 507 static inline uint32_t 508 t4_read_reg(struct adapter *sc, uint32_t reg) 509 { 510 return bus_space_read_4(sc->bt, sc->bh, reg); 511 } 512 513 static inline void 514 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 515 { 516 bus_space_write_4(sc->bt, sc->bh, reg, val); 517 } 518 519 static inline uint64_t 520 t4_read_reg64(struct adapter *sc, uint32_t reg) 521 { 522 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 523 } 524 525 static inline void 526 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 527 { 528 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 529 } 530 531 static inline void 532 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 533 { 534 *val = pci_read_config(sc->dev, reg, 1); 535 } 536 537 static inline void 538 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 539 { 540 pci_write_config(sc->dev, reg, val, 1); 541 } 542 543 static inline void 544 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 545 { 546 *val = pci_read_config(sc->dev, reg, 2); 547 } 548 549 static inline void 550 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 551 { 552 pci_write_config(sc->dev, reg, val, 2); 553 } 554 555 static inline void 556 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 557 { 558 *val = pci_read_config(sc->dev, reg, 4); 559 } 560 561 static inline void 562 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 563 { 564 pci_write_config(sc->dev, reg, val, 4); 565 } 566 567 static inline struct port_info * 568 adap2pinfo(struct adapter *sc, int idx) 569 { 570 return (sc->port[idx]); 571 } 572 573 static inline void 574 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 575 { 576 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 577 } 578 579 static inline bool is_10G_port(const struct port_info *pi) 580 { 581 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 582 } 583 584 /* t4_main.c */ 585 void cxgbe_txq_start(void *, int); 586 int t4_os_find_pci_capability(struct adapter *, int); 587 int t4_os_pci_save_state(struct adapter *); 588 int t4_os_pci_restore_state(struct adapter *); 589 void t4_os_portmod_changed(const struct adapter *, int); 590 void t4_os_link_changed(struct adapter *, int, int); 591 592 /* t4_sge.c */ 593 void t4_sge_modload(void); 594 void t4_sge_init(struct adapter *); 595 int t4_create_dma_tag(struct adapter *); 596 int t4_destroy_dma_tag(struct adapter *); 597 int t4_setup_adapter_queues(struct adapter *); 598 int t4_teardown_adapter_queues(struct adapter *); 599 int t4_setup_eth_queues(struct port_info *); 600 int t4_teardown_eth_queues(struct port_info *); 601 void t4_intr_all(void *); 602 void t4_intr_fwd(void *); 603 void t4_intr_err(void *); 604 void t4_intr_evt(void *); 605 void t4_intr_data(void *); 606 void t4_evt_rx(void *); 607 void t4_eth_rx(void *); 608 int t4_mgmt_tx(struct adapter *, struct mbuf *); 609 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 610 void t4_update_fl_bufsize(struct ifnet *); 611 612 #endif 613