1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/types.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/rwlock.h> 43 #include <sys/sx.h> 44 #include <sys/vmem.h> 45 #include <vm/uma.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <machine/bus.h> 50 #include <sys/socket.h> 51 #include <sys/sysctl.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <netinet/in.h> 57 #include <netinet/tcp_lro.h> 58 59 #include "offload.h" 60 #include "t4_ioctl.h" 61 #include "common/t4_msg.h" 62 #include "firmware/t4fw_interface.h" 63 64 #define KTR_CXGBE KTR_SPARE3 65 MALLOC_DECLARE(M_CXGBE); 66 #define CXGBE_UNIMPLEMENTED(s) \ 67 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 68 69 #if defined(__i386__) || defined(__amd64__) 70 static __inline void 71 prefetch(void *x) 72 { 73 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 74 } 75 #else 76 #define prefetch(x) __builtin_prefetch(x) 77 #endif 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 struct adapter; 86 typedef struct adapter adapter_t; 87 88 enum { 89 /* 90 * All ingress queues use this entry size. Note that the firmware event 91 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 92 * be at least 64. 93 */ 94 IQ_ESIZE = 64, 95 96 /* Default queue sizes for all kinds of ingress queues */ 97 FW_IQ_QSIZE = 256, 98 RX_IQ_QSIZE = 1024, 99 100 /* All egress queues use this entry size */ 101 EQ_ESIZE = 64, 102 103 /* Default queue sizes for all kinds of egress queues */ 104 CTRL_EQ_QSIZE = 1024, 105 TX_EQ_QSIZE = 1024, 106 107 #if MJUMPAGESIZE != MCLBYTES 108 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 109 #else 110 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 111 #endif 112 CL_METADATA_SIZE = CACHE_LINE_SIZE, 113 114 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 115 TX_SGL_SEGS = 39, 116 TX_SGL_SEGS_TSO = 38, 117 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 118 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 119 }; 120 121 enum { 122 /* adapter intr_type */ 123 INTR_INTX = (1 << 0), 124 INTR_MSI = (1 << 1), 125 INTR_MSIX = (1 << 2) 126 }; 127 128 enum { 129 XGMAC_MTU = (1 << 0), 130 XGMAC_PROMISC = (1 << 1), 131 XGMAC_ALLMULTI = (1 << 2), 132 XGMAC_VLANEX = (1 << 3), 133 XGMAC_UCADDR = (1 << 4), 134 XGMAC_MCADDRS = (1 << 5), 135 136 XGMAC_ALL = 0xffff 137 }; 138 139 enum { 140 /* flags understood by begin_synchronized_op */ 141 HOLD_LOCK = (1 << 0), 142 SLEEP_OK = (1 << 1), 143 INTR_OK = (1 << 2), 144 145 /* flags understood by end_synchronized_op */ 146 LOCK_HELD = HOLD_LOCK, 147 }; 148 149 enum { 150 /* adapter flags */ 151 FULL_INIT_DONE = (1 << 0), 152 FW_OK = (1 << 1), 153 CHK_MBOX_ACCESS = (1 << 2), 154 MASTER_PF = (1 << 3), 155 ADAP_SYSCTL_CTX = (1 << 4), 156 /* TOM_INIT_DONE= (1 << 5), No longer used */ 157 BUF_PACKING_OK = (1 << 6), 158 IS_VF = (1 << 7), 159 160 CXGBE_BUSY = (1 << 9), 161 162 /* port flags */ 163 HAS_TRACEQ = (1 << 3), 164 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 165 166 /* VI flags */ 167 DOOMED = (1 << 0), 168 VI_INIT_DONE = (1 << 1), 169 VI_SYSCTL_CTX = (1 << 2), 170 171 /* adapter debug_flags */ 172 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 173 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 174 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 175 }; 176 177 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 178 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 179 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 180 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 181 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 182 183 struct vi_info { 184 device_t dev; 185 struct port_info *pi; 186 187 struct ifnet *ifp; 188 189 unsigned long flags; 190 int if_flags; 191 192 uint16_t *rss, *nm_rss; 193 int smt_idx; /* for convenience */ 194 uint16_t viid; 195 int16_t xact_addr_filt;/* index of exact MAC address filter */ 196 uint16_t rss_size; /* size of VI's RSS table slice */ 197 uint16_t rss_base; /* start of VI's RSS table slice */ 198 int hashen; 199 200 int nintr; 201 int first_intr; 202 203 /* These need to be int as they are used in sysctl */ 204 int ntxq; /* # of tx queues */ 205 int first_txq; /* index of first tx queue */ 206 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 207 int nrxq; /* # of rx queues */ 208 int first_rxq; /* index of first rx queue */ 209 int nofldtxq; /* # of offload tx queues */ 210 int first_ofld_txq; /* index of first offload tx queue */ 211 int nofldrxq; /* # of offload rx queues */ 212 int first_ofld_rxq; /* index of first offload rx queue */ 213 int nnmtxq; 214 int first_nm_txq; 215 int nnmrxq; 216 int first_nm_rxq; 217 int tmr_idx; 218 int ofld_tmr_idx; 219 int pktc_idx; 220 int ofld_pktc_idx; 221 int qsize_rxq; 222 int qsize_txq; 223 224 struct timeval last_refreshed; 225 struct fw_vi_stats_vf stats; 226 227 struct callout tick; 228 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 229 230 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 231 }; 232 233 struct tx_ch_rl_params { 234 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 235 uint32_t maxrate; 236 }; 237 238 enum { 239 CLRL_USER = (1 << 0), /* allocated manually. */ 240 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 241 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 242 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 243 }; 244 245 struct tx_cl_rl_params { 246 int refcount; 247 uint8_t flags; 248 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 249 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 250 enum fw_sched_params_mode mode; /* aggr or per-flow */ 251 uint32_t maxrate; 252 uint16_t pktsize; 253 uint16_t burstsize; 254 }; 255 256 /* Tx scheduler parameters for a channel/port */ 257 struct tx_sched_params { 258 /* Channel Rate Limiter */ 259 struct tx_ch_rl_params ch_rl; 260 261 /* Class WRR */ 262 /* XXX */ 263 264 /* Class Rate Limiter (including the default pktsize and burstsize). */ 265 int pktsize; 266 int burstsize; 267 struct tx_cl_rl_params cl_rl[]; 268 }; 269 270 struct port_info { 271 device_t dev; 272 struct adapter *adapter; 273 274 struct vi_info *vi; 275 int nvi; 276 int up_vis; 277 int uld_vis; 278 279 struct tx_sched_params *sched_params; 280 281 struct mtx pi_lock; 282 char lockname[16]; 283 unsigned long flags; 284 285 uint8_t lport; /* associated offload logical port */ 286 int8_t mdio_addr; 287 uint8_t port_type; 288 uint8_t mod_type; 289 uint8_t port_id; 290 uint8_t tx_chan; 291 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 292 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 293 294 struct link_config link_cfg; 295 struct ifmedia media; 296 297 struct timeval last_refreshed; 298 struct port_stats stats; 299 u_int tnl_cong_drops; 300 u_int tx_parse_error; 301 u_long tx_tls_records; 302 u_long tx_tls_octets; 303 u_long rx_tls_records; 304 u_long rx_tls_octets; 305 306 struct callout tick; 307 }; 308 309 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 310 311 /* Where the cluster came from, how it has been carved up. */ 312 struct cluster_layout { 313 int8_t zidx; 314 int8_t hwidx; 315 uint16_t region1; /* mbufs laid out within this region */ 316 /* region2 is the DMA region */ 317 uint16_t region3; /* cluster_metadata within this region */ 318 }; 319 320 struct cluster_metadata { 321 u_int refcount; 322 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 323 }; 324 325 struct fl_sdesc { 326 caddr_t cl; 327 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 328 struct cluster_layout cll; 329 }; 330 331 struct tx_desc { 332 __be64 flit[8]; 333 }; 334 335 struct tx_sdesc { 336 struct mbuf *m; /* m_nextpkt linked chain of frames */ 337 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 338 }; 339 340 341 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 342 struct iq_desc { 343 struct rss_header rss; 344 uint8_t cpl[IQ_PAD]; 345 struct rsp_ctrl rsp; 346 }; 347 #undef IQ_PAD 348 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 349 350 enum { 351 /* iq flags */ 352 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 353 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 354 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 355 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 356 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 357 358 /* iq state */ 359 IQS_DISABLED = 0, 360 IQS_BUSY = 1, 361 IQS_IDLE = 2, 362 363 /* netmap related flags */ 364 NM_OFF = 0, 365 NM_ON = 1, 366 NM_BUSY = 2, 367 }; 368 369 enum { 370 CPL_COOKIE_RESERVED = 0, 371 CPL_COOKIE_FILTER, 372 CPL_COOKIE_DDP0, 373 CPL_COOKIE_DDP1, 374 CPL_COOKIE_TOM, 375 CPL_COOKIE_HASHFILTER, 376 CPL_COOKIE_ETHOFLD, 377 CPL_COOKIE_AVAILABLE3, 378 379 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 380 }; 381 382 struct sge_iq; 383 struct rss_header; 384 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 385 struct mbuf *); 386 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 387 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 388 389 /* 390 * Ingress Queue: T4 is producer, driver is consumer. 391 */ 392 struct sge_iq { 393 uint32_t flags; 394 volatile int state; 395 struct adapter *adapter; 396 struct iq_desc *desc; /* KVA of descriptor ring */ 397 int8_t intr_pktc_idx; /* packet count threshold index */ 398 uint8_t gen; /* generation bit */ 399 uint8_t intr_params; /* interrupt holdoff parameters */ 400 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 401 uint16_t qsize; /* size (# of entries) of the queue */ 402 uint16_t sidx; /* index of the entry with the status page */ 403 uint16_t cidx; /* consumer index */ 404 uint16_t cntxt_id; /* SGE context id for the iq */ 405 uint16_t abs_id; /* absolute SGE id for the iq */ 406 407 STAILQ_ENTRY(sge_iq) link; 408 409 bus_dma_tag_t desc_tag; 410 bus_dmamap_t desc_map; 411 bus_addr_t ba; /* bus address of descriptor ring */ 412 }; 413 414 enum { 415 EQ_CTRL = 1, 416 EQ_ETH = 2, 417 EQ_OFLD = 3, 418 419 /* eq flags */ 420 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 421 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 422 EQ_ENABLED = (1 << 3), /* open for business */ 423 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 424 }; 425 426 /* Listed in order of preference. Update t4_sysctls too if you change these */ 427 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 428 429 /* 430 * Egress Queue: driver is producer, T4 is consumer. 431 * 432 * Note: A free list is an egress queue (driver produces the buffers and T4 433 * consumes them) but it's special enough to have its own struct (see sge_fl). 434 */ 435 struct sge_eq { 436 unsigned int flags; /* MUST be first */ 437 unsigned int cntxt_id; /* SGE context id for the eq */ 438 unsigned int abs_id; /* absolute SGE id for the eq */ 439 struct mtx eq_lock; 440 441 struct tx_desc *desc; /* KVA of descriptor ring */ 442 uint8_t doorbells; 443 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 444 u_int udb_qid; /* relative qid within the doorbell page */ 445 uint16_t sidx; /* index of the entry with the status page */ 446 uint16_t cidx; /* consumer idx (desc idx) */ 447 uint16_t pidx; /* producer idx (desc idx) */ 448 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 449 uint16_t dbidx; /* pidx of the most recent doorbell */ 450 uint16_t iqid; /* iq that gets egr_update for the eq */ 451 uint8_t tx_chan; /* tx channel used by the eq */ 452 volatile u_int equiq; /* EQUIQ outstanding */ 453 454 bus_dma_tag_t desc_tag; 455 bus_dmamap_t desc_map; 456 bus_addr_t ba; /* bus address of descriptor ring */ 457 char lockname[16]; 458 }; 459 460 struct sw_zone_info { 461 uma_zone_t zone; /* zone that this cluster comes from */ 462 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 463 int type; /* EXT_xxx type of the cluster */ 464 int8_t head_hwidx; 465 int8_t tail_hwidx; 466 }; 467 468 struct hw_buf_info { 469 int8_t zidx; /* backpointer to zone; -ve means unused */ 470 int8_t next; /* next hwidx for this zone; -1 means no more */ 471 int size; 472 }; 473 474 enum { 475 NUM_MEMWIN = 3, 476 477 MEMWIN0_APERTURE = 2048, 478 MEMWIN0_BASE = 0x1b800, 479 480 MEMWIN1_APERTURE = 32768, 481 MEMWIN1_BASE = 0x28000, 482 483 MEMWIN2_APERTURE_T4 = 65536, 484 MEMWIN2_BASE_T4 = 0x30000, 485 486 MEMWIN2_APERTURE_T5 = 128 * 1024, 487 MEMWIN2_BASE_T5 = 0x60000, 488 }; 489 490 struct memwin { 491 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 492 uint32_t mw_base; /* constant after setup_memwin */ 493 uint32_t mw_aperture; /* ditto */ 494 uint32_t mw_curpos; /* protected by mw_lock */ 495 }; 496 497 enum { 498 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 499 FL_DOOMED = (1 << 1), /* about to be destroyed */ 500 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 501 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 502 }; 503 504 #define FL_RUNNING_LOW(fl) \ 505 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 506 #define FL_NOT_RUNNING_LOW(fl) \ 507 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 508 509 struct sge_fl { 510 struct mtx fl_lock; 511 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 512 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 513 struct cluster_layout cll_def; /* default refill zone, layout */ 514 uint16_t lowat; /* # of buffers <= this means fl needs help */ 515 int flags; 516 uint16_t buf_boundary; 517 518 /* The 16b idx all deal with hw descriptors */ 519 uint16_t dbidx; /* hw pidx after last doorbell */ 520 uint16_t sidx; /* index of status page */ 521 volatile uint16_t hw_cidx; 522 523 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 524 uint32_t cidx; /* consumer index */ 525 uint32_t pidx; /* producer index */ 526 527 uint32_t dbval; 528 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 529 volatile uint32_t *udb; 530 531 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 532 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 533 uint64_t cl_allocated; /* # of clusters allocated */ 534 uint64_t cl_recycled; /* # of clusters recycled */ 535 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 536 537 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 538 struct mbuf *m0; 539 struct mbuf **pnext; 540 u_int remaining; 541 542 uint16_t qsize; /* # of hw descriptors (status page included) */ 543 uint16_t cntxt_id; /* SGE context id for the freelist */ 544 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 545 bus_dma_tag_t desc_tag; 546 bus_dmamap_t desc_map; 547 char lockname[16]; 548 bus_addr_t ba; /* bus address of descriptor ring */ 549 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 550 }; 551 552 struct mp_ring; 553 554 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 555 struct sge_txq { 556 struct sge_eq eq; /* MUST be first */ 557 558 struct ifnet *ifp; /* the interface this txq belongs to */ 559 struct mp_ring *r; /* tx software ring */ 560 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 561 struct sglist *gl; 562 __be32 cpl_ctrl0; /* for convenience */ 563 int tc_idx; /* traffic class */ 564 565 struct task tx_reclaim_task; 566 /* stats for common events first */ 567 568 uint64_t txcsum; /* # of times hardware assisted with checksum */ 569 uint64_t tso_wrs; /* # of TSO work requests */ 570 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 571 uint64_t imm_wrs; /* # of work requests with immediate data */ 572 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 573 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 574 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 575 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 576 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 577 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 578 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 579 580 /* stats for not-that-common events */ 581 } __aligned(CACHE_LINE_SIZE); 582 583 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 584 struct sge_rxq { 585 struct sge_iq iq; /* MUST be first */ 586 struct sge_fl fl; /* MUST follow iq */ 587 588 struct ifnet *ifp; /* the interface this rxq belongs to */ 589 #if defined(INET) || defined(INET6) 590 struct lro_ctrl lro; /* LRO state */ 591 #endif 592 593 /* stats for common events first */ 594 595 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 596 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 597 598 /* stats for not-that-common events */ 599 600 } __aligned(CACHE_LINE_SIZE); 601 602 static inline struct sge_rxq * 603 iq_to_rxq(struct sge_iq *iq) 604 { 605 606 return (__containerof(iq, struct sge_rxq, iq)); 607 } 608 609 610 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 611 struct sge_ofld_rxq { 612 struct sge_iq iq; /* MUST be first */ 613 struct sge_fl fl; /* MUST follow iq */ 614 } __aligned(CACHE_LINE_SIZE); 615 616 static inline struct sge_ofld_rxq * 617 iq_to_ofld_rxq(struct sge_iq *iq) 618 { 619 620 return (__containerof(iq, struct sge_ofld_rxq, iq)); 621 } 622 623 struct wrqe { 624 STAILQ_ENTRY(wrqe) link; 625 struct sge_wrq *wrq; 626 int wr_len; 627 char wr[] __aligned(16); 628 }; 629 630 struct wrq_cookie { 631 TAILQ_ENTRY(wrq_cookie) link; 632 int ndesc; 633 int pidx; 634 }; 635 636 /* 637 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 638 * and offload tx queues are of this type. 639 */ 640 struct sge_wrq { 641 struct sge_eq eq; /* MUST be first */ 642 643 struct adapter *adapter; 644 struct task wrq_tx_task; 645 646 /* Tx desc reserved but WR not "committed" yet. */ 647 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 648 649 /* List of WRs ready to go out as soon as descriptors are available. */ 650 STAILQ_HEAD(, wrqe) wr_list; 651 u_int nwr_pending; 652 u_int ndesc_needed; 653 654 /* stats for common events first */ 655 656 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 657 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 658 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 659 660 /* stats for not-that-common events */ 661 662 /* 663 * Scratch space for work requests that wrap around after reaching the 664 * status page, and some information about the last WR that used it. 665 */ 666 uint16_t ss_pidx; 667 uint16_t ss_len; 668 uint8_t ss[SGE_MAX_WR_LEN]; 669 670 } __aligned(CACHE_LINE_SIZE); 671 672 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 673 struct sge_nm_rxq { 674 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 675 struct vi_info *vi; 676 677 struct iq_desc *iq_desc; 678 uint16_t iq_abs_id; 679 uint16_t iq_cntxt_id; 680 uint16_t iq_cidx; 681 uint16_t iq_sidx; 682 uint8_t iq_gen; 683 684 __be64 *fl_desc; 685 uint16_t fl_cntxt_id; 686 uint32_t fl_cidx; 687 uint32_t fl_pidx; 688 uint32_t fl_sidx; 689 uint32_t fl_db_val; 690 u_int fl_hwidx:4; 691 692 u_int fl_db_saved; 693 u_int nid; /* netmap ring # for this queue */ 694 695 /* infrequently used items after this */ 696 697 bus_dma_tag_t iq_desc_tag; 698 bus_dmamap_t iq_desc_map; 699 bus_addr_t iq_ba; 700 int intr_idx; 701 702 bus_dma_tag_t fl_desc_tag; 703 bus_dmamap_t fl_desc_map; 704 bus_addr_t fl_ba; 705 } __aligned(CACHE_LINE_SIZE); 706 707 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 708 struct sge_nm_txq { 709 struct tx_desc *desc; 710 uint16_t cidx; 711 uint16_t pidx; 712 uint16_t sidx; 713 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 714 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 715 uint16_t dbidx; /* pidx of the most recent doorbell */ 716 uint8_t doorbells; 717 volatile uint32_t *udb; 718 u_int udb_qid; 719 u_int cntxt_id; 720 __be32 cpl_ctrl0; /* for convenience */ 721 u_int nid; /* netmap ring # for this queue */ 722 723 /* infrequently used items after this */ 724 725 bus_dma_tag_t desc_tag; 726 bus_dmamap_t desc_map; 727 bus_addr_t ba; 728 int iqidx; 729 } __aligned(CACHE_LINE_SIZE); 730 731 struct sge { 732 int nrxq; /* total # of Ethernet rx queues */ 733 int ntxq; /* total # of Ethernet tx queues */ 734 int nofldrxq; /* total # of TOE rx queues */ 735 int nofldtxq; /* total # of TOE tx queues */ 736 int nnmrxq; /* total # of netmap rx queues */ 737 int nnmtxq; /* total # of netmap tx queues */ 738 int niq; /* total # of ingress queues */ 739 int neq; /* total # of egress queues */ 740 741 struct sge_iq fwq; /* Firmware event queue */ 742 struct sge_wrq *ctrlq; /* Control queues */ 743 struct sge_txq *txq; /* NIC tx queues */ 744 struct sge_rxq *rxq; /* NIC rx queues */ 745 struct sge_wrq *ofld_txq; /* TOE tx queues */ 746 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 747 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 748 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 749 750 uint16_t iq_start; /* first cntxt_id */ 751 uint16_t iq_base; /* first abs_id */ 752 int eq_start; /* first cntxt_id */ 753 int eq_base; /* first abs_id */ 754 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 755 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 756 757 int8_t safe_hwidx1; /* may not have room for metadata */ 758 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 759 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 760 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 761 }; 762 763 struct devnames { 764 const char *nexus_name; 765 const char *ifnet_name; 766 const char *vi_ifnet_name; 767 const char *pf03_drv_name; 768 const char *vf_nexus_name; 769 const char *vf_ifnet_name; 770 }; 771 772 struct adapter { 773 SLIST_ENTRY(adapter) link; 774 device_t dev; 775 struct cdev *cdev; 776 const struct devnames *names; 777 778 /* PCIe register resources */ 779 int regs_rid; 780 struct resource *regs_res; 781 int msix_rid; 782 struct resource *msix_res; 783 bus_space_handle_t bh; 784 bus_space_tag_t bt; 785 bus_size_t mmio_len; 786 int udbs_rid; 787 struct resource *udbs_res; 788 volatile uint8_t *udbs_base; 789 790 unsigned int pf; 791 unsigned int mbox; 792 unsigned int vpd_busy; 793 unsigned int vpd_flag; 794 795 /* Interrupt information */ 796 int intr_type; 797 int intr_count; 798 struct irq { 799 struct resource *res; 800 int rid; 801 void *tag; 802 struct sge_rxq *rxq; 803 struct sge_nm_rxq *nm_rxq; 804 } __aligned(CACHE_LINE_SIZE) *irq; 805 int sge_gts_reg; 806 int sge_kdoorbell_reg; 807 808 bus_dma_tag_t dmat; /* Parent DMA tag */ 809 810 struct sge sge; 811 int lro_timeout; 812 int sc_do_rxcopy; 813 814 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 815 struct port_info *port[MAX_NPORTS]; 816 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 817 818 void *tom_softc; /* (struct tom_data *) */ 819 struct tom_tunables tt; 820 struct t4_offload_policy *policy; 821 struct rwlock policy_lock; 822 823 void *iwarp_softc; /* (struct c4iw_dev *) */ 824 struct iw_tunables iwt; 825 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 826 void *ccr_softc; /* (struct ccr_softc *) */ 827 struct l2t_data *l2t; /* L2 table */ 828 struct smt_data *smt; /* Source MAC Table */ 829 struct tid_info tids; 830 vmem_t *key_map; 831 832 uint8_t doorbells; 833 int offload_map; /* ports with IFCAP_TOE enabled */ 834 int active_ulds; /* ULDs activated on this adapter */ 835 int flags; 836 int debug_flags; 837 838 char ifp_lockname[16]; 839 struct mtx ifp_lock; 840 struct ifnet *ifp; /* tracer ifp */ 841 struct ifmedia media; 842 int traceq; /* iq used by all tracers, -1 if none */ 843 int tracer_valid; /* bitmap of valid tracers */ 844 int tracer_enabled; /* bitmap of enabled tracers */ 845 846 char fw_version[16]; 847 char tp_version[16]; 848 char er_version[16]; 849 char bs_version[16]; 850 char cfg_file[32]; 851 u_int cfcsum; 852 struct adapter_params params; 853 const struct chip_params *chip_params; 854 struct t4_virt_res vres; 855 856 uint16_t nbmcaps; 857 uint16_t linkcaps; 858 uint16_t switchcaps; 859 uint16_t niccaps; 860 uint16_t toecaps; 861 uint16_t rdmacaps; 862 uint16_t cryptocaps; 863 uint16_t iscsicaps; 864 uint16_t fcoecaps; 865 866 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 867 868 struct mtx sc_lock; 869 char lockname[16]; 870 871 /* Starving free lists */ 872 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 873 TAILQ_HEAD(, sge_fl) sfl; 874 struct callout sfl_callout; 875 876 struct mtx reg_lock; /* for indirect register access */ 877 878 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 879 880 struct mtx tc_lock; 881 struct task tc_task; 882 883 const char *last_op; 884 const void *last_op_thr; 885 int last_op_flags; 886 }; 887 888 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 889 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 890 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 891 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 892 893 #define ASSERT_SYNCHRONIZED_OP(sc) \ 894 KASSERT(IS_BUSY(sc) && \ 895 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 896 ("%s: operation not synchronized.", __func__)) 897 898 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 899 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 900 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 901 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 902 903 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 904 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 905 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 906 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 907 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 908 909 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 910 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 911 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 912 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 913 914 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 915 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 916 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 917 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 918 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 919 920 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 921 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 922 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 923 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 924 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 925 926 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 927 do { \ 928 if (sc->debug_flags & DF_DUMP_MBOX) { \ 929 log(LOG_NOTICE, \ 930 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 931 "%016llx %016llx %016llx %016llx\n", \ 932 device_get_nameunit(sc->dev), mbox, \ 933 (unsigned long long)t4_read_reg64(sc, data_reg), \ 934 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 935 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 936 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 937 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 938 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 939 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 940 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 941 } \ 942 } while (0) 943 944 #define for_each_txq(vi, iter, q) \ 945 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 946 iter < vi->ntxq; ++iter, ++q) 947 #define for_each_rxq(vi, iter, q) \ 948 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 949 iter < vi->nrxq; ++iter, ++q) 950 #define for_each_ofld_txq(vi, iter, q) \ 951 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 952 iter < vi->nofldtxq; ++iter, ++q) 953 #define for_each_ofld_rxq(vi, iter, q) \ 954 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 955 iter < vi->nofldrxq; ++iter, ++q) 956 #define for_each_nm_txq(vi, iter, q) \ 957 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 958 iter < vi->nnmtxq; ++iter, ++q) 959 #define for_each_nm_rxq(vi, iter, q) \ 960 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 961 iter < vi->nnmrxq; ++iter, ++q) 962 #define for_each_vi(_pi, _iter, _vi) \ 963 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 964 ++(_iter), ++(_vi)) 965 966 #define IDXINCR(idx, incr, wrap) do { \ 967 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 968 } while (0) 969 #define IDXDIFF(head, tail, wrap) \ 970 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 971 972 /* One for errors, one for firmware events */ 973 #define T4_EXTRA_INTR 2 974 975 /* One for firmware events */ 976 #define T4VF_EXTRA_INTR 1 977 978 static inline int 979 forwarding_intr_to_fwq(struct adapter *sc) 980 { 981 982 return (sc->intr_count == 1); 983 } 984 985 static inline uint32_t 986 t4_read_reg(struct adapter *sc, uint32_t reg) 987 { 988 989 return bus_space_read_4(sc->bt, sc->bh, reg); 990 } 991 992 static inline void 993 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 994 { 995 996 bus_space_write_4(sc->bt, sc->bh, reg, val); 997 } 998 999 static inline uint64_t 1000 t4_read_reg64(struct adapter *sc, uint32_t reg) 1001 { 1002 1003 #ifdef __LP64__ 1004 return bus_space_read_8(sc->bt, sc->bh, reg); 1005 #else 1006 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1007 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1008 1009 #endif 1010 } 1011 1012 static inline void 1013 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1014 { 1015 1016 #ifdef __LP64__ 1017 bus_space_write_8(sc->bt, sc->bh, reg, val); 1018 #else 1019 bus_space_write_4(sc->bt, sc->bh, reg, val); 1020 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1021 #endif 1022 } 1023 1024 static inline void 1025 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1026 { 1027 1028 *val = pci_read_config(sc->dev, reg, 1); 1029 } 1030 1031 static inline void 1032 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1033 { 1034 1035 pci_write_config(sc->dev, reg, val, 1); 1036 } 1037 1038 static inline void 1039 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1040 { 1041 1042 *val = pci_read_config(sc->dev, reg, 2); 1043 } 1044 1045 static inline void 1046 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1047 { 1048 1049 pci_write_config(sc->dev, reg, val, 2); 1050 } 1051 1052 static inline void 1053 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1054 { 1055 1056 *val = pci_read_config(sc->dev, reg, 4); 1057 } 1058 1059 static inline void 1060 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1061 { 1062 1063 pci_write_config(sc->dev, reg, val, 4); 1064 } 1065 1066 static inline struct port_info * 1067 adap2pinfo(struct adapter *sc, int idx) 1068 { 1069 1070 return (sc->port[idx]); 1071 } 1072 1073 static inline void 1074 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1075 { 1076 1077 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1078 } 1079 1080 static inline int 1081 tx_resume_threshold(struct sge_eq *eq) 1082 { 1083 1084 /* not quite the same as qsize / 4, but this will do. */ 1085 return (eq->sidx / 4); 1086 } 1087 1088 static inline int 1089 t4_use_ldst(struct adapter *sc) 1090 { 1091 1092 #ifdef notyet 1093 return (sc->flags & FW_OK || !sc->use_bd); 1094 #else 1095 return (0); 1096 #endif 1097 } 1098 1099 /* t4_main.c */ 1100 extern int t4_ntxq; 1101 extern int t4_nrxq; 1102 extern int t4_intr_types; 1103 extern int t4_tmr_idx; 1104 extern int t4_pktc_idx; 1105 extern unsigned int t4_qsize_rxq; 1106 extern unsigned int t4_qsize_txq; 1107 extern device_method_t cxgbe_methods[]; 1108 1109 int t4_os_find_pci_capability(struct adapter *, int); 1110 int t4_os_pci_save_state(struct adapter *); 1111 int t4_os_pci_restore_state(struct adapter *); 1112 void t4_os_portmod_changed(struct port_info *); 1113 void t4_os_link_changed(struct port_info *); 1114 void t4_iterate(void (*)(struct adapter *, void *), void *); 1115 void t4_init_devnames(struct adapter *); 1116 void t4_add_adapter(struct adapter *); 1117 void t4_aes_getdeckey(void *, const void *, unsigned int); 1118 int t4_detach_common(device_t); 1119 int t4_map_bars_0_and_4(struct adapter *); 1120 int t4_map_bar_2(struct adapter *); 1121 int t4_setup_intr_handlers(struct adapter *); 1122 void t4_sysctls(struct adapter *); 1123 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1124 void doom_vi(struct adapter *, struct vi_info *); 1125 void end_synchronized_op(struct adapter *, int); 1126 int update_mac_settings(struct ifnet *, int); 1127 int adapter_full_init(struct adapter *); 1128 int adapter_full_uninit(struct adapter *); 1129 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1130 int vi_full_init(struct vi_info *); 1131 int vi_full_uninit(struct vi_info *); 1132 void vi_sysctls(struct vi_info *); 1133 void vi_tick(void *); 1134 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1135 int alloc_atid_tab(struct tid_info *, int); 1136 void free_atid_tab(struct tid_info *); 1137 int alloc_atid(struct adapter *, void *); 1138 void *lookup_atid(struct adapter *, int); 1139 void free_atid(struct adapter *, int); 1140 void release_tid(struct adapter *, int, struct sge_wrq *); 1141 int cxgbe_media_change(struct ifnet *); 1142 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1143 1144 #ifdef DEV_NETMAP 1145 /* t4_netmap.c */ 1146 struct sge_nm_rxq; 1147 void cxgbe_nm_attach(struct vi_info *); 1148 void cxgbe_nm_detach(struct vi_info *); 1149 void service_nm_rxq(struct sge_nm_rxq *); 1150 #endif 1151 1152 /* t4_sge.c */ 1153 void t4_sge_modload(void); 1154 void t4_sge_modunload(void); 1155 uint64_t t4_sge_extfree_refs(void); 1156 void t4_tweak_chip_settings(struct adapter *); 1157 int t4_read_chip_settings(struct adapter *); 1158 int t4_create_dma_tag(struct adapter *); 1159 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1160 struct sysctl_oid_list *); 1161 int t4_destroy_dma_tag(struct adapter *); 1162 int t4_setup_adapter_queues(struct adapter *); 1163 int t4_teardown_adapter_queues(struct adapter *); 1164 int t4_setup_vi_queues(struct vi_info *); 1165 int t4_teardown_vi_queues(struct vi_info *); 1166 void t4_intr_all(void *); 1167 void t4_intr(void *); 1168 #ifdef DEV_NETMAP 1169 void t4_nm_intr(void *); 1170 void t4_vi_intr(void *); 1171 #endif 1172 void t4_intr_err(void *); 1173 void t4_intr_evt(void *); 1174 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1175 void t4_update_fl_bufsize(struct ifnet *); 1176 struct mbuf *alloc_wr_mbuf(int, int); 1177 int parse_pkt(struct adapter *, struct mbuf **); 1178 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1179 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1180 int tnl_cong(struct port_info *, int); 1181 void t4_register_an_handler(an_handler_t); 1182 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1183 void t4_register_cpl_handler(int, cpl_handler_t); 1184 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1185 #ifdef RATELIMIT 1186 int ethofld_transmit(struct ifnet *, struct mbuf *); 1187 void send_etid_flush_wr(struct cxgbe_snd_tag *); 1188 #endif 1189 1190 /* t4_tracer.c */ 1191 struct t4_tracer; 1192 void t4_tracer_modload(void); 1193 void t4_tracer_modunload(void); 1194 void t4_tracer_port_detach(struct adapter *); 1195 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1196 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1197 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1198 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1199 1200 /* t4_sched.c */ 1201 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1202 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1203 int t4_init_tx_sched(struct adapter *); 1204 int t4_free_tx_sched(struct adapter *); 1205 void t4_update_tx_sched(struct adapter *); 1206 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1207 void t4_release_cl_rl(struct adapter *, int, int); 1208 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1209 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1210 #ifdef RATELIMIT 1211 void t4_init_etid_table(struct adapter *); 1212 void t4_free_etid_table(struct adapter *); 1213 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int); 1214 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1215 struct m_snd_tag **); 1216 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1217 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1218 void cxgbe_snd_tag_free(struct m_snd_tag *); 1219 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *); 1220 #endif 1221 1222 /* t4_filter.c */ 1223 int get_filter_mode(struct adapter *, uint32_t *); 1224 int set_filter_mode(struct adapter *, uint32_t); 1225 int get_filter(struct adapter *, struct t4_filter *); 1226 int set_filter(struct adapter *, struct t4_filter *); 1227 int del_filter(struct adapter *, struct t4_filter *); 1228 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1229 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1230 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1231 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1232 void free_hftid_hash(struct tid_info *); 1233 1234 static inline struct wrqe * 1235 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1236 { 1237 int len = offsetof(struct wrqe, wr) + wr_len; 1238 struct wrqe *wr; 1239 1240 wr = malloc(len, M_CXGBE, M_NOWAIT); 1241 if (__predict_false(wr == NULL)) 1242 return (NULL); 1243 wr->wr_len = wr_len; 1244 wr->wrq = wrq; 1245 return (wr); 1246 } 1247 1248 static inline void * 1249 wrtod(struct wrqe *wr) 1250 { 1251 return (&wr->wr[0]); 1252 } 1253 1254 static inline void 1255 free_wrqe(struct wrqe *wr) 1256 { 1257 free(wr, M_CXGBE); 1258 } 1259 1260 static inline void 1261 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1262 { 1263 struct sge_wrq *wrq = wr->wrq; 1264 1265 TXQ_LOCK(wrq); 1266 t4_wrq_tx_locked(sc, wrq, wr); 1267 TXQ_UNLOCK(wrq); 1268 } 1269 1270 static inline int 1271 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1272 int len) 1273 { 1274 1275 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1276 } 1277 1278 static inline int 1279 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1280 const uint32_t *val, int len) 1281 { 1282 1283 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1284 } 1285 #endif 1286