1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 #define KTR_CXGBE KTR_SPARE3 61 MALLOC_DECLARE(M_CXGBE); 62 #define CXGBE_UNIMPLEMENTED(s) \ 63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 64 65 #if defined(__i386__) || defined(__amd64__) 66 static __inline void 67 prefetch(void *x) 68 { 69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 70 } 71 #else 72 #define prefetch(x) 73 #endif 74 75 #ifndef SYSCTL_ADD_UQUAD 76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 77 #define sysctl_handle_64 sysctl_handle_quad 78 #define CTLTYPE_U64 CTLTYPE_QUAD 79 #endif 80 81 #if (__FreeBSD_version >= 900030) || \ 82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 83 #define SBUF_DRAIN 1 84 #endif 85 86 #ifdef __amd64__ 87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 KASSERT(tag == X86_BUS_SPACE_MEM, 93 ("%s: can only handle mem space", __func__)); 94 95 return (*(volatile uint64_t *)(handle + offset)); 96 } 97 98 static __inline void 99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 100 bus_size_t offset, uint64_t value) 101 { 102 KASSERT(tag == X86_BUS_SPACE_MEM, 103 ("%s: can only handle mem space", __func__)); 104 105 *(volatile uint64_t *)(bsh + offset) = value; 106 } 107 #else 108 static __inline uint64_t 109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 110 bus_size_t offset) 111 { 112 return (uint64_t)bus_space_read_4(tag, handle, offset) + 113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 114 } 115 116 static __inline void 117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 118 bus_size_t offset, uint64_t value) 119 { 120 bus_space_write_4(tag, bsh, offset, value); 121 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 122 } 123 #endif 124 125 struct adapter; 126 typedef struct adapter adapter_t; 127 128 enum { 129 /* 130 * All ingress queues use this entry size. Note that the firmware event 131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 132 * be at least 64. 133 */ 134 IQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of ingress queues */ 137 FW_IQ_QSIZE = 256, 138 RX_IQ_QSIZE = 1024, 139 140 /* All egress queues use this entry size */ 141 EQ_ESIZE = 64, 142 143 /* Default queue sizes for all kinds of egress queues */ 144 CTRL_EQ_QSIZE = 128, 145 TX_EQ_QSIZE = 1024, 146 147 #if MJUMPAGESIZE != MCLBYTES 148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 149 #else 150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 151 #endif 152 CL_METADATA_SIZE = CACHE_LINE_SIZE, 153 154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 155 TX_SGL_SEGS = 36, 156 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 157 }; 158 159 enum { 160 /* adapter intr_type */ 161 INTR_INTX = (1 << 0), 162 INTR_MSI = (1 << 1), 163 INTR_MSIX = (1 << 2) 164 }; 165 166 enum { 167 XGMAC_MTU = (1 << 0), 168 XGMAC_PROMISC = (1 << 1), 169 XGMAC_ALLMULTI = (1 << 2), 170 XGMAC_VLANEX = (1 << 3), 171 XGMAC_UCADDR = (1 << 4), 172 XGMAC_MCADDRS = (1 << 5), 173 174 XGMAC_ALL = 0xffff 175 }; 176 177 enum { 178 /* flags understood by begin_synchronized_op */ 179 HOLD_LOCK = (1 << 0), 180 SLEEP_OK = (1 << 1), 181 INTR_OK = (1 << 2), 182 183 /* flags understood by end_synchronized_op */ 184 LOCK_HELD = HOLD_LOCK, 185 }; 186 187 enum { 188 /* adapter flags */ 189 FULL_INIT_DONE = (1 << 0), 190 FW_OK = (1 << 1), 191 /* INTR_DIRECT = (1 << 2), No longer used. */ 192 MASTER_PF = (1 << 3), 193 ADAP_SYSCTL_CTX = (1 << 4), 194 TOM_INIT_DONE = (1 << 5), 195 BUF_PACKING_OK = (1 << 6), 196 197 CXGBE_BUSY = (1 << 9), 198 199 /* port flags */ 200 DOOMED = (1 << 0), 201 PORT_INIT_DONE = (1 << 1), 202 PORT_SYSCTL_CTX = (1 << 2), 203 HAS_TRACEQ = (1 << 3), 204 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 205 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 206 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */ 207 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ), 208 }; 209 210 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 211 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 212 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 213 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 214 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 215 216 struct port_info { 217 device_t dev; 218 struct adapter *adapter; 219 220 struct ifnet *ifp; 221 struct ifmedia media; 222 223 struct mtx pi_lock; 224 char lockname[16]; 225 unsigned long flags; 226 int if_flags; 227 228 uint16_t *rss; 229 uint16_t viid; 230 int16_t xact_addr_filt;/* index of exact MAC address filter */ 231 uint16_t rss_size; /* size of VI's RSS table slice */ 232 uint8_t lport; /* associated offload logical port */ 233 int8_t mdio_addr; 234 uint8_t port_type; 235 uint8_t mod_type; 236 uint8_t port_id; 237 uint8_t tx_chan; 238 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 239 240 /* These need to be int as they are used in sysctl */ 241 int ntxq; /* # of tx queues */ 242 int first_txq; /* index of first tx queue */ 243 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 244 int nrxq; /* # of rx queues */ 245 int first_rxq; /* index of first rx queue */ 246 #ifdef TCP_OFFLOAD 247 int nofldtxq; /* # of offload tx queues */ 248 int first_ofld_txq; /* index of first offload tx queue */ 249 int nofldrxq; /* # of offload rx queues */ 250 int first_ofld_rxq; /* index of first offload rx queue */ 251 #endif 252 #ifdef DEV_NETMAP 253 int nnmtxq; /* # of netmap tx queues */ 254 int first_nm_txq; /* index of first netmap tx queue */ 255 int nnmrxq; /* # of netmap rx queues */ 256 int first_nm_rxq; /* index of first netmap rx queue */ 257 258 struct ifnet *nm_ifp; 259 struct ifmedia nm_media; 260 int nmif_flags; 261 uint16_t nm_viid; 262 int16_t nm_xact_addr_filt; 263 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */ 264 #endif 265 int tmr_idx; 266 int pktc_idx; 267 int qsize_rxq; 268 int qsize_txq; 269 270 int linkdnrc; 271 struct link_config link_cfg; 272 273 struct timeval last_refreshed; 274 struct port_stats stats; 275 u_int tnl_cong_drops; 276 277 eventhandler_tag vlan_c; 278 279 struct callout tick; 280 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 281 282 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 283 }; 284 285 /* Where the cluster came from, how it has been carved up. */ 286 struct cluster_layout { 287 int8_t zidx; 288 int8_t hwidx; 289 uint16_t region1; /* mbufs laid out within this region */ 290 /* region2 is the DMA region */ 291 uint16_t region3; /* cluster_metadata within this region */ 292 }; 293 294 struct cluster_metadata { 295 u_int refcount; 296 #ifdef INVARIANTS 297 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 298 #endif 299 }; 300 301 struct fl_sdesc { 302 caddr_t cl; 303 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 304 struct cluster_layout cll; 305 }; 306 307 struct tx_desc { 308 __be64 flit[8]; 309 }; 310 311 struct tx_map { 312 struct mbuf *m; 313 bus_dmamap_t map; 314 }; 315 316 /* DMA maps used for tx */ 317 struct tx_maps { 318 struct tx_map *maps; 319 uint32_t map_total; /* # of DMA maps */ 320 uint32_t map_pidx; /* next map to be used */ 321 uint32_t map_cidx; /* reclaimed up to this index */ 322 uint32_t map_avail; /* # of available maps */ 323 }; 324 325 struct tx_sdesc { 326 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 327 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 328 }; 329 330 331 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 332 struct iq_desc { 333 struct rss_header rss; 334 uint8_t cpl[IQ_PAD]; 335 struct rsp_ctrl rsp; 336 }; 337 #undef IQ_PAD 338 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 339 340 enum { 341 /* iq flags */ 342 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 343 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 344 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 345 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 346 347 /* iq state */ 348 IQS_DISABLED = 0, 349 IQS_BUSY = 1, 350 IQS_IDLE = 2, 351 }; 352 353 /* 354 * Ingress Queue: T4 is producer, driver is consumer. 355 */ 356 struct sge_iq { 357 uint32_t flags; 358 volatile int state; 359 struct adapter *adapter; 360 struct iq_desc *desc; /* KVA of descriptor ring */ 361 int8_t intr_pktc_idx; /* packet count threshold index */ 362 uint8_t gen; /* generation bit */ 363 uint8_t intr_params; /* interrupt holdoff parameters */ 364 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 365 uint16_t qsize; /* size (# of entries) of the queue */ 366 uint16_t sidx; /* index of the entry with the status page */ 367 uint16_t cidx; /* consumer index */ 368 uint16_t cntxt_id; /* SGE context id for the iq */ 369 uint16_t abs_id; /* absolute SGE id for the iq */ 370 371 STAILQ_ENTRY(sge_iq) link; 372 373 bus_dma_tag_t desc_tag; 374 bus_dmamap_t desc_map; 375 bus_addr_t ba; /* bus address of descriptor ring */ 376 }; 377 378 enum { 379 EQ_CTRL = 1, 380 EQ_ETH = 2, 381 #ifdef TCP_OFFLOAD 382 EQ_OFLD = 3, 383 #endif 384 385 /* eq flags */ 386 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 387 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 388 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 389 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 390 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 391 }; 392 393 /* Listed in order of preference. Update t4_sysctls too if you change these */ 394 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 395 396 /* 397 * Egress Queue: driver is producer, T4 is consumer. 398 * 399 * Note: A free list is an egress queue (driver produces the buffers and T4 400 * consumes them) but it's special enough to have its own struct (see sge_fl). 401 */ 402 struct sge_eq { 403 unsigned int flags; /* MUST be first */ 404 unsigned int cntxt_id; /* SGE context id for the eq */ 405 bus_dma_tag_t desc_tag; 406 bus_dmamap_t desc_map; 407 char lockname[16]; 408 struct mtx eq_lock; 409 410 struct tx_desc *desc; /* KVA of descriptor ring */ 411 bus_addr_t ba; /* bus address of descriptor ring */ 412 struct sge_qstat *spg; /* status page, for convenience */ 413 uint16_t doorbells; 414 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 415 u_int udb_qid; /* relative qid within the doorbell page */ 416 uint16_t cap; /* max # of desc, for convenience */ 417 uint16_t avail; /* available descriptors, for convenience */ 418 uint16_t qsize; /* size (# of entries) of the queue */ 419 uint16_t cidx; /* consumer idx (desc idx) */ 420 uint16_t pidx; /* producer idx (desc idx) */ 421 uint16_t pending; /* # of descriptors used since last doorbell */ 422 uint16_t iqid; /* iq that gets egr_update for the eq */ 423 uint8_t tx_chan; /* tx channel used by the eq */ 424 struct task tx_task; 425 struct callout tx_callout; 426 427 /* stats */ 428 429 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 430 uint32_t unstalled; /* recovered from stall */ 431 }; 432 433 struct sw_zone_info { 434 uma_zone_t zone; /* zone that this cluster comes from */ 435 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 436 int type; /* EXT_xxx type of the cluster */ 437 int8_t head_hwidx; 438 int8_t tail_hwidx; 439 }; 440 441 struct hw_buf_info { 442 int8_t zidx; /* backpointer to zone; -ve means unused */ 443 int8_t next; /* next hwidx for this zone; -1 means no more */ 444 int size; 445 }; 446 447 enum { 448 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 449 FL_DOOMED = (1 << 1), /* about to be destroyed */ 450 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 451 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 452 }; 453 454 #define FL_RUNNING_LOW(fl) \ 455 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 456 #define FL_NOT_RUNNING_LOW(fl) \ 457 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 458 459 struct sge_fl { 460 struct mtx fl_lock; 461 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 462 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 463 struct cluster_layout cll_def; /* default refill zone, layout */ 464 uint16_t lowat; /* # of buffers <= this means fl needs help */ 465 int flags; 466 uint16_t buf_boundary; 467 468 /* The 16b idx all deal with hw descriptors */ 469 uint16_t dbidx; /* hw pidx after last doorbell */ 470 uint16_t sidx; /* index of status page */ 471 volatile uint16_t hw_cidx; 472 473 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 474 uint32_t cidx; /* consumer index */ 475 uint32_t pidx; /* producer index */ 476 477 uint32_t dbval; 478 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 479 volatile uint32_t *udb; 480 481 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 482 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 483 uint64_t cl_allocated; /* # of clusters allocated */ 484 uint64_t cl_recycled; /* # of clusters recycled */ 485 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 486 487 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 488 struct mbuf *m0; 489 struct mbuf **pnext; 490 u_int remaining; 491 492 uint16_t qsize; /* # of hw descriptors (status page included) */ 493 uint16_t cntxt_id; /* SGE context id for the freelist */ 494 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 495 bus_dma_tag_t desc_tag; 496 bus_dmamap_t desc_map; 497 char lockname[16]; 498 bus_addr_t ba; /* bus address of descriptor ring */ 499 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 500 }; 501 502 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 503 struct sge_txq { 504 struct sge_eq eq; /* MUST be first */ 505 506 struct ifnet *ifp; /* the interface this txq belongs to */ 507 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 508 struct buf_ring *br; /* tx buffer ring */ 509 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 510 struct mbuf *m; /* held up due to temporary resource shortage */ 511 512 struct tx_maps txmaps; 513 514 /* stats for common events first */ 515 516 uint64_t txcsum; /* # of times hardware assisted with checksum */ 517 uint64_t tso_wrs; /* # of TSO work requests */ 518 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 519 uint64_t imm_wrs; /* # of work requests with immediate data */ 520 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 521 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 522 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 523 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 524 525 /* stats for not-that-common events */ 526 527 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 528 uint32_t no_desc; /* out of hardware descriptors */ 529 } __aligned(CACHE_LINE_SIZE); 530 531 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 532 struct sge_rxq { 533 struct sge_iq iq; /* MUST be first */ 534 struct sge_fl fl; /* MUST follow iq */ 535 536 struct ifnet *ifp; /* the interface this rxq belongs to */ 537 #if defined(INET) || defined(INET6) 538 struct lro_ctrl lro; /* LRO state */ 539 #endif 540 541 /* stats for common events first */ 542 543 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 544 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 545 546 /* stats for not-that-common events */ 547 548 } __aligned(CACHE_LINE_SIZE); 549 550 static inline struct sge_rxq * 551 iq_to_rxq(struct sge_iq *iq) 552 { 553 554 return (__containerof(iq, struct sge_rxq, iq)); 555 } 556 557 558 #ifdef TCP_OFFLOAD 559 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 560 struct sge_ofld_rxq { 561 struct sge_iq iq; /* MUST be first */ 562 struct sge_fl fl; /* MUST follow iq */ 563 } __aligned(CACHE_LINE_SIZE); 564 565 static inline struct sge_ofld_rxq * 566 iq_to_ofld_rxq(struct sge_iq *iq) 567 { 568 569 return (__containerof(iq, struct sge_ofld_rxq, iq)); 570 } 571 #endif 572 573 struct wrqe { 574 STAILQ_ENTRY(wrqe) link; 575 struct sge_wrq *wrq; 576 int wr_len; 577 uint64_t wr[] __aligned(16); 578 }; 579 580 /* 581 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 582 * and offload tx queues are of this type. 583 */ 584 struct sge_wrq { 585 struct sge_eq eq; /* MUST be first */ 586 587 struct adapter *adapter; 588 589 /* List of WRs held up due to lack of tx descriptors */ 590 STAILQ_HEAD(, wrqe) wr_list; 591 592 /* stats for common events first */ 593 594 uint64_t tx_wrs; /* # of tx work requests */ 595 596 /* stats for not-that-common events */ 597 598 uint32_t no_desc; /* out of hardware descriptors */ 599 } __aligned(CACHE_LINE_SIZE); 600 601 602 #ifdef DEV_NETMAP 603 struct sge_nm_rxq { 604 struct port_info *pi; 605 606 struct iq_desc *iq_desc; 607 uint16_t iq_abs_id; 608 uint16_t iq_cntxt_id; 609 uint16_t iq_cidx; 610 uint16_t iq_sidx; 611 uint8_t iq_gen; 612 613 __be64 *fl_desc; 614 uint16_t fl_cntxt_id; 615 uint32_t fl_cidx; 616 uint32_t fl_pidx; 617 uint32_t fl_sidx; 618 uint32_t fl_db_val; 619 u_int fl_hwidx:4; 620 621 u_int nid; /* netmap ring # for this queue */ 622 623 /* infrequently used items after this */ 624 625 bus_dma_tag_t iq_desc_tag; 626 bus_dmamap_t iq_desc_map; 627 bus_addr_t iq_ba; 628 int intr_idx; 629 630 bus_dma_tag_t fl_desc_tag; 631 bus_dmamap_t fl_desc_map; 632 bus_addr_t fl_ba; 633 } __aligned(CACHE_LINE_SIZE); 634 635 struct sge_nm_txq { 636 struct tx_desc *desc; 637 uint16_t cidx; 638 uint16_t pidx; 639 uint16_t sidx; 640 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 641 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 642 uint16_t dbidx; /* pidx of the most recent doorbell */ 643 uint16_t doorbells; 644 volatile uint32_t *udb; 645 u_int udb_qid; 646 u_int cntxt_id; 647 __be32 cpl_ctrl0; /* for convenience */ 648 u_int nid; /* netmap ring # for this queue */ 649 650 /* infrequently used items after this */ 651 652 bus_dma_tag_t desc_tag; 653 bus_dmamap_t desc_map; 654 bus_addr_t ba; 655 int iqidx; 656 } __aligned(CACHE_LINE_SIZE); 657 #endif 658 659 struct sge { 660 int timer_val[SGE_NTIMERS]; 661 int counter_val[SGE_NCOUNTERS]; 662 int fl_starve_threshold; 663 int fl_starve_threshold2; 664 int eq_s_qpp; 665 int iq_s_qpp; 666 667 int nrxq; /* total # of Ethernet rx queues */ 668 int ntxq; /* total # of Ethernet tx tx queues */ 669 #ifdef TCP_OFFLOAD 670 int nofldrxq; /* total # of TOE rx queues */ 671 int nofldtxq; /* total # of TOE tx queues */ 672 #endif 673 #ifdef DEV_NETMAP 674 int nnmrxq; /* total # of netmap rx queues */ 675 int nnmtxq; /* total # of netmap tx queues */ 676 #endif 677 int niq; /* total # of ingress queues */ 678 int neq; /* total # of egress queues */ 679 680 struct sge_iq fwq; /* Firmware event queue */ 681 struct sge_wrq mgmtq; /* Management queue (control queue) */ 682 struct sge_wrq *ctrlq; /* Control queues */ 683 struct sge_txq *txq; /* NIC tx queues */ 684 struct sge_rxq *rxq; /* NIC rx queues */ 685 #ifdef TCP_OFFLOAD 686 struct sge_wrq *ofld_txq; /* TOE tx queues */ 687 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 688 #endif 689 #ifdef DEV_NETMAP 690 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 691 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 692 #endif 693 694 uint16_t iq_start; 695 int eq_start; 696 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 697 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 698 699 int pad_boundary; 700 int pack_boundary; 701 int8_t safe_hwidx1; /* may not have room for metadata */ 702 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 703 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 704 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 705 }; 706 707 struct rss_header; 708 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 709 struct mbuf *); 710 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 711 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 712 713 struct adapter { 714 SLIST_ENTRY(adapter) link; 715 device_t dev; 716 struct cdev *cdev; 717 718 /* PCIe register resources */ 719 int regs_rid; 720 struct resource *regs_res; 721 int msix_rid; 722 struct resource *msix_res; 723 bus_space_handle_t bh; 724 bus_space_tag_t bt; 725 bus_size_t mmio_len; 726 int udbs_rid; 727 struct resource *udbs_res; 728 volatile uint8_t *udbs_base; 729 730 unsigned int pf; 731 unsigned int mbox; 732 733 /* Interrupt information */ 734 int intr_type; 735 int intr_count; 736 struct irq { 737 struct resource *res; 738 int rid; 739 void *tag; 740 } *irq; 741 742 bus_dma_tag_t dmat; /* Parent DMA tag */ 743 744 struct sge sge; 745 int lro_timeout; 746 747 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 748 struct port_info *port[MAX_NPORTS]; 749 uint8_t chan_map[NCHAN]; 750 751 #ifdef TCP_OFFLOAD 752 void *tom_softc; /* (struct tom_data *) */ 753 struct tom_tunables tt; 754 void *iwarp_softc; /* (struct c4iw_dev *) */ 755 void *iscsi_softc; 756 #endif 757 struct l2t_data *l2t; /* L2 table */ 758 struct tid_info tids; 759 760 uint16_t doorbells; 761 int open_device_map; 762 #ifdef TCP_OFFLOAD 763 int offload_map; 764 #endif 765 int flags; 766 767 char ifp_lockname[16]; 768 struct mtx ifp_lock; 769 struct ifnet *ifp; /* tracer ifp */ 770 struct ifmedia media; 771 int traceq; /* iq used by all tracers, -1 if none */ 772 int tracer_valid; /* bitmap of valid tracers */ 773 int tracer_enabled; /* bitmap of enabled tracers */ 774 775 char fw_version[32]; 776 char cfg_file[32]; 777 u_int cfcsum; 778 struct adapter_params params; 779 struct t4_virt_res vres; 780 781 uint16_t linkcaps; 782 uint16_t niccaps; 783 uint16_t toecaps; 784 uint16_t rdmacaps; 785 uint16_t iscsicaps; 786 uint16_t fcoecaps; 787 788 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 789 790 struct mtx sc_lock; 791 char lockname[16]; 792 793 /* Starving free lists */ 794 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 795 TAILQ_HEAD(, sge_fl) sfl; 796 struct callout sfl_callout; 797 798 struct mtx regwin_lock; /* for indirect reads and memory windows */ 799 800 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 801 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 802 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 803 804 #ifdef INVARIANTS 805 const char *last_op; 806 const void *last_op_thr; 807 #endif 808 809 int sc_do_rxcopy; 810 }; 811 812 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 813 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 814 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 815 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 816 817 /* XXX: not bulletproof, but much better than nothing */ 818 #define ASSERT_SYNCHRONIZED_OP(sc) \ 819 KASSERT(IS_BUSY(sc) && \ 820 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 821 ("%s: operation not synchronized.", __func__)) 822 823 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 824 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 825 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 826 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 827 828 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 829 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 830 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 831 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 832 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 833 834 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 835 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 836 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 837 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 838 839 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 840 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 841 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 842 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 843 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 844 845 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 846 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 847 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 848 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 849 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 850 851 #define for_each_txq(pi, iter, q) \ 852 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 853 iter < pi->ntxq; ++iter, ++q) 854 #define for_each_rxq(pi, iter, q) \ 855 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 856 iter < pi->nrxq; ++iter, ++q) 857 #define for_each_ofld_txq(pi, iter, q) \ 858 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 859 iter < pi->nofldtxq; ++iter, ++q) 860 #define for_each_ofld_rxq(pi, iter, q) \ 861 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 862 iter < pi->nofldrxq; ++iter, ++q) 863 #define for_each_nm_txq(pi, iter, q) \ 864 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \ 865 iter < pi->nnmtxq; ++iter, ++q) 866 #define for_each_nm_rxq(pi, iter, q) \ 867 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \ 868 iter < pi->nnmrxq; ++iter, ++q) 869 870 #define IDXINCR(idx, incr, wrap) do { \ 871 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 872 } while (0) 873 #define IDXDIFF(head, tail, wrap) \ 874 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 875 876 /* One for errors, one for firmware events */ 877 #define T4_EXTRA_INTR 2 878 879 static inline uint32_t 880 t4_read_reg(struct adapter *sc, uint32_t reg) 881 { 882 883 return bus_space_read_4(sc->bt, sc->bh, reg); 884 } 885 886 static inline void 887 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 888 { 889 890 bus_space_write_4(sc->bt, sc->bh, reg, val); 891 } 892 893 static inline uint64_t 894 t4_read_reg64(struct adapter *sc, uint32_t reg) 895 { 896 897 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 898 } 899 900 static inline void 901 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 902 { 903 904 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 905 } 906 907 static inline void 908 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 909 { 910 911 *val = pci_read_config(sc->dev, reg, 1); 912 } 913 914 static inline void 915 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 916 { 917 918 pci_write_config(sc->dev, reg, val, 1); 919 } 920 921 static inline void 922 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 923 { 924 925 *val = pci_read_config(sc->dev, reg, 2); 926 } 927 928 static inline void 929 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 930 { 931 932 pci_write_config(sc->dev, reg, val, 2); 933 } 934 935 static inline void 936 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 937 { 938 939 *val = pci_read_config(sc->dev, reg, 4); 940 } 941 942 static inline void 943 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 944 { 945 946 pci_write_config(sc->dev, reg, val, 4); 947 } 948 949 static inline struct port_info * 950 adap2pinfo(struct adapter *sc, int idx) 951 { 952 953 return (sc->port[idx]); 954 } 955 956 static inline void 957 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 958 { 959 960 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 961 } 962 963 static inline bool 964 is_10G_port(const struct port_info *pi) 965 { 966 967 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 968 } 969 970 static inline bool 971 is_40G_port(const struct port_info *pi) 972 { 973 974 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 975 } 976 977 static inline int 978 tx_resume_threshold(struct sge_eq *eq) 979 { 980 981 return (eq->qsize / 4); 982 } 983 984 /* t4_main.c */ 985 void t4_tx_task(void *, int); 986 void t4_tx_callout(void *); 987 int t4_os_find_pci_capability(struct adapter *, int); 988 int t4_os_pci_save_state(struct adapter *); 989 int t4_os_pci_restore_state(struct adapter *); 990 void t4_os_portmod_changed(const struct adapter *, int); 991 void t4_os_link_changed(struct adapter *, int, int, int); 992 void t4_iterate(void (*)(struct adapter *, void *), void *); 993 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 994 int t4_register_an_handler(struct adapter *, an_handler_t); 995 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 996 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 997 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 998 void end_synchronized_op(struct adapter *, int); 999 int update_mac_settings(struct ifnet *, int); 1000 int adapter_full_init(struct adapter *); 1001 int adapter_full_uninit(struct adapter *); 1002 int port_full_init(struct port_info *); 1003 int port_full_uninit(struct port_info *); 1004 1005 #ifdef DEV_NETMAP 1006 /* t4_netmap.c */ 1007 int create_netmap_ifnet(struct port_info *); 1008 int destroy_netmap_ifnet(struct port_info *); 1009 void t4_nm_intr(void *); 1010 #endif 1011 1012 /* t4_sge.c */ 1013 void t4_sge_modload(void); 1014 void t4_sge_modunload(void); 1015 uint64_t t4_sge_extfree_refs(void); 1016 void t4_init_sge_cpl_handlers(struct adapter *); 1017 void t4_tweak_chip_settings(struct adapter *); 1018 int t4_read_chip_settings(struct adapter *); 1019 int t4_create_dma_tag(struct adapter *); 1020 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1021 struct sysctl_oid_list *); 1022 int t4_destroy_dma_tag(struct adapter *); 1023 int t4_setup_adapter_queues(struct adapter *); 1024 int t4_teardown_adapter_queues(struct adapter *); 1025 int t4_setup_port_queues(struct port_info *); 1026 int t4_teardown_port_queues(struct port_info *); 1027 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 1028 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 1029 void t4_intr_all(void *); 1030 void t4_intr(void *); 1031 void t4_intr_err(void *); 1032 void t4_intr_evt(void *); 1033 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1034 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 1035 void t4_update_fl_bufsize(struct ifnet *); 1036 int can_resume_tx(struct sge_eq *); 1037 1038 /* t4_tracer.c */ 1039 struct t4_tracer; 1040 void t4_tracer_modload(void); 1041 void t4_tracer_modunload(void); 1042 void t4_tracer_port_detach(struct adapter *); 1043 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1044 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1045 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1046 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1047 1048 static inline struct wrqe * 1049 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1050 { 1051 int len = offsetof(struct wrqe, wr) + wr_len; 1052 struct wrqe *wr; 1053 1054 wr = malloc(len, M_CXGBE, M_NOWAIT); 1055 if (__predict_false(wr == NULL)) 1056 return (NULL); 1057 wr->wr_len = wr_len; 1058 wr->wrq = wrq; 1059 return (wr); 1060 } 1061 1062 static inline void * 1063 wrtod(struct wrqe *wr) 1064 { 1065 return (&wr->wr[0]); 1066 } 1067 1068 static inline void 1069 free_wrqe(struct wrqe *wr) 1070 { 1071 free(wr, M_CXGBE); 1072 } 1073 1074 static inline void 1075 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1076 { 1077 struct sge_wrq *wrq = wr->wrq; 1078 1079 TXQ_LOCK(wrq); 1080 t4_wrq_tx_locked(sc, wrq, wr); 1081 TXQ_UNLOCK(wrq); 1082 } 1083 1084 #endif 1085