xref: /freebsd/sys/dev/cxgbe/adapter.h (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 Chelsio Communications, Inc.
5  * All rights reserved.
6  * Written by: Navdeep Parhar <np@FreeBSD.org>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  *
31  */
32 
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
35 
36 #include <sys/kernel.h>
37 #include <sys/bus.h>
38 #include <sys/counter.h>
39 #include <sys/rman.h>
40 #include <sys/types.h>
41 #include <sys/lock.h>
42 #include <sys/malloc.h>
43 #include <sys/rwlock.h>
44 #include <sys/sx.h>
45 #include <sys/vmem.h>
46 #include <vm/uma.h>
47 
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <machine/bus.h>
51 #include <sys/socket.h>
52 #include <sys/sysctl.h>
53 #include <net/ethernet.h>
54 #include <net/if.h>
55 #include <net/if_var.h>
56 #include <net/if_media.h>
57 #include <net/pfil.h>
58 #include <netinet/in.h>
59 #include <netinet/tcp_lro.h>
60 
61 #include "offload.h"
62 #include "t4_ioctl.h"
63 #include "common/t4_msg.h"
64 #include "firmware/t4fw_interface.h"
65 
66 #define KTR_CXGBE	KTR_SPARE3
67 MALLOC_DECLARE(M_CXGBE);
68 #define CXGBE_UNIMPLEMENTED(s) \
69     panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
70 
71 #if defined(__i386__) || defined(__amd64__)
72 static __inline void
73 prefetch(void *x)
74 {
75 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
76 }
77 #else
78 #define prefetch(x) __builtin_prefetch(x)
79 #endif
80 
81 #ifndef SYSCTL_ADD_UQUAD
82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
83 #define sysctl_handle_64 sysctl_handle_quad
84 #define CTLTYPE_U64 CTLTYPE_QUAD
85 #endif
86 
87 SYSCTL_DECL(_hw_cxgbe);
88 
89 struct adapter;
90 typedef struct adapter adapter_t;
91 
92 enum {
93 	/*
94 	 * All ingress queues use this entry size.  Note that the firmware event
95 	 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
96 	 * be at least 64.
97 	 */
98 	IQ_ESIZE = 64,
99 
100 	/* Default queue sizes for all kinds of ingress queues */
101 	FW_IQ_QSIZE = 256,
102 	RX_IQ_QSIZE = 1024,
103 
104 	/* All egress queues use this entry size */
105 	EQ_ESIZE = 64,
106 
107 	/* Default queue sizes for all kinds of egress queues */
108 	CTRL_EQ_QSIZE = 1024,
109 	TX_EQ_QSIZE = 1024,
110 
111 #if MJUMPAGESIZE != MCLBYTES
112 	SW_ZONE_SIZES = 4,	/* cluster, jumbop, jumbo9k, jumbo16k */
113 #else
114 	SW_ZONE_SIZES = 3,	/* cluster, jumbo9k, jumbo16k */
115 #endif
116 	CL_METADATA_SIZE = CACHE_LINE_SIZE,
117 
118 	SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
119 	TX_SGL_SEGS = 39,
120 	TX_SGL_SEGS_TSO = 38,
121 	TX_SGL_SEGS_VM = 38,
122 	TX_SGL_SEGS_VM_TSO = 37,
123 	TX_SGL_SEGS_EO_TSO = 30,	/* XXX: lower for IPv6. */
124 	TX_SGL_SEGS_VXLAN_TSO = 37,
125 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
126 };
127 
128 enum {
129 	/* adapter intr_type */
130 	INTR_INTX	= (1 << 0),
131 	INTR_MSI 	= (1 << 1),
132 	INTR_MSIX	= (1 << 2)
133 };
134 
135 enum {
136 	XGMAC_MTU	= (1 << 0),
137 	XGMAC_PROMISC	= (1 << 1),
138 	XGMAC_ALLMULTI	= (1 << 2),
139 	XGMAC_VLANEX	= (1 << 3),
140 	XGMAC_UCADDR	= (1 << 4),
141 	XGMAC_MCADDRS	= (1 << 5),
142 
143 	XGMAC_ALL	= 0xffff
144 };
145 
146 enum {
147 	/* flags understood by begin_synchronized_op */
148 	HOLD_LOCK	= (1 << 0),
149 	SLEEP_OK	= (1 << 1),
150 	INTR_OK		= (1 << 2),
151 
152 	/* flags understood by end_synchronized_op */
153 	LOCK_HELD	= HOLD_LOCK,
154 };
155 
156 enum {
157 	/* adapter flags */
158 	FULL_INIT_DONE	= (1 << 0),
159 	FW_OK		= (1 << 1),
160 	CHK_MBOX_ACCESS	= (1 << 2),
161 	MASTER_PF	= (1 << 3),
162 	ADAP_SYSCTL_CTX	= (1 << 4),
163 	ADAP_ERR	= (1 << 5),
164 	BUF_PACKING_OK	= (1 << 6),
165 	IS_VF		= (1 << 7),
166 	KERN_TLS_OK	= (1 << 8),
167 
168 	CXGBE_BUSY	= (1 << 9),
169 
170 	/* port flags */
171 	HAS_TRACEQ	= (1 << 3),
172 	FIXED_IFMEDIA	= (1 << 4),	/* ifmedia list doesn't change. */
173 
174 	/* VI flags */
175 	DOOMED		= (1 << 0),
176 	VI_INIT_DONE	= (1 << 1),
177 	VI_SYSCTL_CTX	= (1 << 2),
178 	TX_USES_VM_WR 	= (1 << 3),
179 
180 	/* adapter debug_flags */
181 	DF_DUMP_MBOX		= (1 << 0),	/* Log all mbox cmd/rpl. */
182 	DF_LOAD_FW_ANYTIME	= (1 << 1),	/* Allow LOAD_FW after init */
183 	DF_DISABLE_TCB_CACHE	= (1 << 2),	/* Disable TCB cache (T6+) */
184 	DF_DISABLE_CFG_RETRY	= (1 << 3),	/* Disable fallback config */
185 	DF_VERBOSE_SLOWINTR	= (1 << 4),	/* Chatty slow intr handler */
186 };
187 
188 #define IS_DOOMED(vi)	((vi)->flags & DOOMED)
189 #define SET_DOOMED(vi)	do {(vi)->flags |= DOOMED;} while (0)
190 #define IS_BUSY(sc)	((sc)->flags & CXGBE_BUSY)
191 #define SET_BUSY(sc)	do {(sc)->flags |= CXGBE_BUSY;} while (0)
192 #define CLR_BUSY(sc)	do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
193 
194 struct vi_info {
195 	device_t dev;
196 	struct port_info *pi;
197 	struct adapter *adapter;
198 
199 	struct ifnet *ifp;
200 	struct pfil_head *pfil;
201 
202 	unsigned long flags;
203 	int if_flags;
204 
205 	uint16_t *rss, *nm_rss;
206 	uint16_t viid;		/* opaque VI identifier */
207 	uint16_t smt_idx;
208 	uint16_t vin;
209 	uint8_t vfvld;
210 	int16_t  xact_addr_filt;/* index of exact MAC address filter */
211 	uint16_t rss_size;	/* size of VI's RSS table slice */
212 	uint16_t rss_base;	/* start of VI's RSS table slice */
213 	int hashen;
214 
215 	int nintr;
216 	int first_intr;
217 
218 	/* These need to be int as they are used in sysctl */
219 	int ntxq;		/* # of tx queues */
220 	int first_txq;		/* index of first tx queue */
221 	int rsrv_noflowq; 	/* Reserve queue 0 for non-flowid packets */
222 	int nrxq;		/* # of rx queues */
223 	int first_rxq;		/* index of first rx queue */
224 	int nofldtxq;		/* # of offload tx queues */
225 	int first_ofld_txq;	/* index of first offload tx queue */
226 	int nofldrxq;		/* # of offload rx queues */
227 	int first_ofld_rxq;	/* index of first offload rx queue */
228 	int nnmtxq;
229 	int first_nm_txq;
230 	int nnmrxq;
231 	int first_nm_rxq;
232 	int tmr_idx;
233 	int ofld_tmr_idx;
234 	int pktc_idx;
235 	int ofld_pktc_idx;
236 	int qsize_rxq;
237 	int qsize_txq;
238 
239 	struct timeval last_refreshed;
240 	struct fw_vi_stats_vf stats;
241 
242 	struct callout tick;
243 	struct sysctl_ctx_list ctx;	/* from ifconfig up to driver detach */
244 
245 	uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
246 };
247 
248 struct tx_ch_rl_params {
249 	enum fw_sched_params_rate ratemode;	/* %port (REL) or kbps (ABS) */
250 	uint32_t maxrate;
251 };
252 
253 enum {
254 	CLRL_USER	= (1 << 0),	/* allocated manually. */
255 	CLRL_SYNC	= (1 << 1),	/* sync hw update in progress. */
256 	CLRL_ASYNC	= (1 << 2),	/* async hw update requested. */
257 	CLRL_ERR	= (1 << 3),	/* last hw setup ended in error. */
258 };
259 
260 struct tx_cl_rl_params {
261 	int refcount;
262 	uint8_t flags;
263 	enum fw_sched_params_rate ratemode;	/* %port REL or ABS value */
264 	enum fw_sched_params_unit rateunit;	/* kbps or pps (when ABS) */
265 	enum fw_sched_params_mode mode;		/* aggr or per-flow */
266 	uint32_t maxrate;
267 	uint16_t pktsize;
268 	uint16_t burstsize;
269 };
270 
271 /* Tx scheduler parameters for a channel/port */
272 struct tx_sched_params {
273 	/* Channel Rate Limiter */
274 	struct tx_ch_rl_params ch_rl;
275 
276 	/* Class WRR */
277 	/* XXX */
278 
279 	/* Class Rate Limiter (including the default pktsize and burstsize). */
280 	int pktsize;
281 	int burstsize;
282 	struct tx_cl_rl_params cl_rl[];
283 };
284 
285 struct port_info {
286 	device_t dev;
287 	struct adapter *adapter;
288 
289 	struct vi_info *vi;
290 	int nvi;
291 	int up_vis;
292 	int uld_vis;
293 	bool vxlan_tcam_entry;
294 
295 	struct tx_sched_params *sched_params;
296 
297 	struct mtx pi_lock;
298 	char lockname[16];
299 	unsigned long flags;
300 
301 	uint8_t  lport;		/* associated offload logical port */
302 	int8_t   mdio_addr;
303 	uint8_t  port_type;
304 	uint8_t  mod_type;
305 	uint8_t  port_id;
306 	uint8_t  tx_chan;
307 	uint8_t  mps_bg_map;	/* rx MPS buffer group bitmap */
308 	uint8_t  rx_e_chan_map;	/* rx TP e-channel bitmap */
309 
310 	struct link_config link_cfg;
311 	struct ifmedia media;
312 
313 	struct timeval last_refreshed;
314  	struct port_stats stats;
315 	u_int tnl_cong_drops;
316 	u_int tx_parse_error;
317 	int fcs_reg;
318 	uint64_t fcs_base;
319 	u_long	tx_toe_tls_records;
320 	u_long	tx_toe_tls_octets;
321 	u_long	rx_toe_tls_records;
322 	u_long	rx_toe_tls_octets;
323 
324 	struct callout tick;
325 };
326 
327 #define	IS_MAIN_VI(vi)		((vi) == &((vi)->pi->vi[0]))
328 
329 struct cluster_metadata {
330 	uma_zone_t zone;
331 	caddr_t cl;
332 	u_int refcount;
333 };
334 
335 struct fl_sdesc {
336 	caddr_t cl;
337 	uint16_t nmbuf;	/* # of driver originated mbufs with ref on cluster */
338 	int16_t moff;	/* offset of metadata from cl */
339 	uint8_t zidx;
340 };
341 
342 struct tx_desc {
343 	__be64 flit[8];
344 };
345 
346 struct tx_sdesc {
347 	struct mbuf *m;		/* m_nextpkt linked chain of frames */
348 	uint8_t desc_used;	/* # of hardware descriptors used by the WR */
349 };
350 
351 
352 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
353 struct iq_desc {
354 	struct rss_header rss;
355 	uint8_t cpl[IQ_PAD];
356 	struct rsp_ctrl rsp;
357 };
358 #undef IQ_PAD
359 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
360 
361 enum {
362 	/* iq flags */
363 	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
364 	IQ_HAS_FL	= (1 << 1),	/* iq associated with a freelist */
365 	IQ_RX_TIMESTAMP	= (1 << 2),	/* provide the SGE rx timestamp */
366 	IQ_LRO_ENABLED	= (1 << 3),	/* iq is an eth rxq with LRO enabled */
367 	IQ_ADJ_CREDIT	= (1 << 4),	/* hw is off by 1 credit for this iq */
368 
369 	/* iq state */
370 	IQS_DISABLED	= 0,
371 	IQS_BUSY	= 1,
372 	IQS_IDLE	= 2,
373 
374 	/* netmap related flags */
375 	NM_OFF	= 0,
376 	NM_ON	= 1,
377 	NM_BUSY	= 2,
378 };
379 
380 enum {
381 	CPL_COOKIE_RESERVED = 0,
382 	CPL_COOKIE_FILTER,
383 	CPL_COOKIE_DDP0,
384 	CPL_COOKIE_DDP1,
385 	CPL_COOKIE_TOM,
386 	CPL_COOKIE_HASHFILTER,
387 	CPL_COOKIE_ETHOFLD,
388 	CPL_COOKIE_KERN_TLS,
389 
390 	NUM_CPL_COOKIES = 8	/* Limited by M_COOKIE.  Do not increase. */
391 };
392 
393 struct sge_iq;
394 struct rss_header;
395 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
396     struct mbuf *);
397 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
398 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
399 
400 /*
401  * Ingress Queue: T4 is producer, driver is consumer.
402  */
403 struct sge_iq {
404 	uint32_t flags;
405 	volatile int state;
406 	struct adapter *adapter;
407 	struct iq_desc  *desc;	/* KVA of descriptor ring */
408 	int8_t   intr_pktc_idx;	/* packet count threshold index */
409 	uint8_t  gen;		/* generation bit */
410 	uint8_t  intr_params;	/* interrupt holdoff parameters */
411 	uint8_t  intr_next;	/* XXX: holdoff for next interrupt */
412 	uint16_t qsize;		/* size (# of entries) of the queue */
413 	uint16_t sidx;		/* index of the entry with the status page */
414 	uint16_t cidx;		/* consumer index */
415 	uint16_t cntxt_id;	/* SGE context id for the iq */
416 	uint16_t abs_id;	/* absolute SGE id for the iq */
417 
418 	STAILQ_ENTRY(sge_iq) link;
419 
420 	bus_dma_tag_t desc_tag;
421 	bus_dmamap_t desc_map;
422 	bus_addr_t ba;		/* bus address of descriptor ring */
423 };
424 
425 enum {
426 	EQ_CTRL		= 1,
427 	EQ_ETH		= 2,
428 	EQ_OFLD		= 3,
429 
430 	/* eq flags */
431 	EQ_TYPEMASK	= 0x3,		/* 2 lsbits hold the type (see above) */
432 	EQ_ALLOCATED	= (1 << 2),	/* firmware resources allocated */
433 	EQ_ENABLED	= (1 << 3),	/* open for business */
434 	EQ_QFLUSH	= (1 << 4),	/* if_qflush in progress */
435 };
436 
437 /* Listed in order of preference.  Update t4_sysctls too if you change these */
438 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
439 
440 /*
441  * Egress Queue: driver is producer, T4 is consumer.
442  *
443  * Note: A free list is an egress queue (driver produces the buffers and T4
444  * consumes them) but it's special enough to have its own struct (see sge_fl).
445  */
446 struct sge_eq {
447 	unsigned int flags;	/* MUST be first */
448 	unsigned int cntxt_id;	/* SGE context id for the eq */
449 	unsigned int abs_id;	/* absolute SGE id for the eq */
450 	struct mtx eq_lock;
451 
452 	struct tx_desc *desc;	/* KVA of descriptor ring */
453 	uint8_t doorbells;
454 	volatile uint32_t *udb;	/* KVA of doorbell (lies within BAR2) */
455 	u_int udb_qid;		/* relative qid within the doorbell page */
456 	uint16_t sidx;		/* index of the entry with the status page */
457 	uint16_t cidx;		/* consumer idx (desc idx) */
458 	uint16_t pidx;		/* producer idx (desc idx) */
459 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
460 	uint16_t dbidx;		/* pidx of the most recent doorbell */
461 	uint16_t iqid;		/* iq that gets egr_update for the eq */
462 	uint8_t tx_chan;	/* tx channel used by the eq */
463 	volatile u_int equiq;	/* EQUIQ outstanding */
464 
465 	bus_dma_tag_t desc_tag;
466 	bus_dmamap_t desc_map;
467 	bus_addr_t ba;		/* bus address of descriptor ring */
468 	char lockname[16];
469 };
470 
471 struct rx_buf_info {
472 	uma_zone_t zone;	/* zone that this cluster comes from */
473 	uint16_t size1;		/* same as size of cluster: 2K/4K/9K/16K.
474 				 * hwsize[hwidx1] = size1.  No spare. */
475 	uint16_t size2;		/* hwsize[hwidx2] = size2.
476 				 * spare in cluster = size1 - size2. */
477 	int8_t hwidx1;		/* SGE bufsize idx for size1 */
478 	int8_t hwidx2;		/* SGE bufsize idx for size2 */
479 	uint8_t type;		/* EXT_xxx type of the cluster */
480 };
481 
482 enum {
483 	NUM_MEMWIN = 3,
484 
485 	MEMWIN0_APERTURE = 2048,
486 	MEMWIN0_BASE     = 0x1b800,
487 
488 	MEMWIN1_APERTURE = 32768,
489 	MEMWIN1_BASE     = 0x28000,
490 
491 	MEMWIN2_APERTURE_T4 = 65536,
492 	MEMWIN2_BASE_T4     = 0x30000,
493 
494 	MEMWIN2_APERTURE_T5 = 128 * 1024,
495 	MEMWIN2_BASE_T5     = 0x60000,
496 };
497 
498 struct memwin {
499 	struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
500 	uint32_t mw_base;	/* constant after setup_memwin */
501 	uint32_t mw_aperture;	/* ditto */
502 	uint32_t mw_curpos;	/* protected by mw_lock */
503 };
504 
505 enum {
506 	FL_STARVING	= (1 << 0), /* on the adapter's list of starving fl's */
507 	FL_DOOMED	= (1 << 1), /* about to be destroyed */
508 	FL_BUF_PACKING	= (1 << 2), /* buffer packing enabled */
509 	FL_BUF_RESUME	= (1 << 3), /* resume from the middle of the frame */
510 };
511 
512 #define FL_RUNNING_LOW(fl) \
513     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
514 #define FL_NOT_RUNNING_LOW(fl) \
515     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
516 
517 struct sge_fl {
518 	struct mtx fl_lock;
519 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
520 	struct fl_sdesc *sdesc;	/* KVA of software descriptor ring */
521 	uint16_t zidx;		/* refill zone idx */
522 	uint16_t safe_zidx;
523 	uint16_t lowat;		/* # of buffers <= this means fl needs help */
524 	int flags;
525 	uint16_t buf_boundary;
526 
527 	/* The 16b idx all deal with hw descriptors */
528 	uint16_t dbidx;		/* hw pidx after last doorbell */
529 	uint16_t sidx;		/* index of status page */
530 	volatile uint16_t hw_cidx;
531 
532 	/* The 32b idx are all buffer idx, not hardware descriptor idx */
533 	uint32_t cidx;		/* consumer index */
534 	uint32_t pidx;		/* producer index */
535 
536 	uint32_t dbval;
537 	u_int rx_offset;	/* offset in fl buf (when buffer packing) */
538 	volatile uint32_t *udb;
539 
540 	uint64_t cl_allocated;	/* # of clusters allocated */
541 	uint64_t cl_recycled;	/* # of clusters recycled */
542 	uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
543 
544 	/* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
545 	struct mbuf *m0;
546 	struct mbuf **pnext;
547 	u_int remaining;
548 
549 	uint16_t qsize;		/* # of hw descriptors (status page included) */
550 	uint16_t cntxt_id;	/* SGE context id for the freelist */
551 	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
552 	bus_dma_tag_t desc_tag;
553 	bus_dmamap_t desc_map;
554 	char lockname[16];
555 	bus_addr_t ba;		/* bus address of descriptor ring */
556 };
557 
558 struct mp_ring;
559 
560 struct txpkts {
561 	uint8_t wr_type;	/* type 0 or type 1 */
562 	uint8_t npkt;		/* # of packets in this work request */
563 	uint8_t len16;		/* # of 16B pieces used by this work request */
564 	uint8_t score;		/* 1-10. coalescing attempted if score > 3 */
565 	uint8_t max_npkt;	/* maximum number of packets allowed */
566 	uint16_t plen;		/* total payload (sum of all packets) */
567 
568 	/* straight from fw_eth_tx_pkts_vm_wr. */
569 	__u8   ethmacdst[6];
570 	__u8   ethmacsrc[6];
571 	__be16 ethtype;
572 	__be16 vlantci;
573 
574 	struct mbuf *mb[15];
575 };
576 
577 /* txq: SGE egress queue + what's needed for Ethernet NIC */
578 struct sge_txq {
579 	struct sge_eq eq;	/* MUST be first */
580 
581 	struct ifnet *ifp;	/* the interface this txq belongs to */
582 	struct mp_ring *r;	/* tx software ring */
583 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
584 	struct sglist *gl;
585 	__be32 cpl_ctrl0;	/* for convenience */
586 	int tc_idx;		/* traffic class */
587 	struct txpkts txp;
588 
589 	struct task tx_reclaim_task;
590 	/* stats for common events first */
591 
592 	uint64_t txcsum;	/* # of times hardware assisted with checksum */
593 	uint64_t tso_wrs;	/* # of TSO work requests */
594 	uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
595 	uint64_t imm_wrs;	/* # of work requests with immediate data */
596 	uint64_t sgl_wrs;	/* # of work requests with direct SGL */
597 	uint64_t txpkt_wrs;	/* # of txpkt work requests (not coalesced) */
598 	uint64_t txpkts0_wrs;	/* # of type0 coalesced tx work requests */
599 	uint64_t txpkts1_wrs;	/* # of type1 coalesced tx work requests */
600 	uint64_t txpkts0_pkts;	/* # of frames in type0 coalesced tx WRs */
601 	uint64_t txpkts1_pkts;	/* # of frames in type1 coalesced tx WRs */
602 	uint64_t raw_wrs;	/* # of raw work requests (alloc_wr_mbuf) */
603 	uint64_t vxlan_tso_wrs;	/* # of VXLAN TSO work requests */
604 	uint64_t vxlan_txcsum;
605 
606 	uint64_t kern_tls_records;
607 	uint64_t kern_tls_short;
608 	uint64_t kern_tls_partial;
609 	uint64_t kern_tls_full;
610 	uint64_t kern_tls_octets;
611 	uint64_t kern_tls_waste;
612 	uint64_t kern_tls_options;
613 	uint64_t kern_tls_header;
614 	uint64_t kern_tls_fin;
615 	uint64_t kern_tls_fin_short;
616 	uint64_t kern_tls_cbc;
617 	uint64_t kern_tls_gcm;
618 
619 	/* stats for not-that-common events */
620 
621 	/* Optional scratch space for constructing work requests. */
622 	uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
623 } __aligned(CACHE_LINE_SIZE);
624 
625 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
626 struct sge_rxq {
627 	struct sge_iq iq;	/* MUST be first */
628 	struct sge_fl fl;	/* MUST follow iq */
629 
630 	struct ifnet *ifp;	/* the interface this rxq belongs to */
631 	struct lro_ctrl lro;	/* LRO state */
632 
633 	/* stats for common events first */
634 
635 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
636 	uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
637 	uint64_t vxlan_rxcsum;
638 
639 	/* stats for not-that-common events */
640 
641 } __aligned(CACHE_LINE_SIZE);
642 
643 static inline struct sge_rxq *
644 iq_to_rxq(struct sge_iq *iq)
645 {
646 
647 	return (__containerof(iq, struct sge_rxq, iq));
648 }
649 
650 
651 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
652 struct sge_ofld_rxq {
653 	struct sge_iq iq;	/* MUST be first */
654 	struct sge_fl fl;	/* MUST follow iq */
655 } __aligned(CACHE_LINE_SIZE);
656 
657 static inline struct sge_ofld_rxq *
658 iq_to_ofld_rxq(struct sge_iq *iq)
659 {
660 
661 	return (__containerof(iq, struct sge_ofld_rxq, iq));
662 }
663 
664 struct wrqe {
665 	STAILQ_ENTRY(wrqe) link;
666 	struct sge_wrq *wrq;
667 	int wr_len;
668 	char wr[] __aligned(16);
669 };
670 
671 struct wrq_cookie {
672 	TAILQ_ENTRY(wrq_cookie) link;
673 	int ndesc;
674 	int pidx;
675 };
676 
677 /*
678  * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
679  * and offload tx queues are of this type.
680  */
681 struct sge_wrq {
682 	struct sge_eq eq;	/* MUST be first */
683 
684 	struct adapter *adapter;
685 	struct task wrq_tx_task;
686 
687 	/* Tx desc reserved but WR not "committed" yet. */
688 	TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
689 
690 	/* List of WRs ready to go out as soon as descriptors are available. */
691 	STAILQ_HEAD(, wrqe) wr_list;
692 	u_int nwr_pending;
693 	u_int ndesc_needed;
694 
695 	/* stats for common events first */
696 
697 	uint64_t tx_wrs_direct;	/* # of WRs written directly to desc ring. */
698 	uint64_t tx_wrs_ss;	/* # of WRs copied from scratch space. */
699 	uint64_t tx_wrs_copied;	/* # of WRs queued and copied to desc ring. */
700 
701 	/* stats for not-that-common events */
702 
703 	/*
704 	 * Scratch space for work requests that wrap around after reaching the
705 	 * status page, and some information about the last WR that used it.
706 	 */
707 	uint16_t ss_pidx;
708 	uint16_t ss_len;
709 	uint8_t ss[SGE_MAX_WR_LEN];
710 
711 } __aligned(CACHE_LINE_SIZE);
712 
713 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
714 struct sge_nm_rxq {
715 	/* Items used by the driver rx ithread are in this cacheline. */
716 	volatile int nm_state __aligned(CACHE_LINE_SIZE);	/* NM_OFF, NM_ON, or NM_BUSY */
717 	u_int nid;		/* netmap ring # for this queue */
718 	struct vi_info *vi;
719 
720 	struct iq_desc *iq_desc;
721 	uint16_t iq_abs_id;
722 	uint16_t iq_cntxt_id;
723 	uint16_t iq_cidx;
724 	uint16_t iq_sidx;
725 	uint8_t iq_gen;
726 	uint32_t fl_sidx;
727 
728 	/* Items used by netmap rxsync are in this cacheline. */
729 	__be64  *fl_desc __aligned(CACHE_LINE_SIZE);
730 	uint16_t fl_cntxt_id;
731 	uint32_t fl_pidx;
732 	uint32_t fl_sidx2;	/* copy of fl_sidx */
733 	uint32_t fl_db_val;
734 	u_int fl_db_saved;
735 	u_int fl_db_threshold;	/* in descriptors */
736 	u_int fl_hwidx:4;
737 
738 	/*
739 	 * fl_cidx is used by both the ithread and rxsync, the rest are not used
740 	 * in the rx fast path.
741 	 */
742 	uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
743 
744 	bus_dma_tag_t iq_desc_tag;
745 	bus_dmamap_t iq_desc_map;
746 	bus_addr_t iq_ba;
747 	int intr_idx;
748 
749 	bus_dma_tag_t fl_desc_tag;
750 	bus_dmamap_t fl_desc_map;
751 	bus_addr_t fl_ba;
752 };
753 
754 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
755 struct sge_nm_txq {
756 	struct tx_desc *desc;
757 	uint16_t cidx;
758 	uint16_t pidx;
759 	uint16_t sidx;
760 	uint16_t equiqidx;	/* EQUIQ last requested at this pidx */
761 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
762 	uint16_t dbidx;		/* pidx of the most recent doorbell */
763 	uint8_t doorbells;
764 	volatile uint32_t *udb;
765 	u_int udb_qid;
766 	u_int cntxt_id;
767 	__be32 cpl_ctrl0;	/* for convenience */
768 	__be32 op_pkd;		/* ditto */
769 	u_int nid;		/* netmap ring # for this queue */
770 
771 	/* infrequently used items after this */
772 
773 	bus_dma_tag_t desc_tag;
774 	bus_dmamap_t desc_map;
775 	bus_addr_t ba;
776 	int iqidx;
777 } __aligned(CACHE_LINE_SIZE);
778 
779 struct sge {
780 	int nrxq;	/* total # of Ethernet rx queues */
781 	int ntxq;	/* total # of Ethernet tx queues */
782 	int nofldrxq;	/* total # of TOE rx queues */
783 	int nofldtxq;	/* total # of TOE tx queues */
784 	int nnmrxq;	/* total # of netmap rx queues */
785 	int nnmtxq;	/* total # of netmap tx queues */
786 	int niq;	/* total # of ingress queues */
787 	int neq;	/* total # of egress queues */
788 
789 	struct sge_iq fwq;	/* Firmware event queue */
790 	struct sge_wrq *ctrlq;	/* Control queues */
791 	struct sge_txq *txq;	/* NIC tx queues */
792 	struct sge_rxq *rxq;	/* NIC rx queues */
793 	struct sge_wrq *ofld_txq;	/* TOE tx queues */
794 	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
795 	struct sge_nm_txq *nm_txq;	/* netmap tx queues */
796 	struct sge_nm_rxq *nm_rxq;	/* netmap rx queues */
797 
798 	uint16_t iq_start;	/* first cntxt_id */
799 	uint16_t iq_base;	/* first abs_id */
800 	int eq_start;		/* first cntxt_id */
801 	int eq_base;		/* first abs_id */
802 	int iqmap_sz;
803 	int eqmap_sz;
804 	struct sge_iq **iqmap;	/* iq->cntxt_id to iq mapping */
805 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
806 
807 	int8_t safe_zidx;
808 	struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
809 };
810 
811 struct devnames {
812 	const char *nexus_name;
813 	const char *ifnet_name;
814 	const char *vi_ifnet_name;
815 	const char *pf03_drv_name;
816 	const char *vf_nexus_name;
817 	const char *vf_ifnet_name;
818 };
819 
820 struct clip_entry;
821 
822 struct adapter {
823 	SLIST_ENTRY(adapter) link;
824 	device_t dev;
825 	struct cdev *cdev;
826 	const struct devnames *names;
827 
828 	/* PCIe register resources */
829 	int regs_rid;
830 	struct resource *regs_res;
831 	int msix_rid;
832 	struct resource *msix_res;
833 	bus_space_handle_t bh;
834 	bus_space_tag_t bt;
835 	bus_size_t mmio_len;
836 	int udbs_rid;
837 	struct resource *udbs_res;
838 	volatile uint8_t *udbs_base;
839 
840 	unsigned int pf;
841 	unsigned int mbox;
842 	unsigned int vpd_busy;
843 	unsigned int vpd_flag;
844 
845 	/* Interrupt information */
846 	int intr_type;
847 	int intr_count;
848 	struct irq {
849 		struct resource *res;
850 		int rid;
851 		void *tag;
852 		struct sge_rxq *rxq;
853 		struct sge_nm_rxq *nm_rxq;
854 	} __aligned(CACHE_LINE_SIZE) *irq;
855 	int sge_gts_reg;
856 	int sge_kdoorbell_reg;
857 
858 	bus_dma_tag_t dmat;	/* Parent DMA tag */
859 
860 	struct sge sge;
861 	int lro_timeout;
862 	int sc_do_rxcopy;
863 
864 	int vxlan_port;
865 	u_int vxlan_refcount;
866 	int rawf_base;
867 	int nrawf;
868 
869 	struct taskqueue *tq[MAX_NCHAN];	/* General purpose taskqueues */
870 	struct task async_event_task;
871 	struct port_info *port[MAX_NPORTS];
872 	uint8_t chan_map[MAX_NCHAN];		/* channel -> port */
873 
874 	struct mtx clip_table_lock;
875 	TAILQ_HEAD(, clip_entry) clip_table;
876 	int clip_gen;
877 
878 	void *tom_softc;	/* (struct tom_data *) */
879 	struct tom_tunables tt;
880 	struct t4_offload_policy *policy;
881 	struct rwlock policy_lock;
882 
883 	void *iwarp_softc;	/* (struct c4iw_dev *) */
884 	struct iw_tunables iwt;
885 	void *iscsi_ulp_softc;	/* (struct cxgbei_data *) */
886 	void *ccr_softc;	/* (struct ccr_softc *) */
887 	struct l2t_data *l2t;	/* L2 table */
888 	struct smt_data *smt;	/* Source MAC Table */
889 	struct tid_info tids;
890 	vmem_t *key_map;
891 	struct tls_tunables tlst;
892 
893 	uint8_t doorbells;
894 	int offload_map;	/* ports with IFCAP_TOE enabled */
895 	int active_ulds;	/* ULDs activated on this adapter */
896 	int flags;
897 	int debug_flags;
898 
899 	char ifp_lockname[16];
900 	struct mtx ifp_lock;
901 	struct ifnet *ifp;	/* tracer ifp */
902 	struct ifmedia media;
903 	int traceq;		/* iq used by all tracers, -1 if none */
904 	int tracer_valid;	/* bitmap of valid tracers */
905 	int tracer_enabled;	/* bitmap of enabled tracers */
906 
907 	char fw_version[16];
908 	char tp_version[16];
909 	char er_version[16];
910 	char bs_version[16];
911 	char cfg_file[32];
912 	u_int cfcsum;
913 	struct adapter_params params;
914 	const struct chip_params *chip_params;
915 	struct t4_virt_res vres;
916 
917 	uint16_t nbmcaps;
918 	uint16_t linkcaps;
919 	uint16_t switchcaps;
920 	uint16_t niccaps;
921 	uint16_t toecaps;
922 	uint16_t rdmacaps;
923 	uint16_t cryptocaps;
924 	uint16_t iscsicaps;
925 	uint16_t fcoecaps;
926 
927 	struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
928 
929 	struct mtx sc_lock;
930 	char lockname[16];
931 
932 	/* Starving free lists */
933 	struct mtx sfl_lock;	/* same cache-line as sc_lock? but that's ok */
934 	TAILQ_HEAD(, sge_fl) sfl;
935 	struct callout sfl_callout;
936 
937 	struct mtx reg_lock;	/* for indirect register access */
938 
939 	struct memwin memwin[NUM_MEMWIN];	/* memory windows */
940 
941 	struct mtx tc_lock;
942 	struct task tc_task;
943 
944 	const char *last_op;
945 	const void *last_op_thr;
946 	int last_op_flags;
947 
948 	int swintr;
949 	int sensor_resets;
950 
951 	struct callout ktls_tick;
952 };
953 
954 #define ADAPTER_LOCK(sc)		mtx_lock(&(sc)->sc_lock)
955 #define ADAPTER_UNLOCK(sc)		mtx_unlock(&(sc)->sc_lock)
956 #define ADAPTER_LOCK_ASSERT_OWNED(sc)	mtx_assert(&(sc)->sc_lock, MA_OWNED)
957 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
958 
959 #define ASSERT_SYNCHRONIZED_OP(sc)	\
960     KASSERT(IS_BUSY(sc) && \
961 	(mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
962 	("%s: operation not synchronized.", __func__))
963 
964 #define PORT_LOCK(pi)			mtx_lock(&(pi)->pi_lock)
965 #define PORT_UNLOCK(pi)			mtx_unlock(&(pi)->pi_lock)
966 #define PORT_LOCK_ASSERT_OWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_OWNED)
967 #define PORT_LOCK_ASSERT_NOTOWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
968 
969 #define FL_LOCK(fl)			mtx_lock(&(fl)->fl_lock)
970 #define FL_TRYLOCK(fl)			mtx_trylock(&(fl)->fl_lock)
971 #define FL_UNLOCK(fl)			mtx_unlock(&(fl)->fl_lock)
972 #define FL_LOCK_ASSERT_OWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_OWNED)
973 #define FL_LOCK_ASSERT_NOTOWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
974 
975 #define RXQ_FL_LOCK(rxq)		FL_LOCK(&(rxq)->fl)
976 #define RXQ_FL_UNLOCK(rxq)		FL_UNLOCK(&(rxq)->fl)
977 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq)	FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
978 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
979 
980 #define EQ_LOCK(eq)			mtx_lock(&(eq)->eq_lock)
981 #define EQ_TRYLOCK(eq)			mtx_trylock(&(eq)->eq_lock)
982 #define EQ_UNLOCK(eq)			mtx_unlock(&(eq)->eq_lock)
983 #define EQ_LOCK_ASSERT_OWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_OWNED)
984 #define EQ_LOCK_ASSERT_NOTOWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
985 
986 #define TXQ_LOCK(txq)			EQ_LOCK(&(txq)->eq)
987 #define TXQ_TRYLOCK(txq)		EQ_TRYLOCK(&(txq)->eq)
988 #define TXQ_UNLOCK(txq)			EQ_UNLOCK(&(txq)->eq)
989 #define TXQ_LOCK_ASSERT_OWNED(txq)	EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
990 #define TXQ_LOCK_ASSERT_NOTOWNED(txq)	EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
991 
992 #define for_each_txq(vi, iter, q) \
993 	for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
994 	    iter < vi->ntxq; ++iter, ++q)
995 #define for_each_rxq(vi, iter, q) \
996 	for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
997 	    iter < vi->nrxq; ++iter, ++q)
998 #define for_each_ofld_txq(vi, iter, q) \
999 	for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
1000 	    iter < vi->nofldtxq; ++iter, ++q)
1001 #define for_each_ofld_rxq(vi, iter, q) \
1002 	for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
1003 	    iter < vi->nofldrxq; ++iter, ++q)
1004 #define for_each_nm_txq(vi, iter, q) \
1005 	for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
1006 	    iter < vi->nnmtxq; ++iter, ++q)
1007 #define for_each_nm_rxq(vi, iter, q) \
1008 	for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
1009 	    iter < vi->nnmrxq; ++iter, ++q)
1010 #define for_each_vi(_pi, _iter, _vi) \
1011 	for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
1012 	     ++(_iter), ++(_vi))
1013 
1014 #define IDXINCR(idx, incr, wrap) do { \
1015 	idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
1016 } while (0)
1017 #define IDXDIFF(head, tail, wrap) \
1018 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1019 
1020 /* One for errors, one for firmware events */
1021 #define T4_EXTRA_INTR 2
1022 
1023 /* One for firmware events */
1024 #define T4VF_EXTRA_INTR 1
1025 
1026 static inline int
1027 forwarding_intr_to_fwq(struct adapter *sc)
1028 {
1029 
1030 	return (sc->intr_count == 1);
1031 }
1032 
1033 static inline uint32_t
1034 t4_read_reg(struct adapter *sc, uint32_t reg)
1035 {
1036 
1037 	return bus_space_read_4(sc->bt, sc->bh, reg);
1038 }
1039 
1040 static inline void
1041 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1042 {
1043 
1044 	bus_space_write_4(sc->bt, sc->bh, reg, val);
1045 }
1046 
1047 static inline uint64_t
1048 t4_read_reg64(struct adapter *sc, uint32_t reg)
1049 {
1050 
1051 #ifdef __LP64__
1052 	return bus_space_read_8(sc->bt, sc->bh, reg);
1053 #else
1054 	return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1055 	    ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1056 
1057 #endif
1058 }
1059 
1060 static inline void
1061 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1062 {
1063 
1064 #ifdef __LP64__
1065 	bus_space_write_8(sc->bt, sc->bh, reg, val);
1066 #else
1067 	bus_space_write_4(sc->bt, sc->bh, reg, val);
1068 	bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1069 #endif
1070 }
1071 
1072 static inline void
1073 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1074 {
1075 
1076 	*val = pci_read_config(sc->dev, reg, 1);
1077 }
1078 
1079 static inline void
1080 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1081 {
1082 
1083 	pci_write_config(sc->dev, reg, val, 1);
1084 }
1085 
1086 static inline void
1087 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1088 {
1089 
1090 	*val = pci_read_config(sc->dev, reg, 2);
1091 }
1092 
1093 static inline void
1094 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1095 {
1096 
1097 	pci_write_config(sc->dev, reg, val, 2);
1098 }
1099 
1100 static inline void
1101 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1102 {
1103 
1104 	*val = pci_read_config(sc->dev, reg, 4);
1105 }
1106 
1107 static inline void
1108 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1109 {
1110 
1111 	pci_write_config(sc->dev, reg, val, 4);
1112 }
1113 
1114 static inline struct port_info *
1115 adap2pinfo(struct adapter *sc, int idx)
1116 {
1117 
1118 	return (sc->port[idx]);
1119 }
1120 
1121 static inline void
1122 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1123 {
1124 
1125 	bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1126 }
1127 
1128 static inline int
1129 tx_resume_threshold(struct sge_eq *eq)
1130 {
1131 
1132 	/* not quite the same as qsize / 4, but this will do. */
1133 	return (eq->sidx / 4);
1134 }
1135 
1136 static inline int
1137 t4_use_ldst(struct adapter *sc)
1138 {
1139 
1140 #ifdef notyet
1141 	return (sc->flags & FW_OK || !sc->use_bd);
1142 #else
1143 	return (0);
1144 #endif
1145 }
1146 
1147 static inline void
1148 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1149     const char *msg, const __be64 *const p, const bool err)
1150 {
1151 
1152 	if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1153 		return;
1154 	if (p != NULL) {
1155 		log(err ? LOG_ERR : LOG_DEBUG,
1156 		    "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1157 		    "%016llx %016llx %016llx %016llx\n",
1158 		    device_get_nameunit(sc->dev), mbox, msg,
1159 		    (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1160 		    (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1161 		    (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1162 		    (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1163 	} else {
1164 		log(err ? LOG_ERR : LOG_DEBUG,
1165 		    "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1166 		    "%016llx %016llx %016llx %016llx\n",
1167 		    device_get_nameunit(sc->dev), mbox, msg,
1168 		    (long long)t4_read_reg64(sc, reg),
1169 		    (long long)t4_read_reg64(sc, reg + 8),
1170 		    (long long)t4_read_reg64(sc, reg + 16),
1171 		    (long long)t4_read_reg64(sc, reg + 24),
1172 		    (long long)t4_read_reg64(sc, reg + 32),
1173 		    (long long)t4_read_reg64(sc, reg + 40),
1174 		    (long long)t4_read_reg64(sc, reg + 48),
1175 		    (long long)t4_read_reg64(sc, reg + 56));
1176 	}
1177 }
1178 
1179 /* t4_main.c */
1180 extern int t4_ntxq;
1181 extern int t4_nrxq;
1182 extern int t4_intr_types;
1183 extern int t4_tmr_idx;
1184 extern int t4_pktc_idx;
1185 extern unsigned int t4_qsize_rxq;
1186 extern unsigned int t4_qsize_txq;
1187 extern device_method_t cxgbe_methods[];
1188 
1189 int t4_os_find_pci_capability(struct adapter *, int);
1190 int t4_os_pci_save_state(struct adapter *);
1191 int t4_os_pci_restore_state(struct adapter *);
1192 void t4_os_portmod_changed(struct port_info *);
1193 void t4_os_link_changed(struct port_info *);
1194 void t4_iterate(void (*)(struct adapter *, void *), void *);
1195 void t4_init_devnames(struct adapter *);
1196 void t4_add_adapter(struct adapter *);
1197 int t4_detach_common(device_t);
1198 int t4_map_bars_0_and_4(struct adapter *);
1199 int t4_map_bar_2(struct adapter *);
1200 int t4_setup_intr_handlers(struct adapter *);
1201 void t4_sysctls(struct adapter *);
1202 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1203 void doom_vi(struct adapter *, struct vi_info *);
1204 void end_synchronized_op(struct adapter *, int);
1205 int update_mac_settings(struct ifnet *, int);
1206 int adapter_full_init(struct adapter *);
1207 int adapter_full_uninit(struct adapter *);
1208 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1209 int vi_full_init(struct vi_info *);
1210 int vi_full_uninit(struct vi_info *);
1211 void vi_sysctls(struct vi_info *);
1212 void vi_tick(void *);
1213 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1214 int alloc_atid(struct adapter *, void *);
1215 void *lookup_atid(struct adapter *, int);
1216 void free_atid(struct adapter *, int);
1217 void release_tid(struct adapter *, int, struct sge_wrq *);
1218 int cxgbe_media_change(struct ifnet *);
1219 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1220 bool t4_os_dump_cimla(struct adapter *, int, bool);
1221 void t4_os_dump_devlog(struct adapter *);
1222 
1223 #ifdef KERN_TLS
1224 /* t4_kern_tls.c */
1225 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1226     struct m_snd_tag **);
1227 void cxgbe_tls_tag_free(struct m_snd_tag *);
1228 void t6_ktls_modload(void);
1229 void t6_ktls_modunload(void);
1230 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *);
1231 int t6_ktls_parse_pkt(struct mbuf *, int *, int *);
1232 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int);
1233 #endif
1234 
1235 /* t4_keyctx.c */
1236 struct auth_hash;
1237 union authctx;
1238 
1239 void t4_aes_getdeckey(void *, const void *, unsigned int);
1240 void t4_copy_partial_hash(int, union authctx *, void *);
1241 void t4_init_gmac_hash(const char *, int, char *);
1242 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *);
1243 
1244 #ifdef DEV_NETMAP
1245 /* t4_netmap.c */
1246 struct sge_nm_rxq;
1247 void cxgbe_nm_attach(struct vi_info *);
1248 void cxgbe_nm_detach(struct vi_info *);
1249 void service_nm_rxq(struct sge_nm_rxq *);
1250 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
1251     struct sysctl_oid *);
1252 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
1253 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
1254     struct sysctl_oid *);
1255 int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
1256 #endif
1257 
1258 /* t4_sge.c */
1259 void t4_sge_modload(void);
1260 void t4_sge_modunload(void);
1261 uint64_t t4_sge_extfree_refs(void);
1262 void t4_tweak_chip_settings(struct adapter *);
1263 int t4_read_chip_settings(struct adapter *);
1264 int t4_create_dma_tag(struct adapter *);
1265 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1266     struct sysctl_oid_list *);
1267 int t4_destroy_dma_tag(struct adapter *);
1268 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
1269     bus_addr_t *, void **);
1270 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1271     void *);
1272 int sysctl_uint16(SYSCTL_HANDLER_ARGS);
1273 int t4_setup_adapter_queues(struct adapter *);
1274 int t4_teardown_adapter_queues(struct adapter *);
1275 int t4_setup_vi_queues(struct vi_info *);
1276 int t4_teardown_vi_queues(struct vi_info *);
1277 void t4_intr_all(void *);
1278 void t4_intr(void *);
1279 #ifdef DEV_NETMAP
1280 void t4_nm_intr(void *);
1281 void t4_vi_intr(void *);
1282 #endif
1283 void t4_intr_err(void *);
1284 void t4_intr_evt(void *);
1285 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1286 void t4_update_fl_bufsize(struct ifnet *);
1287 struct mbuf *alloc_wr_mbuf(int, int);
1288 int parse_pkt(struct mbuf **, bool);
1289 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1290 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1291 int tnl_cong(struct port_info *, int);
1292 void t4_register_an_handler(an_handler_t);
1293 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1294 void t4_register_cpl_handler(int, cpl_handler_t);
1295 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1296 #ifdef RATELIMIT
1297 int ethofld_transmit(struct ifnet *, struct mbuf *);
1298 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1299 #endif
1300 
1301 /* t4_tracer.c */
1302 struct t4_tracer;
1303 void t4_tracer_modload(void);
1304 void t4_tracer_modunload(void);
1305 void t4_tracer_port_detach(struct adapter *);
1306 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1307 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1308 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1309 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1310 
1311 /* t4_sched.c */
1312 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1313 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1314 int t4_init_tx_sched(struct adapter *);
1315 int t4_free_tx_sched(struct adapter *);
1316 void t4_update_tx_sched(struct adapter *);
1317 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1318 void t4_release_cl_rl(struct adapter *, int, int);
1319 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1320 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1321 #ifdef RATELIMIT
1322 void t4_init_etid_table(struct adapter *);
1323 void t4_free_etid_table(struct adapter *);
1324 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1325 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1326     struct m_snd_tag **);
1327 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1328 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1329 void cxgbe_rate_tag_free(struct m_snd_tag *);
1330 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1331 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *);
1332 #endif
1333 
1334 /* t4_filter.c */
1335 int get_filter_mode(struct adapter *, uint32_t *);
1336 int set_filter_mode(struct adapter *, uint32_t);
1337 int get_filter(struct adapter *, struct t4_filter *);
1338 int set_filter(struct adapter *, struct t4_filter *);
1339 int del_filter(struct adapter *, struct t4_filter *);
1340 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1341 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1342 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1343 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1344 void free_hftid_hash(struct tid_info *);
1345 
1346 static inline struct wrqe *
1347 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1348 {
1349 	int len = offsetof(struct wrqe, wr) + wr_len;
1350 	struct wrqe *wr;
1351 
1352 	wr = malloc(len, M_CXGBE, M_NOWAIT);
1353 	if (__predict_false(wr == NULL))
1354 		return (NULL);
1355 	wr->wr_len = wr_len;
1356 	wr->wrq = wrq;
1357 	return (wr);
1358 }
1359 
1360 static inline void *
1361 wrtod(struct wrqe *wr)
1362 {
1363 	return (&wr->wr[0]);
1364 }
1365 
1366 static inline void
1367 free_wrqe(struct wrqe *wr)
1368 {
1369 	free(wr, M_CXGBE);
1370 }
1371 
1372 static inline void
1373 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1374 {
1375 	struct sge_wrq *wrq = wr->wrq;
1376 
1377 	TXQ_LOCK(wrq);
1378 	t4_wrq_tx_locked(sc, wrq, wr);
1379 	TXQ_UNLOCK(wrq);
1380 }
1381 
1382 static inline int
1383 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1384     int len)
1385 {
1386 
1387 	return (rw_via_memwin(sc, idx, addr, val, len, 0));
1388 }
1389 
1390 static inline int
1391 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1392     const uint32_t *val, int len)
1393 {
1394 
1395 	return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1396 }
1397 
1398 /* Number of len16 -> number of descriptors */
1399 static inline int
1400 tx_len16_to_desc(int len16)
1401 {
1402 
1403 	return (howmany(len16, EQ_ESIZE / 16));
1404 }
1405 #endif
1406