1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/in.h> 48 #include <netinet/tcp_lro.h> 49 50 #include "offload.h" 51 #include "firmware/t4fw_interface.h" 52 53 #define T4_CFGNAME "t4fw_cfg" 54 #define T4_FWNAME "t4fw" 55 56 MALLOC_DECLARE(M_CXGBE); 57 #define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60 #if defined(__i386__) || defined(__amd64__) 61 static __inline void 62 prefetch(void *x) 63 { 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65 } 66 #else 67 #define prefetch(x) 68 #endif 69 70 #ifndef SYSCTL_ADD_UQUAD 71 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72 #define sysctl_handle_64 sysctl_handle_quad 73 #define CTLTYPE_U64 CTLTYPE_QUAD 74 #endif 75 76 #if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78 #define SBUF_DRAIN 1 79 #endif 80 81 #ifdef __amd64__ 82 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 83 static __inline uint64_t 84 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 85 bus_size_t offset) 86 { 87 KASSERT(tag == X86_BUS_SPACE_MEM, 88 ("%s: can only handle mem space", __func__)); 89 90 return (*(volatile uint64_t *)(handle + offset)); 91 } 92 93 static __inline void 94 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 95 bus_size_t offset, uint64_t value) 96 { 97 KASSERT(tag == X86_BUS_SPACE_MEM, 98 ("%s: can only handle mem space", __func__)); 99 100 *(volatile uint64_t *)(bsh + offset) = value; 101 } 102 #else 103 static __inline uint64_t 104 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 105 bus_size_t offset) 106 { 107 return (uint64_t)bus_space_read_4(tag, handle, offset) + 108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 109 } 110 111 static __inline void 112 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 113 bus_size_t offset, uint64_t value) 114 { 115 bus_space_write_4(tag, bsh, offset, value); 116 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 117 } 118 #endif 119 120 struct adapter; 121 typedef struct adapter adapter_t; 122 123 enum { 124 FW_IQ_QSIZE = 256, 125 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 126 127 RX_IQ_QSIZE = 1024, 128 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 129 130 EQ_ESIZE = 64, /* All egress queues use this entry size */ 131 132 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 133 #if MJUMPAGESIZE != MCLBYTES 134 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 135 #else 136 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 137 #endif 138 OFLD_BUF_SIZE = MJUM16BYTES, /* size of fl buffer for TOE rxq */ 139 140 CTRL_EQ_QSIZE = 128, 141 142 TX_EQ_QSIZE = 1024, 143 TX_SGL_SEGS = 36, 144 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 145 }; 146 147 #ifdef T4_PKT_TIMESTAMP 148 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 149 #else 150 #define RX_COPY_THRESHOLD MINCLSIZE 151 #endif 152 153 enum { 154 /* adapter intr_type */ 155 INTR_INTX = (1 << 0), 156 INTR_MSI = (1 << 1), 157 INTR_MSIX = (1 << 2) 158 }; 159 160 enum { 161 /* adapter flags */ 162 FULL_INIT_DONE = (1 << 0), 163 FW_OK = (1 << 1), 164 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 165 MASTER_PF = (1 << 3), 166 ADAP_SYSCTL_CTX = (1 << 4), 167 TOM_INIT_DONE = (1 << 5), 168 169 CXGBE_BUSY = (1 << 9), 170 171 /* port flags */ 172 DOOMED = (1 << 0), 173 PORT_INIT_DONE = (1 << 1), 174 PORT_SYSCTL_CTX = (1 << 2), 175 }; 176 177 #define IS_DOOMED(pi) (pi->flags & DOOMED) 178 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 179 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 180 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 181 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 182 183 struct port_info { 184 device_t dev; 185 struct adapter *adapter; 186 187 struct ifnet *ifp; 188 struct ifmedia media; 189 190 struct mtx pi_lock; 191 char lockname[16]; 192 unsigned long flags; 193 int if_flags; 194 195 uint16_t viid; 196 int16_t xact_addr_filt;/* index of exact MAC address filter */ 197 uint16_t rss_size; /* size of VI's RSS table slice */ 198 uint8_t lport; /* associated offload logical port */ 199 int8_t mdio_addr; 200 uint8_t port_type; 201 uint8_t mod_type; 202 uint8_t port_id; 203 uint8_t tx_chan; 204 205 /* These need to be int as they are used in sysctl */ 206 int ntxq; /* # of tx queues */ 207 int first_txq; /* index of first tx queue */ 208 int nrxq; /* # of rx queues */ 209 int first_rxq; /* index of first rx queue */ 210 #ifdef TCP_OFFLOAD 211 int nofldtxq; /* # of offload tx queues */ 212 int first_ofld_txq; /* index of first offload tx queue */ 213 int nofldrxq; /* # of offload rx queues */ 214 int first_ofld_rxq; /* index of first offload rx queue */ 215 #endif 216 int tmr_idx; 217 int pktc_idx; 218 int qsize_rxq; 219 int qsize_txq; 220 221 struct link_config link_cfg; 222 struct port_stats stats; 223 224 eventhandler_tag vlan_c; 225 226 struct callout tick; 227 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 228 229 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 230 }; 231 232 struct fl_sdesc { 233 struct mbuf *m; 234 bus_dmamap_t map; 235 caddr_t cl; 236 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 237 #ifdef INVARIANTS 238 __be64 ba_tag; 239 #endif 240 }; 241 242 struct tx_desc { 243 __be64 flit[8]; 244 }; 245 246 struct tx_map { 247 struct mbuf *m; 248 bus_dmamap_t map; 249 }; 250 251 /* DMA maps used for tx */ 252 struct tx_maps { 253 struct tx_map *maps; 254 uint32_t map_total; /* # of DMA maps */ 255 uint32_t map_pidx; /* next map to be used */ 256 uint32_t map_cidx; /* reclaimed up to this index */ 257 uint32_t map_avail; /* # of available maps */ 258 }; 259 260 struct tx_sdesc { 261 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 262 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 263 }; 264 265 enum { 266 /* iq flags */ 267 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 268 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 269 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 270 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 271 272 /* iq state */ 273 IQS_DISABLED = 0, 274 IQS_BUSY = 1, 275 IQS_IDLE = 2, 276 }; 277 278 /* 279 * Ingress Queue: T4 is producer, driver is consumer. 280 */ 281 struct sge_iq { 282 bus_dma_tag_t desc_tag; 283 bus_dmamap_t desc_map; 284 bus_addr_t ba; /* bus address of descriptor ring */ 285 uint32_t flags; 286 uint16_t abs_id; /* absolute SGE id for the iq */ 287 int8_t intr_pktc_idx; /* packet count threshold index */ 288 int8_t pad0; 289 __be64 *desc; /* KVA of descriptor ring */ 290 291 volatile int state; 292 struct adapter *adapter; 293 const __be64 *cdesc; /* current descriptor */ 294 uint8_t gen; /* generation bit */ 295 uint8_t intr_params; /* interrupt holdoff parameters */ 296 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 297 uint8_t esize; /* size (bytes) of each entry in the queue */ 298 uint16_t qsize; /* size (# of entries) of the queue */ 299 uint16_t cidx; /* consumer index */ 300 uint16_t cntxt_id; /* SGE context id for the iq */ 301 302 STAILQ_ENTRY(sge_iq) link; 303 }; 304 305 enum { 306 EQ_CTRL = 1, 307 EQ_ETH = 2, 308 #ifdef TCP_OFFLOAD 309 EQ_OFLD = 3, 310 #endif 311 312 /* eq flags */ 313 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 314 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 315 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 316 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 317 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 318 }; 319 320 /* 321 * Egress Queue: driver is producer, T4 is consumer. 322 * 323 * Note: A free list is an egress queue (driver produces the buffers and T4 324 * consumes them) but it's special enough to have its own struct (see sge_fl). 325 */ 326 struct sge_eq { 327 unsigned int flags; /* MUST be first */ 328 unsigned int cntxt_id; /* SGE context id for the eq */ 329 bus_dma_tag_t desc_tag; 330 bus_dmamap_t desc_map; 331 char lockname[16]; 332 struct mtx eq_lock; 333 334 struct tx_desc *desc; /* KVA of descriptor ring */ 335 bus_addr_t ba; /* bus address of descriptor ring */ 336 struct sge_qstat *spg; /* status page, for convenience */ 337 uint16_t cap; /* max # of desc, for convenience */ 338 uint16_t avail; /* available descriptors, for convenience */ 339 uint16_t qsize; /* size (# of entries) of the queue */ 340 uint16_t cidx; /* consumer idx (desc idx) */ 341 uint16_t pidx; /* producer idx (desc idx) */ 342 uint16_t pending; /* # of descriptors used since last doorbell */ 343 uint16_t iqid; /* iq that gets egr_update for the eq */ 344 uint8_t tx_chan; /* tx channel used by the eq */ 345 struct task tx_task; 346 struct callout tx_callout; 347 348 /* stats */ 349 350 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 351 uint32_t unstalled; /* recovered from stall */ 352 }; 353 354 enum { 355 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 356 FL_DOOMED = (1 << 1), /* about to be destroyed */ 357 }; 358 359 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 360 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 361 362 struct sge_fl { 363 bus_dma_tag_t desc_tag; 364 bus_dmamap_t desc_map; 365 bus_dma_tag_t tag[FL_BUF_SIZES]; 366 uint8_t tag_idx; 367 struct mtx fl_lock; 368 char lockname[16]; 369 int flags; 370 371 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 372 bus_addr_t ba; /* bus address of descriptor ring */ 373 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 374 uint32_t cap; /* max # of buffers, for convenience */ 375 uint16_t qsize; /* size (# of entries) of the queue */ 376 uint16_t cntxt_id; /* SGE context id for the freelist */ 377 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 378 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 379 uint32_t needed; /* # of buffers needed to fill up fl. */ 380 uint32_t lowat; /* # of buffers <= this means fl needs help */ 381 uint32_t pending; /* # of bufs allocated since last doorbell */ 382 unsigned int dmamap_failed; 383 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 384 }; 385 386 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 387 struct sge_txq { 388 struct sge_eq eq; /* MUST be first */ 389 390 struct ifnet *ifp; /* the interface this txq belongs to */ 391 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 392 struct buf_ring *br; /* tx buffer ring */ 393 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 394 struct mbuf *m; /* held up due to temporary resource shortage */ 395 396 struct tx_maps txmaps; 397 398 /* stats for common events first */ 399 400 uint64_t txcsum; /* # of times hardware assisted with checksum */ 401 uint64_t tso_wrs; /* # of TSO work requests */ 402 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 403 uint64_t imm_wrs; /* # of work requests with immediate data */ 404 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 405 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 406 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 407 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 408 409 /* stats for not-that-common events */ 410 411 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 412 uint32_t no_desc; /* out of hardware descriptors */ 413 } __aligned(CACHE_LINE_SIZE); 414 415 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 416 struct sge_rxq { 417 struct sge_iq iq; /* MUST be first */ 418 struct sge_fl fl; /* MUST follow iq */ 419 420 struct ifnet *ifp; /* the interface this rxq belongs to */ 421 #if defined(INET) || defined(INET6) 422 struct lro_ctrl lro; /* LRO state */ 423 #endif 424 425 /* stats for common events first */ 426 427 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 428 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 429 430 /* stats for not-that-common events */ 431 432 } __aligned(CACHE_LINE_SIZE); 433 434 static inline struct sge_rxq * 435 iq_to_rxq(struct sge_iq *iq) 436 { 437 438 return (__containerof(iq, struct sge_rxq, iq)); 439 } 440 441 442 #ifdef TCP_OFFLOAD 443 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 444 struct sge_ofld_rxq { 445 struct sge_iq iq; /* MUST be first */ 446 struct sge_fl fl; /* MUST follow iq */ 447 } __aligned(CACHE_LINE_SIZE); 448 449 static inline struct sge_ofld_rxq * 450 iq_to_ofld_rxq(struct sge_iq *iq) 451 { 452 453 return (__containerof(iq, struct sge_ofld_rxq, iq)); 454 } 455 #endif 456 457 struct wrqe { 458 STAILQ_ENTRY(wrqe) link; 459 struct sge_wrq *wrq; 460 int wr_len; 461 uint64_t wr[] __aligned(16); 462 }; 463 464 /* 465 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 466 * and offload tx queues are of this type. 467 */ 468 struct sge_wrq { 469 struct sge_eq eq; /* MUST be first */ 470 471 struct adapter *adapter; 472 473 /* List of WRs held up due to lack of tx descriptors */ 474 STAILQ_HEAD(, wrqe) wr_list; 475 476 /* stats for common events first */ 477 478 uint64_t tx_wrs; /* # of tx work requests */ 479 480 /* stats for not-that-common events */ 481 482 uint32_t no_desc; /* out of hardware descriptors */ 483 } __aligned(CACHE_LINE_SIZE); 484 485 struct sge { 486 int timer_val[SGE_NTIMERS]; 487 int counter_val[SGE_NCOUNTERS]; 488 int fl_starve_threshold; 489 490 int nrxq; /* total # of Ethernet rx queues */ 491 int ntxq; /* total # of Ethernet tx tx queues */ 492 #ifdef TCP_OFFLOAD 493 int nofldrxq; /* total # of TOE rx queues */ 494 int nofldtxq; /* total # of TOE tx queues */ 495 #endif 496 int niq; /* total # of ingress queues */ 497 int neq; /* total # of egress queues */ 498 499 struct sge_iq fwq; /* Firmware event queue */ 500 struct sge_wrq mgmtq; /* Management queue (control queue) */ 501 struct sge_wrq *ctrlq; /* Control queues */ 502 struct sge_txq *txq; /* NIC tx queues */ 503 struct sge_rxq *rxq; /* NIC rx queues */ 504 #ifdef TCP_OFFLOAD 505 struct sge_wrq *ofld_txq; /* TOE tx queues */ 506 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 507 #endif 508 509 uint16_t iq_start; 510 int eq_start; 511 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 512 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 513 }; 514 515 struct rss_header; 516 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 517 struct mbuf *); 518 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 519 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 520 521 struct adapter { 522 SLIST_ENTRY(adapter) link; 523 device_t dev; 524 struct cdev *cdev; 525 526 /* PCIe register resources */ 527 int regs_rid; 528 struct resource *regs_res; 529 int msix_rid; 530 struct resource *msix_res; 531 bus_space_handle_t bh; 532 bus_space_tag_t bt; 533 bus_size_t mmio_len; 534 535 unsigned int pf; 536 unsigned int mbox; 537 538 /* Interrupt information */ 539 int intr_type; 540 int intr_count; 541 struct irq { 542 struct resource *res; 543 int rid; 544 void *tag; 545 } *irq; 546 547 bus_dma_tag_t dmat; /* Parent DMA tag */ 548 549 struct sge sge; 550 551 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 552 struct port_info *port[MAX_NPORTS]; 553 uint8_t chan_map[NCHAN]; 554 uint32_t filter_mode; 555 556 #ifdef TCP_OFFLOAD 557 void *tom_softc; /* (struct tom_data *) */ 558 struct tom_tunables tt; 559 #endif 560 struct l2t_data *l2t; /* L2 table */ 561 struct tid_info tids; 562 563 int open_device_map; 564 #ifdef TCP_OFFLOAD 565 int offload_map; 566 #endif 567 int flags; 568 569 char fw_version[32]; 570 unsigned int cfcsum; 571 struct adapter_params params; 572 struct t4_virt_res vres; 573 574 uint16_t linkcaps; 575 uint16_t niccaps; 576 uint16_t toecaps; 577 uint16_t rdmacaps; 578 uint16_t iscsicaps; 579 uint16_t fcoecaps; 580 581 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 582 583 struct mtx sc_lock; 584 char lockname[16]; 585 586 /* Starving free lists */ 587 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 588 TAILQ_HEAD(, sge_fl) sfl; 589 struct callout sfl_callout; 590 591 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 592 fw_msg_handler_t fw_msg_handler[4]; /* NUM_FW6_TYPES */ 593 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 594 }; 595 596 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 597 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 598 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 599 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 600 601 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 602 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 603 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 604 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 605 606 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 607 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 608 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 609 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 610 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 611 612 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 613 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 614 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 615 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 616 617 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 618 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 619 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 620 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 621 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 622 623 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 624 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 625 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 626 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 627 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 628 629 #define for_each_txq(pi, iter, txq) \ 630 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 631 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 632 #define for_each_rxq(pi, iter, rxq) \ 633 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 634 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 635 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 636 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 637 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 638 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 639 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 640 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 641 642 /* One for errors, one for firmware events */ 643 #define T4_EXTRA_INTR 2 644 645 static inline uint32_t 646 t4_read_reg(struct adapter *sc, uint32_t reg) 647 { 648 649 return bus_space_read_4(sc->bt, sc->bh, reg); 650 } 651 652 static inline void 653 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 654 { 655 656 bus_space_write_4(sc->bt, sc->bh, reg, val); 657 } 658 659 static inline uint64_t 660 t4_read_reg64(struct adapter *sc, uint32_t reg) 661 { 662 663 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 664 } 665 666 static inline void 667 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 668 { 669 670 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 671 } 672 673 static inline void 674 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 675 { 676 677 *val = pci_read_config(sc->dev, reg, 1); 678 } 679 680 static inline void 681 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 682 { 683 684 pci_write_config(sc->dev, reg, val, 1); 685 } 686 687 static inline void 688 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 689 { 690 691 *val = pci_read_config(sc->dev, reg, 2); 692 } 693 694 static inline void 695 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 696 { 697 698 pci_write_config(sc->dev, reg, val, 2); 699 } 700 701 static inline void 702 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 703 { 704 705 *val = pci_read_config(sc->dev, reg, 4); 706 } 707 708 static inline void 709 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 710 { 711 712 pci_write_config(sc->dev, reg, val, 4); 713 } 714 715 static inline struct port_info * 716 adap2pinfo(struct adapter *sc, int idx) 717 { 718 719 return (sc->port[idx]); 720 } 721 722 static inline void 723 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 724 { 725 726 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 727 } 728 729 static inline bool is_10G_port(const struct port_info *pi) 730 { 731 732 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 733 } 734 735 static inline int tx_resume_threshold(struct sge_eq *eq) 736 { 737 738 return (eq->qsize / 4); 739 } 740 741 /* t4_main.c */ 742 void t4_tx_task(void *, int); 743 void t4_tx_callout(void *); 744 int t4_os_find_pci_capability(struct adapter *, int); 745 int t4_os_pci_save_state(struct adapter *); 746 int t4_os_pci_restore_state(struct adapter *); 747 void t4_os_portmod_changed(const struct adapter *, int); 748 void t4_os_link_changed(struct adapter *, int, int); 749 void t4_iterate(void (*)(struct adapter *, void *), void *); 750 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 751 int t4_register_an_handler(struct adapter *, an_handler_t); 752 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 753 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 754 755 /* t4_sge.c */ 756 void t4_sge_modload(void); 757 int t4_sge_init(struct adapter *); 758 int t4_create_dma_tag(struct adapter *); 759 int t4_destroy_dma_tag(struct adapter *); 760 int t4_setup_adapter_queues(struct adapter *); 761 int t4_teardown_adapter_queues(struct adapter *); 762 int t4_setup_port_queues(struct port_info *); 763 int t4_teardown_port_queues(struct port_info *); 764 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 765 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 766 void t4_intr_all(void *); 767 void t4_intr(void *); 768 void t4_intr_err(void *); 769 void t4_intr_evt(void *); 770 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 771 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 772 void t4_update_fl_bufsize(struct ifnet *); 773 int can_resume_tx(struct sge_eq *); 774 775 static inline struct wrqe * 776 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 777 { 778 int len = offsetof(struct wrqe, wr) + wr_len; 779 struct wrqe *wr; 780 781 wr = malloc(len, M_CXGBE, M_NOWAIT); 782 if (__predict_false(wr == NULL)) 783 return (NULL); 784 wr->wr_len = wr_len; 785 wr->wrq = wrq; 786 return (wr); 787 } 788 789 static inline void * 790 wrtod(struct wrqe *wr) 791 { 792 return (&wr->wr[0]); 793 } 794 795 static inline void 796 free_wrqe(struct wrqe *wr) 797 { 798 free(wr, M_CXGBE); 799 } 800 801 static inline void 802 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 803 { 804 struct sge_wrq *wrq = wr->wrq; 805 806 TXQ_LOCK(wrq); 807 t4_wrq_tx_locked(sc, wrq, wr); 808 TXQ_UNLOCK(wrq); 809 } 810 811 #endif 812