1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/types.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/rwlock.h> 43 #include <sys/sx.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <net/ethernet.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_media.h> 55 #include <netinet/in.h> 56 #include <netinet/tcp_lro.h> 57 58 #include "offload.h" 59 #include "t4_ioctl.h" 60 #include "common/t4_msg.h" 61 #include "firmware/t4fw_interface.h" 62 63 #define KTR_CXGBE KTR_SPARE3 64 MALLOC_DECLARE(M_CXGBE); 65 #define CXGBE_UNIMPLEMENTED(s) \ 66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 67 68 #if defined(__i386__) || defined(__amd64__) 69 static __inline void 70 prefetch(void *x) 71 { 72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 73 } 74 #else 75 #define prefetch(x) __builtin_prefetch(x) 76 #endif 77 78 #ifndef SYSCTL_ADD_UQUAD 79 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 80 #define sysctl_handle_64 sysctl_handle_quad 81 #define CTLTYPE_U64 CTLTYPE_QUAD 82 #endif 83 84 struct adapter; 85 typedef struct adapter adapter_t; 86 87 enum { 88 /* 89 * All ingress queues use this entry size. Note that the firmware event 90 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 91 * be at least 64. 92 */ 93 IQ_ESIZE = 64, 94 95 /* Default queue sizes for all kinds of ingress queues */ 96 FW_IQ_QSIZE = 256, 97 RX_IQ_QSIZE = 1024, 98 99 /* All egress queues use this entry size */ 100 EQ_ESIZE = 64, 101 102 /* Default queue sizes for all kinds of egress queues */ 103 CTRL_EQ_QSIZE = 1024, 104 TX_EQ_QSIZE = 1024, 105 106 #if MJUMPAGESIZE != MCLBYTES 107 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 108 #else 109 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 110 #endif 111 CL_METADATA_SIZE = CACHE_LINE_SIZE, 112 113 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 114 TX_SGL_SEGS = 39, 115 TX_SGL_SEGS_TSO = 38, 116 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 117 }; 118 119 enum { 120 /* adapter intr_type */ 121 INTR_INTX = (1 << 0), 122 INTR_MSI = (1 << 1), 123 INTR_MSIX = (1 << 2) 124 }; 125 126 enum { 127 XGMAC_MTU = (1 << 0), 128 XGMAC_PROMISC = (1 << 1), 129 XGMAC_ALLMULTI = (1 << 2), 130 XGMAC_VLANEX = (1 << 3), 131 XGMAC_UCADDR = (1 << 4), 132 XGMAC_MCADDRS = (1 << 5), 133 134 XGMAC_ALL = 0xffff 135 }; 136 137 enum { 138 /* flags understood by begin_synchronized_op */ 139 HOLD_LOCK = (1 << 0), 140 SLEEP_OK = (1 << 1), 141 INTR_OK = (1 << 2), 142 143 /* flags understood by end_synchronized_op */ 144 LOCK_HELD = HOLD_LOCK, 145 }; 146 147 enum { 148 /* adapter flags */ 149 FULL_INIT_DONE = (1 << 0), 150 FW_OK = (1 << 1), 151 CHK_MBOX_ACCESS = (1 << 2), 152 MASTER_PF = (1 << 3), 153 ADAP_SYSCTL_CTX = (1 << 4), 154 /* TOM_INIT_DONE= (1 << 5), No longer used */ 155 BUF_PACKING_OK = (1 << 6), 156 IS_VF = (1 << 7), 157 158 CXGBE_BUSY = (1 << 9), 159 160 /* port flags */ 161 HAS_TRACEQ = (1 << 3), 162 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 163 164 /* VI flags */ 165 DOOMED = (1 << 0), 166 VI_INIT_DONE = (1 << 1), 167 VI_SYSCTL_CTX = (1 << 2), 168 169 /* adapter debug_flags */ 170 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 171 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 172 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 173 }; 174 175 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 176 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 177 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 178 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 179 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 180 181 struct vi_info { 182 device_t dev; 183 struct port_info *pi; 184 185 struct ifnet *ifp; 186 187 unsigned long flags; 188 int if_flags; 189 190 uint16_t *rss, *nm_rss; 191 int smt_idx; /* for convenience */ 192 uint16_t viid; 193 int16_t xact_addr_filt;/* index of exact MAC address filter */ 194 uint16_t rss_size; /* size of VI's RSS table slice */ 195 uint16_t rss_base; /* start of VI's RSS table slice */ 196 197 int nintr; 198 int first_intr; 199 200 /* These need to be int as they are used in sysctl */ 201 int ntxq; /* # of tx queues */ 202 int first_txq; /* index of first tx queue */ 203 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 204 int nrxq; /* # of rx queues */ 205 int first_rxq; /* index of first rx queue */ 206 int nofldtxq; /* # of offload tx queues */ 207 int first_ofld_txq; /* index of first offload tx queue */ 208 int nofldrxq; /* # of offload rx queues */ 209 int first_ofld_rxq; /* index of first offload rx queue */ 210 int nnmtxq; 211 int first_nm_txq; 212 int nnmrxq; 213 int first_nm_rxq; 214 int tmr_idx; 215 int ofld_tmr_idx; 216 int pktc_idx; 217 int ofld_pktc_idx; 218 int qsize_rxq; 219 int qsize_txq; 220 221 struct timeval last_refreshed; 222 struct fw_vi_stats_vf stats; 223 224 struct callout tick; 225 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 226 227 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 228 }; 229 230 struct tx_ch_rl_params { 231 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 232 uint32_t maxrate; 233 }; 234 235 enum { 236 CLRL_USER = (1 << 0), /* allocated manually. */ 237 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 238 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 239 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 240 }; 241 242 struct tx_cl_rl_params { 243 int refcount; 244 uint8_t flags; 245 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 246 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 247 enum fw_sched_params_mode mode; /* aggr or per-flow */ 248 uint32_t maxrate; 249 uint16_t pktsize; 250 uint16_t burstsize; 251 }; 252 253 /* Tx scheduler parameters for a channel/port */ 254 struct tx_sched_params { 255 /* Channel Rate Limiter */ 256 struct tx_ch_rl_params ch_rl; 257 258 /* Class WRR */ 259 /* XXX */ 260 261 /* Class Rate Limiter (including the default pktsize and burstsize). */ 262 int pktsize; 263 int burstsize; 264 struct tx_cl_rl_params cl_rl[]; 265 }; 266 267 struct port_info { 268 device_t dev; 269 struct adapter *adapter; 270 271 struct vi_info *vi; 272 int nvi; 273 int up_vis; 274 int uld_vis; 275 276 struct tx_sched_params *sched_params; 277 278 struct mtx pi_lock; 279 char lockname[16]; 280 unsigned long flags; 281 282 uint8_t lport; /* associated offload logical port */ 283 int8_t mdio_addr; 284 uint8_t port_type; 285 uint8_t mod_type; 286 uint8_t port_id; 287 uint8_t tx_chan; 288 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 289 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 290 291 struct link_config link_cfg; 292 struct ifmedia media; 293 294 struct timeval last_refreshed; 295 struct port_stats stats; 296 u_int tnl_cong_drops; 297 u_int tx_parse_error; 298 u_long tx_tls_records; 299 u_long tx_tls_octets; 300 u_long rx_tls_records; 301 u_long rx_tls_octets; 302 303 struct callout tick; 304 }; 305 306 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 307 308 /* Where the cluster came from, how it has been carved up. */ 309 struct cluster_layout { 310 int8_t zidx; 311 int8_t hwidx; 312 uint16_t region1; /* mbufs laid out within this region */ 313 /* region2 is the DMA region */ 314 uint16_t region3; /* cluster_metadata within this region */ 315 }; 316 317 struct cluster_metadata { 318 u_int refcount; 319 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 320 }; 321 322 struct fl_sdesc { 323 caddr_t cl; 324 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 325 struct cluster_layout cll; 326 }; 327 328 struct tx_desc { 329 __be64 flit[8]; 330 }; 331 332 struct tx_sdesc { 333 struct mbuf *m; /* m_nextpkt linked chain of frames */ 334 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 335 }; 336 337 338 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 339 struct iq_desc { 340 struct rss_header rss; 341 uint8_t cpl[IQ_PAD]; 342 struct rsp_ctrl rsp; 343 }; 344 #undef IQ_PAD 345 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 346 347 enum { 348 /* iq flags */ 349 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 350 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 351 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 352 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 353 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 354 355 /* iq state */ 356 IQS_DISABLED = 0, 357 IQS_BUSY = 1, 358 IQS_IDLE = 2, 359 360 /* netmap related flags */ 361 NM_OFF = 0, 362 NM_ON = 1, 363 NM_BUSY = 2, 364 }; 365 366 enum { 367 CPL_COOKIE_RESERVED = 0, 368 CPL_COOKIE_FILTER, 369 CPL_COOKIE_DDP0, 370 CPL_COOKIE_DDP1, 371 CPL_COOKIE_TOM, 372 CPL_COOKIE_HASHFILTER, 373 CPL_COOKIE_ETHOFLD, 374 CPL_COOKIE_AVAILABLE3, 375 376 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 377 }; 378 379 struct sge_iq; 380 struct rss_header; 381 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 382 struct mbuf *); 383 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 384 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 385 386 /* 387 * Ingress Queue: T4 is producer, driver is consumer. 388 */ 389 struct sge_iq { 390 uint32_t flags; 391 volatile int state; 392 struct adapter *adapter; 393 struct iq_desc *desc; /* KVA of descriptor ring */ 394 int8_t intr_pktc_idx; /* packet count threshold index */ 395 uint8_t gen; /* generation bit */ 396 uint8_t intr_params; /* interrupt holdoff parameters */ 397 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 398 uint16_t qsize; /* size (# of entries) of the queue */ 399 uint16_t sidx; /* index of the entry with the status page */ 400 uint16_t cidx; /* consumer index */ 401 uint16_t cntxt_id; /* SGE context id for the iq */ 402 uint16_t abs_id; /* absolute SGE id for the iq */ 403 404 STAILQ_ENTRY(sge_iq) link; 405 406 bus_dma_tag_t desc_tag; 407 bus_dmamap_t desc_map; 408 bus_addr_t ba; /* bus address of descriptor ring */ 409 }; 410 411 enum { 412 EQ_CTRL = 1, 413 EQ_ETH = 2, 414 EQ_OFLD = 3, 415 416 /* eq flags */ 417 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 418 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 419 EQ_ENABLED = (1 << 3), /* open for business */ 420 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 421 }; 422 423 /* Listed in order of preference. Update t4_sysctls too if you change these */ 424 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 425 426 /* 427 * Egress Queue: driver is producer, T4 is consumer. 428 * 429 * Note: A free list is an egress queue (driver produces the buffers and T4 430 * consumes them) but it's special enough to have its own struct (see sge_fl). 431 */ 432 struct sge_eq { 433 unsigned int flags; /* MUST be first */ 434 unsigned int cntxt_id; /* SGE context id for the eq */ 435 unsigned int abs_id; /* absolute SGE id for the eq */ 436 struct mtx eq_lock; 437 438 struct tx_desc *desc; /* KVA of descriptor ring */ 439 uint8_t doorbells; 440 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 441 u_int udb_qid; /* relative qid within the doorbell page */ 442 uint16_t sidx; /* index of the entry with the status page */ 443 uint16_t cidx; /* consumer idx (desc idx) */ 444 uint16_t pidx; /* producer idx (desc idx) */ 445 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 446 uint16_t dbidx; /* pidx of the most recent doorbell */ 447 uint16_t iqid; /* iq that gets egr_update for the eq */ 448 uint8_t tx_chan; /* tx channel used by the eq */ 449 volatile u_int equiq; /* EQUIQ outstanding */ 450 451 bus_dma_tag_t desc_tag; 452 bus_dmamap_t desc_map; 453 bus_addr_t ba; /* bus address of descriptor ring */ 454 char lockname[16]; 455 }; 456 457 struct sw_zone_info { 458 uma_zone_t zone; /* zone that this cluster comes from */ 459 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 460 int type; /* EXT_xxx type of the cluster */ 461 int8_t head_hwidx; 462 int8_t tail_hwidx; 463 }; 464 465 struct hw_buf_info { 466 int8_t zidx; /* backpointer to zone; -ve means unused */ 467 int8_t next; /* next hwidx for this zone; -1 means no more */ 468 int size; 469 }; 470 471 enum { 472 NUM_MEMWIN = 3, 473 474 MEMWIN0_APERTURE = 2048, 475 MEMWIN0_BASE = 0x1b800, 476 477 MEMWIN1_APERTURE = 32768, 478 MEMWIN1_BASE = 0x28000, 479 480 MEMWIN2_APERTURE_T4 = 65536, 481 MEMWIN2_BASE_T4 = 0x30000, 482 483 MEMWIN2_APERTURE_T5 = 128 * 1024, 484 MEMWIN2_BASE_T5 = 0x60000, 485 }; 486 487 struct memwin { 488 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 489 uint32_t mw_base; /* constant after setup_memwin */ 490 uint32_t mw_aperture; /* ditto */ 491 uint32_t mw_curpos; /* protected by mw_lock */ 492 }; 493 494 enum { 495 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 496 FL_DOOMED = (1 << 1), /* about to be destroyed */ 497 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 498 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 499 }; 500 501 #define FL_RUNNING_LOW(fl) \ 502 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 503 #define FL_NOT_RUNNING_LOW(fl) \ 504 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 505 506 struct sge_fl { 507 struct mtx fl_lock; 508 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 509 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 510 struct cluster_layout cll_def; /* default refill zone, layout */ 511 uint16_t lowat; /* # of buffers <= this means fl needs help */ 512 int flags; 513 uint16_t buf_boundary; 514 515 /* The 16b idx all deal with hw descriptors */ 516 uint16_t dbidx; /* hw pidx after last doorbell */ 517 uint16_t sidx; /* index of status page */ 518 volatile uint16_t hw_cidx; 519 520 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 521 uint32_t cidx; /* consumer index */ 522 uint32_t pidx; /* producer index */ 523 524 uint32_t dbval; 525 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 526 volatile uint32_t *udb; 527 528 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 529 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 530 uint64_t cl_allocated; /* # of clusters allocated */ 531 uint64_t cl_recycled; /* # of clusters recycled */ 532 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 533 534 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 535 struct mbuf *m0; 536 struct mbuf **pnext; 537 u_int remaining; 538 539 uint16_t qsize; /* # of hw descriptors (status page included) */ 540 uint16_t cntxt_id; /* SGE context id for the freelist */ 541 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 542 bus_dma_tag_t desc_tag; 543 bus_dmamap_t desc_map; 544 char lockname[16]; 545 bus_addr_t ba; /* bus address of descriptor ring */ 546 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 547 }; 548 549 struct mp_ring; 550 551 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 552 struct sge_txq { 553 struct sge_eq eq; /* MUST be first */ 554 555 struct ifnet *ifp; /* the interface this txq belongs to */ 556 struct mp_ring *r; /* tx software ring */ 557 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 558 struct sglist *gl; 559 __be32 cpl_ctrl0; /* for convenience */ 560 int tc_idx; /* traffic class */ 561 562 struct task tx_reclaim_task; 563 /* stats for common events first */ 564 565 uint64_t txcsum; /* # of times hardware assisted with checksum */ 566 uint64_t tso_wrs; /* # of TSO work requests */ 567 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 568 uint64_t imm_wrs; /* # of work requests with immediate data */ 569 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 570 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 571 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 572 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 573 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 574 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 575 576 /* stats for not-that-common events */ 577 } __aligned(CACHE_LINE_SIZE); 578 579 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 580 struct sge_rxq { 581 struct sge_iq iq; /* MUST be first */ 582 struct sge_fl fl; /* MUST follow iq */ 583 584 struct ifnet *ifp; /* the interface this rxq belongs to */ 585 #if defined(INET) || defined(INET6) 586 struct lro_ctrl lro; /* LRO state */ 587 #endif 588 589 /* stats for common events first */ 590 591 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 592 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 593 594 /* stats for not-that-common events */ 595 596 } __aligned(CACHE_LINE_SIZE); 597 598 static inline struct sge_rxq * 599 iq_to_rxq(struct sge_iq *iq) 600 { 601 602 return (__containerof(iq, struct sge_rxq, iq)); 603 } 604 605 606 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 607 struct sge_ofld_rxq { 608 struct sge_iq iq; /* MUST be first */ 609 struct sge_fl fl; /* MUST follow iq */ 610 } __aligned(CACHE_LINE_SIZE); 611 612 static inline struct sge_ofld_rxq * 613 iq_to_ofld_rxq(struct sge_iq *iq) 614 { 615 616 return (__containerof(iq, struct sge_ofld_rxq, iq)); 617 } 618 619 struct wrqe { 620 STAILQ_ENTRY(wrqe) link; 621 struct sge_wrq *wrq; 622 int wr_len; 623 char wr[] __aligned(16); 624 }; 625 626 struct wrq_cookie { 627 TAILQ_ENTRY(wrq_cookie) link; 628 int ndesc; 629 int pidx; 630 }; 631 632 /* 633 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 634 * and offload tx queues are of this type. 635 */ 636 struct sge_wrq { 637 struct sge_eq eq; /* MUST be first */ 638 639 struct adapter *adapter; 640 struct task wrq_tx_task; 641 642 /* Tx desc reserved but WR not "committed" yet. */ 643 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 644 645 /* List of WRs ready to go out as soon as descriptors are available. */ 646 STAILQ_HEAD(, wrqe) wr_list; 647 u_int nwr_pending; 648 u_int ndesc_needed; 649 650 /* stats for common events first */ 651 652 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 653 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 654 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 655 656 /* stats for not-that-common events */ 657 658 /* 659 * Scratch space for work requests that wrap around after reaching the 660 * status page, and some information about the last WR that used it. 661 */ 662 uint16_t ss_pidx; 663 uint16_t ss_len; 664 uint8_t ss[SGE_MAX_WR_LEN]; 665 666 } __aligned(CACHE_LINE_SIZE); 667 668 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 669 struct sge_nm_rxq { 670 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 671 struct vi_info *vi; 672 673 struct iq_desc *iq_desc; 674 uint16_t iq_abs_id; 675 uint16_t iq_cntxt_id; 676 uint16_t iq_cidx; 677 uint16_t iq_sidx; 678 uint8_t iq_gen; 679 680 __be64 *fl_desc; 681 uint16_t fl_cntxt_id; 682 uint32_t fl_cidx; 683 uint32_t fl_pidx; 684 uint32_t fl_sidx; 685 uint32_t fl_db_val; 686 u_int fl_hwidx:4; 687 688 u_int fl_db_saved; 689 u_int nid; /* netmap ring # for this queue */ 690 691 /* infrequently used items after this */ 692 693 bus_dma_tag_t iq_desc_tag; 694 bus_dmamap_t iq_desc_map; 695 bus_addr_t iq_ba; 696 int intr_idx; 697 698 bus_dma_tag_t fl_desc_tag; 699 bus_dmamap_t fl_desc_map; 700 bus_addr_t fl_ba; 701 } __aligned(CACHE_LINE_SIZE); 702 703 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 704 struct sge_nm_txq { 705 struct tx_desc *desc; 706 uint16_t cidx; 707 uint16_t pidx; 708 uint16_t sidx; 709 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 710 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 711 uint16_t dbidx; /* pidx of the most recent doorbell */ 712 uint8_t doorbells; 713 volatile uint32_t *udb; 714 u_int udb_qid; 715 u_int cntxt_id; 716 __be32 cpl_ctrl0; /* for convenience */ 717 u_int nid; /* netmap ring # for this queue */ 718 719 /* infrequently used items after this */ 720 721 bus_dma_tag_t desc_tag; 722 bus_dmamap_t desc_map; 723 bus_addr_t ba; 724 int iqidx; 725 } __aligned(CACHE_LINE_SIZE); 726 727 struct sge { 728 int nrxq; /* total # of Ethernet rx queues */ 729 int ntxq; /* total # of Ethernet tx queues */ 730 int nofldrxq; /* total # of TOE rx queues */ 731 int nofldtxq; /* total # of TOE tx queues */ 732 int nnmrxq; /* total # of netmap rx queues */ 733 int nnmtxq; /* total # of netmap tx queues */ 734 int niq; /* total # of ingress queues */ 735 int neq; /* total # of egress queues */ 736 737 struct sge_iq fwq; /* Firmware event queue */ 738 struct sge_wrq *ctrlq; /* Control queues */ 739 struct sge_txq *txq; /* NIC tx queues */ 740 struct sge_rxq *rxq; /* NIC rx queues */ 741 struct sge_wrq *ofld_txq; /* TOE tx queues */ 742 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 743 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 744 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 745 746 uint16_t iq_start; /* first cntxt_id */ 747 uint16_t iq_base; /* first abs_id */ 748 int eq_start; /* first cntxt_id */ 749 int eq_base; /* first abs_id */ 750 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 751 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 752 753 int8_t safe_hwidx1; /* may not have room for metadata */ 754 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 755 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 756 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 757 }; 758 759 struct devnames { 760 const char *nexus_name; 761 const char *ifnet_name; 762 const char *vi_ifnet_name; 763 const char *pf03_drv_name; 764 const char *vf_nexus_name; 765 const char *vf_ifnet_name; 766 }; 767 768 struct adapter { 769 SLIST_ENTRY(adapter) link; 770 device_t dev; 771 struct cdev *cdev; 772 const struct devnames *names; 773 774 /* PCIe register resources */ 775 int regs_rid; 776 struct resource *regs_res; 777 int msix_rid; 778 struct resource *msix_res; 779 bus_space_handle_t bh; 780 bus_space_tag_t bt; 781 bus_size_t mmio_len; 782 int udbs_rid; 783 struct resource *udbs_res; 784 volatile uint8_t *udbs_base; 785 786 unsigned int pf; 787 unsigned int mbox; 788 unsigned int vpd_busy; 789 unsigned int vpd_flag; 790 791 /* Interrupt information */ 792 int intr_type; 793 int intr_count; 794 struct irq { 795 struct resource *res; 796 int rid; 797 void *tag; 798 struct sge_rxq *rxq; 799 struct sge_nm_rxq *nm_rxq; 800 } __aligned(CACHE_LINE_SIZE) *irq; 801 int sge_gts_reg; 802 int sge_kdoorbell_reg; 803 804 bus_dma_tag_t dmat; /* Parent DMA tag */ 805 806 struct sge sge; 807 int lro_timeout; 808 int sc_do_rxcopy; 809 810 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 811 struct port_info *port[MAX_NPORTS]; 812 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 813 814 void *tom_softc; /* (struct tom_data *) */ 815 struct tom_tunables tt; 816 struct t4_offload_policy *policy; 817 struct rwlock policy_lock; 818 819 void *iwarp_softc; /* (struct c4iw_dev *) */ 820 struct iw_tunables iwt; 821 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 822 void *ccr_softc; /* (struct ccr_softc *) */ 823 struct l2t_data *l2t; /* L2 table */ 824 struct smt_data *smt; /* Source MAC Table */ 825 struct tid_info tids; 826 827 uint8_t doorbells; 828 int offload_map; /* ports with IFCAP_TOE enabled */ 829 int active_ulds; /* ULDs activated on this adapter */ 830 int flags; 831 int debug_flags; 832 833 char ifp_lockname[16]; 834 struct mtx ifp_lock; 835 struct ifnet *ifp; /* tracer ifp */ 836 struct ifmedia media; 837 int traceq; /* iq used by all tracers, -1 if none */ 838 int tracer_valid; /* bitmap of valid tracers */ 839 int tracer_enabled; /* bitmap of enabled tracers */ 840 841 char fw_version[16]; 842 char tp_version[16]; 843 char er_version[16]; 844 char bs_version[16]; 845 char cfg_file[32]; 846 u_int cfcsum; 847 struct adapter_params params; 848 const struct chip_params *chip_params; 849 struct t4_virt_res vres; 850 851 uint16_t nbmcaps; 852 uint16_t linkcaps; 853 uint16_t switchcaps; 854 uint16_t niccaps; 855 uint16_t toecaps; 856 uint16_t rdmacaps; 857 uint16_t cryptocaps; 858 uint16_t iscsicaps; 859 uint16_t fcoecaps; 860 861 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 862 863 struct mtx sc_lock; 864 char lockname[16]; 865 866 /* Starving free lists */ 867 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 868 TAILQ_HEAD(, sge_fl) sfl; 869 struct callout sfl_callout; 870 871 struct mtx reg_lock; /* for indirect register access */ 872 873 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 874 875 struct mtx tc_lock; 876 struct task tc_task; 877 878 const char *last_op; 879 const void *last_op_thr; 880 int last_op_flags; 881 }; 882 883 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 884 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 885 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 886 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 887 888 #define ASSERT_SYNCHRONIZED_OP(sc) \ 889 KASSERT(IS_BUSY(sc) && \ 890 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 891 ("%s: operation not synchronized.", __func__)) 892 893 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 894 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 895 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 896 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 897 898 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 899 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 900 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 901 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 902 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 903 904 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 905 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 906 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 907 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 908 909 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 910 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 911 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 912 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 913 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 914 915 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 916 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 917 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 918 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 919 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 920 921 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 922 do { \ 923 if (sc->debug_flags & DF_DUMP_MBOX) { \ 924 log(LOG_NOTICE, \ 925 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 926 "%016llx %016llx %016llx %016llx\n", \ 927 device_get_nameunit(sc->dev), mbox, \ 928 (unsigned long long)t4_read_reg64(sc, data_reg), \ 929 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 930 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 931 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 932 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 933 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 934 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 935 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 936 } \ 937 } while (0) 938 939 #define for_each_txq(vi, iter, q) \ 940 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 941 iter < vi->ntxq; ++iter, ++q) 942 #define for_each_rxq(vi, iter, q) \ 943 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 944 iter < vi->nrxq; ++iter, ++q) 945 #define for_each_ofld_txq(vi, iter, q) \ 946 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 947 iter < vi->nofldtxq; ++iter, ++q) 948 #define for_each_ofld_rxq(vi, iter, q) \ 949 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 950 iter < vi->nofldrxq; ++iter, ++q) 951 #define for_each_nm_txq(vi, iter, q) \ 952 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 953 iter < vi->nnmtxq; ++iter, ++q) 954 #define for_each_nm_rxq(vi, iter, q) \ 955 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 956 iter < vi->nnmrxq; ++iter, ++q) 957 #define for_each_vi(_pi, _iter, _vi) \ 958 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 959 ++(_iter), ++(_vi)) 960 961 #define IDXINCR(idx, incr, wrap) do { \ 962 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 963 } while (0) 964 #define IDXDIFF(head, tail, wrap) \ 965 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 966 967 /* One for errors, one for firmware events */ 968 #define T4_EXTRA_INTR 2 969 970 /* One for firmware events */ 971 #define T4VF_EXTRA_INTR 1 972 973 static inline int 974 forwarding_intr_to_fwq(struct adapter *sc) 975 { 976 977 return (sc->intr_count == 1); 978 } 979 980 static inline uint32_t 981 t4_read_reg(struct adapter *sc, uint32_t reg) 982 { 983 984 return bus_space_read_4(sc->bt, sc->bh, reg); 985 } 986 987 static inline void 988 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 989 { 990 991 bus_space_write_4(sc->bt, sc->bh, reg, val); 992 } 993 994 static inline uint64_t 995 t4_read_reg64(struct adapter *sc, uint32_t reg) 996 { 997 998 #ifdef __LP64__ 999 return bus_space_read_8(sc->bt, sc->bh, reg); 1000 #else 1001 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1002 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1003 1004 #endif 1005 } 1006 1007 static inline void 1008 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1009 { 1010 1011 #ifdef __LP64__ 1012 bus_space_write_8(sc->bt, sc->bh, reg, val); 1013 #else 1014 bus_space_write_4(sc->bt, sc->bh, reg, val); 1015 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1016 #endif 1017 } 1018 1019 static inline void 1020 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1021 { 1022 1023 *val = pci_read_config(sc->dev, reg, 1); 1024 } 1025 1026 static inline void 1027 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1028 { 1029 1030 pci_write_config(sc->dev, reg, val, 1); 1031 } 1032 1033 static inline void 1034 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1035 { 1036 1037 *val = pci_read_config(sc->dev, reg, 2); 1038 } 1039 1040 static inline void 1041 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1042 { 1043 1044 pci_write_config(sc->dev, reg, val, 2); 1045 } 1046 1047 static inline void 1048 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1049 { 1050 1051 *val = pci_read_config(sc->dev, reg, 4); 1052 } 1053 1054 static inline void 1055 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1056 { 1057 1058 pci_write_config(sc->dev, reg, val, 4); 1059 } 1060 1061 static inline struct port_info * 1062 adap2pinfo(struct adapter *sc, int idx) 1063 { 1064 1065 return (sc->port[idx]); 1066 } 1067 1068 static inline void 1069 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1070 { 1071 1072 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1073 } 1074 1075 static inline int 1076 tx_resume_threshold(struct sge_eq *eq) 1077 { 1078 1079 /* not quite the same as qsize / 4, but this will do. */ 1080 return (eq->sidx / 4); 1081 } 1082 1083 static inline int 1084 t4_use_ldst(struct adapter *sc) 1085 { 1086 1087 #ifdef notyet 1088 return (sc->flags & FW_OK || !sc->use_bd); 1089 #else 1090 return (0); 1091 #endif 1092 } 1093 1094 /* t4_main.c */ 1095 extern int t4_ntxq; 1096 extern int t4_nrxq; 1097 extern int t4_intr_types; 1098 extern int t4_tmr_idx; 1099 extern int t4_pktc_idx; 1100 extern unsigned int t4_qsize_rxq; 1101 extern unsigned int t4_qsize_txq; 1102 extern device_method_t cxgbe_methods[]; 1103 1104 int t4_os_find_pci_capability(struct adapter *, int); 1105 int t4_os_pci_save_state(struct adapter *); 1106 int t4_os_pci_restore_state(struct adapter *); 1107 void t4_os_portmod_changed(struct port_info *); 1108 void t4_os_link_changed(struct port_info *); 1109 void t4_iterate(void (*)(struct adapter *, void *), void *); 1110 void t4_init_devnames(struct adapter *); 1111 void t4_add_adapter(struct adapter *); 1112 void t4_aes_getdeckey(void *, const void *, unsigned int); 1113 int t4_detach_common(device_t); 1114 int t4_map_bars_0_and_4(struct adapter *); 1115 int t4_map_bar_2(struct adapter *); 1116 int t4_setup_intr_handlers(struct adapter *); 1117 void t4_sysctls(struct adapter *); 1118 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1119 void doom_vi(struct adapter *, struct vi_info *); 1120 void end_synchronized_op(struct adapter *, int); 1121 int update_mac_settings(struct ifnet *, int); 1122 int adapter_full_init(struct adapter *); 1123 int adapter_full_uninit(struct adapter *); 1124 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1125 int vi_full_init(struct vi_info *); 1126 int vi_full_uninit(struct vi_info *); 1127 void vi_sysctls(struct vi_info *); 1128 void vi_tick(void *); 1129 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1130 int alloc_atid_tab(struct tid_info *, int); 1131 void free_atid_tab(struct tid_info *); 1132 int alloc_atid(struct adapter *, void *); 1133 void *lookup_atid(struct adapter *, int); 1134 void free_atid(struct adapter *, int); 1135 void release_tid(struct adapter *, int, struct sge_wrq *); 1136 int cxgbe_media_change(struct ifnet *); 1137 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1138 1139 #ifdef DEV_NETMAP 1140 /* t4_netmap.c */ 1141 struct sge_nm_rxq; 1142 void cxgbe_nm_attach(struct vi_info *); 1143 void cxgbe_nm_detach(struct vi_info *); 1144 void service_nm_rxq(struct sge_nm_rxq *); 1145 #endif 1146 1147 /* t4_sge.c */ 1148 void t4_sge_modload(void); 1149 void t4_sge_modunload(void); 1150 uint64_t t4_sge_extfree_refs(void); 1151 void t4_tweak_chip_settings(struct adapter *); 1152 int t4_read_chip_settings(struct adapter *); 1153 int t4_create_dma_tag(struct adapter *); 1154 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1155 struct sysctl_oid_list *); 1156 int t4_destroy_dma_tag(struct adapter *); 1157 int t4_setup_adapter_queues(struct adapter *); 1158 int t4_teardown_adapter_queues(struct adapter *); 1159 int t4_setup_vi_queues(struct vi_info *); 1160 int t4_teardown_vi_queues(struct vi_info *); 1161 void t4_intr_all(void *); 1162 void t4_intr(void *); 1163 #ifdef DEV_NETMAP 1164 void t4_nm_intr(void *); 1165 void t4_vi_intr(void *); 1166 #endif 1167 void t4_intr_err(void *); 1168 void t4_intr_evt(void *); 1169 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1170 void t4_update_fl_bufsize(struct ifnet *); 1171 int parse_pkt(struct adapter *, struct mbuf **); 1172 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1173 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1174 int tnl_cong(struct port_info *, int); 1175 void t4_register_an_handler(an_handler_t); 1176 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1177 void t4_register_cpl_handler(int, cpl_handler_t); 1178 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1179 #ifdef RATELIMIT 1180 int ethofld_transmit(struct ifnet *, struct mbuf *); 1181 void send_etid_flush_wr(struct cxgbe_snd_tag *); 1182 #endif 1183 1184 /* t4_tracer.c */ 1185 struct t4_tracer; 1186 void t4_tracer_modload(void); 1187 void t4_tracer_modunload(void); 1188 void t4_tracer_port_detach(struct adapter *); 1189 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1190 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1191 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1192 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1193 1194 /* t4_sched.c */ 1195 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1196 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1197 int t4_init_tx_sched(struct adapter *); 1198 int t4_free_tx_sched(struct adapter *); 1199 void t4_update_tx_sched(struct adapter *); 1200 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1201 void t4_release_cl_rl(struct adapter *, int, int); 1202 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1203 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1204 #ifdef RATELIMIT 1205 void t4_init_etid_table(struct adapter *); 1206 void t4_free_etid_table(struct adapter *); 1207 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int); 1208 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1209 struct m_snd_tag **); 1210 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1211 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1212 void cxgbe_snd_tag_free(struct m_snd_tag *); 1213 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *); 1214 #endif 1215 1216 /* t4_filter.c */ 1217 int get_filter_mode(struct adapter *, uint32_t *); 1218 int set_filter_mode(struct adapter *, uint32_t); 1219 int get_filter(struct adapter *, struct t4_filter *); 1220 int set_filter(struct adapter *, struct t4_filter *); 1221 int del_filter(struct adapter *, struct t4_filter *); 1222 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1223 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1224 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1225 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1226 void free_hftid_hash(struct tid_info *); 1227 1228 static inline struct wrqe * 1229 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1230 { 1231 int len = offsetof(struct wrqe, wr) + wr_len; 1232 struct wrqe *wr; 1233 1234 wr = malloc(len, M_CXGBE, M_NOWAIT); 1235 if (__predict_false(wr == NULL)) 1236 return (NULL); 1237 wr->wr_len = wr_len; 1238 wr->wrq = wrq; 1239 return (wr); 1240 } 1241 1242 static inline void * 1243 wrtod(struct wrqe *wr) 1244 { 1245 return (&wr->wr[0]); 1246 } 1247 1248 static inline void 1249 free_wrqe(struct wrqe *wr) 1250 { 1251 free(wr, M_CXGBE); 1252 } 1253 1254 static inline void 1255 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1256 { 1257 struct sge_wrq *wrq = wr->wrq; 1258 1259 TXQ_LOCK(wrq); 1260 t4_wrq_tx_locked(sc, wrq, wr); 1261 TXQ_UNLOCK(wrq); 1262 } 1263 1264 static inline int 1265 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1266 int len) 1267 { 1268 1269 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1270 } 1271 1272 static inline int 1273 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1274 const uint32_t *val, int len) 1275 { 1276 1277 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1278 } 1279 #endif 1280