1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 #define KTR_CXGBE KTR_SPARE3 61 MALLOC_DECLARE(M_CXGBE); 62 #define CXGBE_UNIMPLEMENTED(s) \ 63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 64 65 #if defined(__i386__) || defined(__amd64__) 66 static __inline void 67 prefetch(void *x) 68 { 69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 70 } 71 #else 72 #define prefetch(x) 73 #endif 74 75 #ifndef SYSCTL_ADD_UQUAD 76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 77 #define sysctl_handle_64 sysctl_handle_quad 78 #define CTLTYPE_U64 CTLTYPE_QUAD 79 #endif 80 81 #if (__FreeBSD_version >= 900030) || \ 82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 83 #define SBUF_DRAIN 1 84 #endif 85 86 #ifdef __amd64__ 87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 KASSERT(tag == X86_BUS_SPACE_MEM, 93 ("%s: can only handle mem space", __func__)); 94 95 return (*(volatile uint64_t *)(handle + offset)); 96 } 97 98 static __inline void 99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 100 bus_size_t offset, uint64_t value) 101 { 102 KASSERT(tag == X86_BUS_SPACE_MEM, 103 ("%s: can only handle mem space", __func__)); 104 105 *(volatile uint64_t *)(bsh + offset) = value; 106 } 107 #else 108 static __inline uint64_t 109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 110 bus_size_t offset) 111 { 112 return (uint64_t)bus_space_read_4(tag, handle, offset) + 113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 114 } 115 116 static __inline void 117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 118 bus_size_t offset, uint64_t value) 119 { 120 bus_space_write_4(tag, bsh, offset, value); 121 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 122 } 123 #endif 124 125 struct adapter; 126 typedef struct adapter adapter_t; 127 128 enum { 129 /* 130 * All ingress queues use this entry size. Note that the firmware event 131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 132 * be at least 64. 133 */ 134 IQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of ingress queues */ 137 FW_IQ_QSIZE = 256, 138 RX_IQ_QSIZE = 1024, 139 140 /* All egress queues use this entry size */ 141 EQ_ESIZE = 64, 142 143 /* Default queue sizes for all kinds of egress queues */ 144 CTRL_EQ_QSIZE = 128, 145 TX_EQ_QSIZE = 1024, 146 147 #if MJUMPAGESIZE != MCLBYTES 148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 149 #else 150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 151 #endif 152 CL_METADATA_SIZE = CACHE_LINE_SIZE, 153 154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 155 TX_SGL_SEGS = 39, 156 TX_SGL_SEGS_TSO = 38, 157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 158 }; 159 160 enum { 161 /* adapter intr_type */ 162 INTR_INTX = (1 << 0), 163 INTR_MSI = (1 << 1), 164 INTR_MSIX = (1 << 2) 165 }; 166 167 enum { 168 XGMAC_MTU = (1 << 0), 169 XGMAC_PROMISC = (1 << 1), 170 XGMAC_ALLMULTI = (1 << 2), 171 XGMAC_VLANEX = (1 << 3), 172 XGMAC_UCADDR = (1 << 4), 173 XGMAC_MCADDRS = (1 << 5), 174 175 XGMAC_ALL = 0xffff 176 }; 177 178 enum { 179 /* flags understood by begin_synchronized_op */ 180 HOLD_LOCK = (1 << 0), 181 SLEEP_OK = (1 << 1), 182 INTR_OK = (1 << 2), 183 184 /* flags understood by end_synchronized_op */ 185 LOCK_HELD = HOLD_LOCK, 186 }; 187 188 enum { 189 /* adapter flags */ 190 FULL_INIT_DONE = (1 << 0), 191 FW_OK = (1 << 1), 192 /* INTR_DIRECT = (1 << 2), No longer used. */ 193 MASTER_PF = (1 << 3), 194 ADAP_SYSCTL_CTX = (1 << 4), 195 /* TOM_INIT_DONE= (1 << 5), No longer used */ 196 BUF_PACKING_OK = (1 << 6), 197 198 CXGBE_BUSY = (1 << 9), 199 200 /* port flags */ 201 DOOMED = (1 << 0), 202 PORT_INIT_DONE = (1 << 1), 203 PORT_SYSCTL_CTX = (1 << 2), 204 HAS_TRACEQ = (1 << 3), 205 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 206 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 207 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */ 208 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ), 209 210 /* adapter debug_flags */ 211 DF_DUMP_MBOX = (1 << 0), 212 }; 213 214 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 215 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 216 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 217 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 218 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 219 220 struct port_info { 221 device_t dev; 222 struct adapter *adapter; 223 224 struct ifnet *ifp; 225 struct ifmedia media; 226 227 struct mtx pi_lock; 228 char lockname[16]; 229 unsigned long flags; 230 int if_flags; 231 232 uint16_t *rss; 233 uint16_t viid; 234 int16_t xact_addr_filt;/* index of exact MAC address filter */ 235 uint16_t rss_size; /* size of VI's RSS table slice */ 236 uint8_t lport; /* associated offload logical port */ 237 int8_t mdio_addr; 238 uint8_t port_type; 239 uint8_t mod_type; 240 uint8_t port_id; 241 uint8_t tx_chan; 242 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 243 244 /* These need to be int as they are used in sysctl */ 245 int ntxq; /* # of tx queues */ 246 int first_txq; /* index of first tx queue */ 247 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 248 int nrxq; /* # of rx queues */ 249 int first_rxq; /* index of first rx queue */ 250 #ifdef TCP_OFFLOAD 251 int nofldtxq; /* # of offload tx queues */ 252 int first_ofld_txq; /* index of first offload tx queue */ 253 int nofldrxq; /* # of offload rx queues */ 254 int first_ofld_rxq; /* index of first offload rx queue */ 255 #endif 256 #ifdef DEV_NETMAP 257 int nnmtxq; /* # of netmap tx queues */ 258 int first_nm_txq; /* index of first netmap tx queue */ 259 int nnmrxq; /* # of netmap rx queues */ 260 int first_nm_rxq; /* index of first netmap rx queue */ 261 262 struct ifnet *nm_ifp; 263 struct ifmedia nm_media; 264 int nmif_flags; 265 uint16_t nm_viid; 266 int16_t nm_xact_addr_filt; 267 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */ 268 #endif 269 int tmr_idx; 270 int pktc_idx; 271 int qsize_rxq; 272 int qsize_txq; 273 274 int linkdnrc; 275 struct link_config link_cfg; 276 277 struct timeval last_refreshed; 278 struct port_stats stats; 279 u_int tnl_cong_drops; 280 u_int tx_parse_error; 281 282 eventhandler_tag vlan_c; 283 284 struct callout tick; 285 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 286 287 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 288 }; 289 290 /* Where the cluster came from, how it has been carved up. */ 291 struct cluster_layout { 292 int8_t zidx; 293 int8_t hwidx; 294 uint16_t region1; /* mbufs laid out within this region */ 295 /* region2 is the DMA region */ 296 uint16_t region3; /* cluster_metadata within this region */ 297 }; 298 299 struct cluster_metadata { 300 u_int refcount; 301 #ifdef INVARIANTS 302 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 303 #endif 304 }; 305 306 struct fl_sdesc { 307 caddr_t cl; 308 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 309 struct cluster_layout cll; 310 }; 311 312 struct tx_desc { 313 __be64 flit[8]; 314 }; 315 316 struct tx_sdesc { 317 struct mbuf *m; /* m_nextpkt linked chain of frames */ 318 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 319 }; 320 321 322 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 323 struct iq_desc { 324 struct rss_header rss; 325 uint8_t cpl[IQ_PAD]; 326 struct rsp_ctrl rsp; 327 }; 328 #undef IQ_PAD 329 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 330 331 enum { 332 /* iq flags */ 333 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 334 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 335 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 336 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 337 338 /* iq state */ 339 IQS_DISABLED = 0, 340 IQS_BUSY = 1, 341 IQS_IDLE = 2, 342 }; 343 344 /* 345 * Ingress Queue: T4 is producer, driver is consumer. 346 */ 347 struct sge_iq { 348 uint32_t flags; 349 volatile int state; 350 struct adapter *adapter; 351 struct iq_desc *desc; /* KVA of descriptor ring */ 352 int8_t intr_pktc_idx; /* packet count threshold index */ 353 uint8_t gen; /* generation bit */ 354 uint8_t intr_params; /* interrupt holdoff parameters */ 355 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 356 uint16_t qsize; /* size (# of entries) of the queue */ 357 uint16_t sidx; /* index of the entry with the status page */ 358 uint16_t cidx; /* consumer index */ 359 uint16_t cntxt_id; /* SGE context id for the iq */ 360 uint16_t abs_id; /* absolute SGE id for the iq */ 361 362 STAILQ_ENTRY(sge_iq) link; 363 364 bus_dma_tag_t desc_tag; 365 bus_dmamap_t desc_map; 366 bus_addr_t ba; /* bus address of descriptor ring */ 367 }; 368 369 enum { 370 EQ_CTRL = 1, 371 EQ_ETH = 2, 372 EQ_OFLD = 3, 373 374 /* eq flags */ 375 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 376 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 377 EQ_ENABLED = (1 << 3), /* open for business */ 378 }; 379 380 /* Listed in order of preference. Update t4_sysctls too if you change these */ 381 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 382 383 /* 384 * Egress Queue: driver is producer, T4 is consumer. 385 * 386 * Note: A free list is an egress queue (driver produces the buffers and T4 387 * consumes them) but it's special enough to have its own struct (see sge_fl). 388 */ 389 struct sge_eq { 390 unsigned int flags; /* MUST be first */ 391 unsigned int cntxt_id; /* SGE context id for the eq */ 392 struct mtx eq_lock; 393 394 struct tx_desc *desc; /* KVA of descriptor ring */ 395 uint16_t doorbells; 396 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 397 u_int udb_qid; /* relative qid within the doorbell page */ 398 uint16_t sidx; /* index of the entry with the status page */ 399 uint16_t cidx; /* consumer idx (desc idx) */ 400 uint16_t pidx; /* producer idx (desc idx) */ 401 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 402 uint16_t dbidx; /* pidx of the most recent doorbell */ 403 uint16_t iqid; /* iq that gets egr_update for the eq */ 404 uint8_t tx_chan; /* tx channel used by the eq */ 405 volatile u_int equiq; /* EQUIQ outstanding */ 406 407 bus_dma_tag_t desc_tag; 408 bus_dmamap_t desc_map; 409 bus_addr_t ba; /* bus address of descriptor ring */ 410 char lockname[16]; 411 }; 412 413 struct sw_zone_info { 414 uma_zone_t zone; /* zone that this cluster comes from */ 415 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 416 int type; /* EXT_xxx type of the cluster */ 417 int8_t head_hwidx; 418 int8_t tail_hwidx; 419 }; 420 421 struct hw_buf_info { 422 int8_t zidx; /* backpointer to zone; -ve means unused */ 423 int8_t next; /* next hwidx for this zone; -1 means no more */ 424 int size; 425 }; 426 427 enum { 428 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 429 FL_DOOMED = (1 << 1), /* about to be destroyed */ 430 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 431 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 432 }; 433 434 #define FL_RUNNING_LOW(fl) \ 435 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 436 #define FL_NOT_RUNNING_LOW(fl) \ 437 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 438 439 struct sge_fl { 440 struct mtx fl_lock; 441 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 442 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 443 struct cluster_layout cll_def; /* default refill zone, layout */ 444 uint16_t lowat; /* # of buffers <= this means fl needs help */ 445 int flags; 446 uint16_t buf_boundary; 447 448 /* The 16b idx all deal with hw descriptors */ 449 uint16_t dbidx; /* hw pidx after last doorbell */ 450 uint16_t sidx; /* index of status page */ 451 volatile uint16_t hw_cidx; 452 453 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 454 uint32_t cidx; /* consumer index */ 455 uint32_t pidx; /* producer index */ 456 457 uint32_t dbval; 458 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 459 volatile uint32_t *udb; 460 461 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 462 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 463 uint64_t cl_allocated; /* # of clusters allocated */ 464 uint64_t cl_recycled; /* # of clusters recycled */ 465 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 466 467 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 468 struct mbuf *m0; 469 struct mbuf **pnext; 470 u_int remaining; 471 472 uint16_t qsize; /* # of hw descriptors (status page included) */ 473 uint16_t cntxt_id; /* SGE context id for the freelist */ 474 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 475 bus_dma_tag_t desc_tag; 476 bus_dmamap_t desc_map; 477 char lockname[16]; 478 bus_addr_t ba; /* bus address of descriptor ring */ 479 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 480 }; 481 482 struct mp_ring; 483 484 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 485 struct sge_txq { 486 struct sge_eq eq; /* MUST be first */ 487 488 struct ifnet *ifp; /* the interface this txq belongs to */ 489 struct mp_ring *r; /* tx software ring */ 490 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 491 struct sglist *gl; 492 __be32 cpl_ctrl0; /* for convenience */ 493 494 struct task tx_reclaim_task; 495 /* stats for common events first */ 496 497 uint64_t txcsum; /* # of times hardware assisted with checksum */ 498 uint64_t tso_wrs; /* # of TSO work requests */ 499 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 500 uint64_t imm_wrs; /* # of work requests with immediate data */ 501 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 502 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 503 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 504 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 505 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 506 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 507 508 /* stats for not-that-common events */ 509 } __aligned(CACHE_LINE_SIZE); 510 511 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 512 struct sge_rxq { 513 struct sge_iq iq; /* MUST be first */ 514 struct sge_fl fl; /* MUST follow iq */ 515 516 struct ifnet *ifp; /* the interface this rxq belongs to */ 517 #if defined(INET) || defined(INET6) 518 struct lro_ctrl lro; /* LRO state */ 519 #endif 520 521 /* stats for common events first */ 522 523 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 524 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 525 526 /* stats for not-that-common events */ 527 528 } __aligned(CACHE_LINE_SIZE); 529 530 static inline struct sge_rxq * 531 iq_to_rxq(struct sge_iq *iq) 532 { 533 534 return (__containerof(iq, struct sge_rxq, iq)); 535 } 536 537 538 #ifdef TCP_OFFLOAD 539 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 540 struct sge_ofld_rxq { 541 struct sge_iq iq; /* MUST be first */ 542 struct sge_fl fl; /* MUST follow iq */ 543 } __aligned(CACHE_LINE_SIZE); 544 545 static inline struct sge_ofld_rxq * 546 iq_to_ofld_rxq(struct sge_iq *iq) 547 { 548 549 return (__containerof(iq, struct sge_ofld_rxq, iq)); 550 } 551 #endif 552 553 struct wrqe { 554 STAILQ_ENTRY(wrqe) link; 555 struct sge_wrq *wrq; 556 int wr_len; 557 char wr[] __aligned(16); 558 }; 559 560 struct wrq_cookie { 561 TAILQ_ENTRY(wrq_cookie) link; 562 int ndesc; 563 int pidx; 564 }; 565 566 /* 567 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 568 * and offload tx queues are of this type. 569 */ 570 struct sge_wrq { 571 struct sge_eq eq; /* MUST be first */ 572 573 struct adapter *adapter; 574 struct task wrq_tx_task; 575 576 /* Tx desc reserved but WR not "committed" yet. */ 577 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 578 579 /* List of WRs ready to go out as soon as descriptors are available. */ 580 STAILQ_HEAD(, wrqe) wr_list; 581 u_int nwr_pending; 582 u_int ndesc_needed; 583 584 /* stats for common events first */ 585 586 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 587 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 588 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 589 590 /* stats for not-that-common events */ 591 592 /* 593 * Scratch space for work requests that wrap around after reaching the 594 * status page, and some infomation about the last WR that used it. 595 */ 596 uint16_t ss_pidx; 597 uint16_t ss_len; 598 uint8_t ss[SGE_MAX_WR_LEN]; 599 600 } __aligned(CACHE_LINE_SIZE); 601 602 603 #ifdef DEV_NETMAP 604 struct sge_nm_rxq { 605 struct port_info *pi; 606 607 struct iq_desc *iq_desc; 608 uint16_t iq_abs_id; 609 uint16_t iq_cntxt_id; 610 uint16_t iq_cidx; 611 uint16_t iq_sidx; 612 uint8_t iq_gen; 613 614 __be64 *fl_desc; 615 uint16_t fl_cntxt_id; 616 uint32_t fl_cidx; 617 uint32_t fl_pidx; 618 uint32_t fl_sidx; 619 uint32_t fl_db_val; 620 u_int fl_hwidx:4; 621 622 u_int nid; /* netmap ring # for this queue */ 623 624 /* infrequently used items after this */ 625 626 bus_dma_tag_t iq_desc_tag; 627 bus_dmamap_t iq_desc_map; 628 bus_addr_t iq_ba; 629 int intr_idx; 630 631 bus_dma_tag_t fl_desc_tag; 632 bus_dmamap_t fl_desc_map; 633 bus_addr_t fl_ba; 634 } __aligned(CACHE_LINE_SIZE); 635 636 struct sge_nm_txq { 637 struct tx_desc *desc; 638 uint16_t cidx; 639 uint16_t pidx; 640 uint16_t sidx; 641 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 642 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 643 uint16_t dbidx; /* pidx of the most recent doorbell */ 644 uint16_t doorbells; 645 volatile uint32_t *udb; 646 u_int udb_qid; 647 u_int cntxt_id; 648 __be32 cpl_ctrl0; /* for convenience */ 649 u_int nid; /* netmap ring # for this queue */ 650 651 /* infrequently used items after this */ 652 653 bus_dma_tag_t desc_tag; 654 bus_dmamap_t desc_map; 655 bus_addr_t ba; 656 int iqidx; 657 } __aligned(CACHE_LINE_SIZE); 658 #endif 659 660 struct sge { 661 int timer_val[SGE_NTIMERS]; 662 int counter_val[SGE_NCOUNTERS]; 663 int fl_starve_threshold; 664 int fl_starve_threshold2; 665 int eq_s_qpp; 666 int iq_s_qpp; 667 668 int nrxq; /* total # of Ethernet rx queues */ 669 int ntxq; /* total # of Ethernet tx tx queues */ 670 #ifdef TCP_OFFLOAD 671 int nofldrxq; /* total # of TOE rx queues */ 672 int nofldtxq; /* total # of TOE tx queues */ 673 #endif 674 #ifdef DEV_NETMAP 675 int nnmrxq; /* total # of netmap rx queues */ 676 int nnmtxq; /* total # of netmap tx queues */ 677 #endif 678 int niq; /* total # of ingress queues */ 679 int neq; /* total # of egress queues */ 680 681 struct sge_iq fwq; /* Firmware event queue */ 682 struct sge_wrq mgmtq; /* Management queue (control queue) */ 683 struct sge_wrq *ctrlq; /* Control queues */ 684 struct sge_txq *txq; /* NIC tx queues */ 685 struct sge_rxq *rxq; /* NIC rx queues */ 686 #ifdef TCP_OFFLOAD 687 struct sge_wrq *ofld_txq; /* TOE tx queues */ 688 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 689 #endif 690 #ifdef DEV_NETMAP 691 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 692 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 693 #endif 694 695 uint16_t iq_start; 696 int eq_start; 697 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 698 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 699 700 int pad_boundary; 701 int pack_boundary; 702 int8_t safe_hwidx1; /* may not have room for metadata */ 703 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 704 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 705 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 706 }; 707 708 struct rss_header; 709 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 710 struct mbuf *); 711 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 712 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 713 714 struct adapter { 715 SLIST_ENTRY(adapter) link; 716 device_t dev; 717 struct cdev *cdev; 718 719 /* PCIe register resources */ 720 int regs_rid; 721 struct resource *regs_res; 722 int msix_rid; 723 struct resource *msix_res; 724 bus_space_handle_t bh; 725 bus_space_tag_t bt; 726 bus_size_t mmio_len; 727 int udbs_rid; 728 struct resource *udbs_res; 729 volatile uint8_t *udbs_base; 730 731 unsigned int pf; 732 unsigned int mbox; 733 734 /* Interrupt information */ 735 int intr_type; 736 int intr_count; 737 struct irq { 738 struct resource *res; 739 int rid; 740 void *tag; 741 } *irq; 742 743 bus_dma_tag_t dmat; /* Parent DMA tag */ 744 745 struct sge sge; 746 int lro_timeout; 747 748 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */ 749 struct port_info *port[MAX_NPORTS]; 750 uint8_t chan_map[NCHAN]; 751 752 #ifdef TCP_OFFLOAD 753 void *tom_softc; /* (struct tom_data *) */ 754 struct tom_tunables tt; 755 void *iwarp_softc; /* (struct c4iw_dev *) */ 756 void *iscsi_softc; 757 #endif 758 struct l2t_data *l2t; /* L2 table */ 759 struct tid_info tids; 760 761 uint16_t doorbells; 762 int open_device_map; 763 #ifdef TCP_OFFLOAD 764 int offload_map; /* ports with IFCAP_TOE enabled */ 765 int active_ulds; /* ULDs activated on this adapter */ 766 #endif 767 int flags; 768 int debug_flags; 769 770 char ifp_lockname[16]; 771 struct mtx ifp_lock; 772 struct ifnet *ifp; /* tracer ifp */ 773 struct ifmedia media; 774 int traceq; /* iq used by all tracers, -1 if none */ 775 int tracer_valid; /* bitmap of valid tracers */ 776 int tracer_enabled; /* bitmap of enabled tracers */ 777 778 char fw_version[32]; 779 char cfg_file[32]; 780 u_int cfcsum; 781 struct adapter_params params; 782 struct t4_virt_res vres; 783 784 uint16_t linkcaps; 785 uint16_t niccaps; 786 uint16_t toecaps; 787 uint16_t rdmacaps; 788 uint16_t iscsicaps; 789 uint16_t fcoecaps; 790 791 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 792 793 struct mtx sc_lock; 794 char lockname[16]; 795 796 /* Starving free lists */ 797 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 798 TAILQ_HEAD(, sge_fl) sfl; 799 struct callout sfl_callout; 800 801 struct mtx regwin_lock; /* for indirect reads and memory windows */ 802 803 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 804 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 805 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 806 807 #ifdef INVARIANTS 808 const char *last_op; 809 const void *last_op_thr; 810 #endif 811 812 int sc_do_rxcopy; 813 }; 814 815 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 816 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 817 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 818 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 819 820 #define ASSERT_SYNCHRONIZED_OP(sc) \ 821 KASSERT(IS_BUSY(sc) && \ 822 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 823 ("%s: operation not synchronized.", __func__)) 824 825 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 826 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 827 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 828 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 829 830 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 831 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 832 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 833 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 834 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 835 836 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 837 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 838 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 839 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 840 841 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 842 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 843 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 844 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 845 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 846 847 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 848 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 849 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 850 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 851 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 852 853 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 854 do { \ 855 if (sc->debug_flags & DF_DUMP_MBOX) { \ 856 log(LOG_NOTICE, \ 857 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 858 "%016llx %016llx %016llx %016llx\n", \ 859 device_get_nameunit(sc->dev), mbox, \ 860 (unsigned long long)t4_read_reg64(sc, data_reg), \ 861 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 862 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 863 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 864 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 865 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 866 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 867 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 868 } \ 869 } while (0) 870 871 #define for_each_txq(pi, iter, q) \ 872 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 873 iter < pi->ntxq; ++iter, ++q) 874 #define for_each_rxq(pi, iter, q) \ 875 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 876 iter < pi->nrxq; ++iter, ++q) 877 #define for_each_ofld_txq(pi, iter, q) \ 878 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 879 iter < pi->nofldtxq; ++iter, ++q) 880 #define for_each_ofld_rxq(pi, iter, q) \ 881 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 882 iter < pi->nofldrxq; ++iter, ++q) 883 #define for_each_nm_txq(pi, iter, q) \ 884 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \ 885 iter < pi->nnmtxq; ++iter, ++q) 886 #define for_each_nm_rxq(pi, iter, q) \ 887 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \ 888 iter < pi->nnmrxq; ++iter, ++q) 889 890 #define IDXINCR(idx, incr, wrap) do { \ 891 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 892 } while (0) 893 #define IDXDIFF(head, tail, wrap) \ 894 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 895 896 /* One for errors, one for firmware events */ 897 #define T4_EXTRA_INTR 2 898 899 static inline uint32_t 900 t4_read_reg(struct adapter *sc, uint32_t reg) 901 { 902 903 return bus_space_read_4(sc->bt, sc->bh, reg); 904 } 905 906 static inline void 907 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 908 { 909 910 bus_space_write_4(sc->bt, sc->bh, reg, val); 911 } 912 913 static inline uint64_t 914 t4_read_reg64(struct adapter *sc, uint32_t reg) 915 { 916 917 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 918 } 919 920 static inline void 921 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 922 { 923 924 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 925 } 926 927 static inline void 928 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 929 { 930 931 *val = pci_read_config(sc->dev, reg, 1); 932 } 933 934 static inline void 935 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 936 { 937 938 pci_write_config(sc->dev, reg, val, 1); 939 } 940 941 static inline void 942 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 943 { 944 945 *val = pci_read_config(sc->dev, reg, 2); 946 } 947 948 static inline void 949 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 950 { 951 952 pci_write_config(sc->dev, reg, val, 2); 953 } 954 955 static inline void 956 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 957 { 958 959 *val = pci_read_config(sc->dev, reg, 4); 960 } 961 962 static inline void 963 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 964 { 965 966 pci_write_config(sc->dev, reg, val, 4); 967 } 968 969 static inline struct port_info * 970 adap2pinfo(struct adapter *sc, int idx) 971 { 972 973 return (sc->port[idx]); 974 } 975 976 static inline void 977 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 978 { 979 980 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 981 } 982 983 static inline bool 984 is_10G_port(const struct port_info *pi) 985 { 986 987 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 988 } 989 990 static inline bool 991 is_40G_port(const struct port_info *pi) 992 { 993 994 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 995 } 996 997 static inline int 998 tx_resume_threshold(struct sge_eq *eq) 999 { 1000 1001 /* not quite the same as qsize / 4, but this will do. */ 1002 return (eq->sidx / 4); 1003 } 1004 1005 /* t4_main.c */ 1006 int t4_os_find_pci_capability(struct adapter *, int); 1007 int t4_os_pci_save_state(struct adapter *); 1008 int t4_os_pci_restore_state(struct adapter *); 1009 void t4_os_portmod_changed(const struct adapter *, int); 1010 void t4_os_link_changed(struct adapter *, int, int, int); 1011 void t4_iterate(void (*)(struct adapter *, void *), void *); 1012 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 1013 int t4_register_an_handler(struct adapter *, an_handler_t); 1014 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 1015 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1016 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 1017 void end_synchronized_op(struct adapter *, int); 1018 int update_mac_settings(struct ifnet *, int); 1019 int adapter_full_init(struct adapter *); 1020 int adapter_full_uninit(struct adapter *); 1021 int port_full_init(struct port_info *); 1022 int port_full_uninit(struct port_info *); 1023 1024 #ifdef DEV_NETMAP 1025 /* t4_netmap.c */ 1026 int create_netmap_ifnet(struct port_info *); 1027 int destroy_netmap_ifnet(struct port_info *); 1028 void t4_nm_intr(void *); 1029 #endif 1030 1031 /* t4_sge.c */ 1032 void t4_sge_modload(void); 1033 void t4_sge_modunload(void); 1034 uint64_t t4_sge_extfree_refs(void); 1035 void t4_init_sge_cpl_handlers(struct adapter *); 1036 void t4_tweak_chip_settings(struct adapter *); 1037 int t4_read_chip_settings(struct adapter *); 1038 int t4_create_dma_tag(struct adapter *); 1039 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1040 struct sysctl_oid_list *); 1041 int t4_destroy_dma_tag(struct adapter *); 1042 int t4_setup_adapter_queues(struct adapter *); 1043 int t4_teardown_adapter_queues(struct adapter *); 1044 int t4_setup_port_queues(struct port_info *); 1045 int t4_teardown_port_queues(struct port_info *); 1046 void t4_intr_all(void *); 1047 void t4_intr(void *); 1048 void t4_intr_err(void *); 1049 void t4_intr_evt(void *); 1050 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1051 void t4_update_fl_bufsize(struct ifnet *); 1052 int parse_pkt(struct mbuf **); 1053 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1054 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1055 int tnl_cong(struct port_info *); 1056 1057 /* t4_tracer.c */ 1058 struct t4_tracer; 1059 void t4_tracer_modload(void); 1060 void t4_tracer_modunload(void); 1061 void t4_tracer_port_detach(struct adapter *); 1062 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1063 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1064 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1065 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1066 1067 static inline struct wrqe * 1068 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1069 { 1070 int len = offsetof(struct wrqe, wr) + wr_len; 1071 struct wrqe *wr; 1072 1073 wr = malloc(len, M_CXGBE, M_NOWAIT); 1074 if (__predict_false(wr == NULL)) 1075 return (NULL); 1076 wr->wr_len = wr_len; 1077 wr->wrq = wrq; 1078 return (wr); 1079 } 1080 1081 static inline void * 1082 wrtod(struct wrqe *wr) 1083 { 1084 return (&wr->wr[0]); 1085 } 1086 1087 static inline void 1088 free_wrqe(struct wrqe *wr) 1089 { 1090 free(wr, M_CXGBE); 1091 } 1092 1093 static inline void 1094 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1095 { 1096 struct sge_wrq *wrq = wr->wrq; 1097 1098 TXQ_LOCK(wrq); 1099 t4_wrq_tx_locked(sc, wrq, wr); 1100 TXQ_UNLOCK(wrq); 1101 } 1102 1103 #endif 1104