1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_media.h> 58 #include <net/pfil.h> 59 #include <netinet/in.h> 60 #include <netinet/tcp_lro.h> 61 62 #include "offload.h" 63 #include "t4_ioctl.h" 64 #include "common/t4_msg.h" 65 #include "firmware/t4fw_interface.h" 66 67 #define KTR_CXGBE KTR_SPARE3 68 MALLOC_DECLARE(M_CXGBE); 69 #define CXGBE_UNIMPLEMENTED(s) \ 70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 71 72 /* 73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 74 * LIST_HEAD when building iw_cxgbe. 75 */ 76 #define CXGBE_LIST_HEAD(name, type) \ 77 struct name { \ 78 struct type *lh_first; /* first element */ \ 79 } 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 112 CL_METADATA_SIZE = CACHE_LINE_SIZE, 113 114 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 115 TX_SGL_SEGS = 39, 116 TX_SGL_SEGS_TSO = 38, 117 TX_SGL_SEGS_VM = 38, 118 TX_SGL_SEGS_VM_TSO = 37, 119 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 120 TX_SGL_SEGS_VXLAN_TSO = 37, 121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 122 }; 123 124 enum { 125 /* adapter intr_type */ 126 INTR_INTX = (1 << 0), 127 INTR_MSI = (1 << 1), 128 INTR_MSIX = (1 << 2) 129 }; 130 131 enum { 132 XGMAC_MTU = (1 << 0), 133 XGMAC_PROMISC = (1 << 1), 134 XGMAC_ALLMULTI = (1 << 2), 135 XGMAC_VLANEX = (1 << 3), 136 XGMAC_UCADDR = (1 << 4), 137 XGMAC_MCADDRS = (1 << 5), 138 139 XGMAC_ALL = 0xffff 140 }; 141 142 enum { 143 /* flags understood by begin_synchronized_op */ 144 HOLD_LOCK = (1 << 0), 145 SLEEP_OK = (1 << 1), 146 INTR_OK = (1 << 2), 147 148 /* flags understood by end_synchronized_op */ 149 LOCK_HELD = HOLD_LOCK, 150 }; 151 152 enum { 153 /* adapter flags. synch_op or adapter_lock. */ 154 FULL_INIT_DONE = (1 << 0), 155 FW_OK = (1 << 1), 156 CHK_MBOX_ACCESS = (1 << 2), 157 MASTER_PF = (1 << 3), 158 BUF_PACKING_OK = (1 << 6), 159 IS_VF = (1 << 7), 160 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 161 CXGBE_BUSY = (1 << 9), 162 163 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 164 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 165 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 166 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 167 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 168 169 /* port flags */ 170 HAS_TRACEQ = (1 << 3), 171 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 172 173 /* VI flags */ 174 DOOMED = (1 << 0), 175 VI_INIT_DONE = (1 << 1), 176 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 177 TX_USES_VM_WR = (1 << 3), 178 VI_SKIP_STATS = (1 << 4), 179 180 /* adapter debug_flags */ 181 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 182 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 183 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 184 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 185 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 186 }; 187 188 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 189 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 190 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 191 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 192 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 193 194 struct vi_info { 195 device_t dev; 196 struct port_info *pi; 197 struct adapter *adapter; 198 199 struct ifnet *ifp; 200 struct pfil_head *pfil; 201 202 unsigned long flags; 203 int if_flags; 204 205 uint16_t *rss, *nm_rss; 206 uint16_t viid; /* opaque VI identifier */ 207 uint16_t smt_idx; 208 uint16_t vin; 209 uint8_t vfvld; 210 int16_t xact_addr_filt;/* index of exact MAC address filter */ 211 uint16_t rss_size; /* size of VI's RSS table slice */ 212 uint16_t rss_base; /* start of VI's RSS table slice */ 213 int hashen; 214 215 int nintr; 216 int first_intr; 217 218 /* These need to be int as they are used in sysctl */ 219 int ntxq; /* # of tx queues */ 220 int first_txq; /* index of first tx queue */ 221 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 222 int nrxq; /* # of rx queues */ 223 int first_rxq; /* index of first rx queue */ 224 int nofldtxq; /* # of offload tx queues */ 225 int first_ofld_txq; /* index of first offload tx queue */ 226 int nofldrxq; /* # of offload rx queues */ 227 int first_ofld_rxq; /* index of first offload rx queue */ 228 int nnmtxq; 229 int first_nm_txq; 230 int nnmrxq; 231 int first_nm_rxq; 232 int tmr_idx; 233 int ofld_tmr_idx; 234 int pktc_idx; 235 int ofld_pktc_idx; 236 int qsize_rxq; 237 int qsize_txq; 238 239 struct timeval last_refreshed; 240 struct fw_vi_stats_vf stats; 241 struct mtx tick_mtx; 242 struct callout tick; 243 244 struct sysctl_ctx_list ctx; 245 struct sysctl_oid *rxq_oid; 246 struct sysctl_oid *txq_oid; 247 struct sysctl_oid *nm_rxq_oid; 248 struct sysctl_oid *nm_txq_oid; 249 struct sysctl_oid *ofld_rxq_oid; 250 struct sysctl_oid *ofld_txq_oid; 251 252 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 253 u_int txq_rr; 254 u_int rxq_rr; 255 }; 256 257 struct tx_ch_rl_params { 258 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 259 uint32_t maxrate; 260 }; 261 262 /* CLRL state */ 263 enum clrl_state { 264 CS_UNINITIALIZED = 0, 265 CS_PARAMS_SET, /* sw parameters have been set. */ 266 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 267 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 268 CS_HW_CONFIGURED /* configured in the hardware. */ 269 }; 270 271 /* CLRL flags */ 272 enum { 273 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 274 }; 275 276 struct tx_cl_rl_params { 277 enum clrl_state state; 278 int refcount; 279 uint8_t flags; 280 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 281 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 282 enum fw_sched_params_mode mode; /* aggr or per-flow */ 283 uint32_t maxrate; 284 uint16_t pktsize; 285 uint16_t burstsize; 286 }; 287 288 /* Tx scheduler parameters for a channel/port */ 289 struct tx_sched_params { 290 /* Channel Rate Limiter */ 291 struct tx_ch_rl_params ch_rl; 292 293 /* Class WRR */ 294 /* XXX */ 295 296 /* Class Rate Limiter (including the default pktsize and burstsize). */ 297 int pktsize; 298 int burstsize; 299 struct tx_cl_rl_params cl_rl[]; 300 }; 301 302 struct port_info { 303 device_t dev; 304 struct adapter *adapter; 305 306 struct vi_info *vi; 307 int nvi; 308 int up_vis; 309 int uld_vis; 310 bool vxlan_tcam_entry; 311 312 struct tx_sched_params *sched_params; 313 314 struct mtx pi_lock; 315 char lockname[16]; 316 unsigned long flags; 317 318 uint8_t lport; /* associated offload logical port */ 319 int8_t mdio_addr; 320 uint8_t port_type; 321 uint8_t mod_type; 322 uint8_t port_id; 323 uint8_t tx_chan; 324 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 325 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 326 uint8_t rx_c_chan; /* rx TP c-channel */ 327 328 struct link_config link_cfg; 329 struct ifmedia media; 330 331 struct port_stats stats; 332 u_int tnl_cong_drops; 333 u_int tx_parse_error; 334 int fcs_reg; 335 uint64_t fcs_base; 336 337 struct sysctl_ctx_list ctx; 338 }; 339 340 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 341 342 struct cluster_metadata { 343 uma_zone_t zone; 344 caddr_t cl; 345 u_int refcount; 346 }; 347 348 struct fl_sdesc { 349 caddr_t cl; 350 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 351 int16_t moff; /* offset of metadata from cl */ 352 uint8_t zidx; 353 }; 354 355 struct tx_desc { 356 __be64 flit[8]; 357 }; 358 359 struct tx_sdesc { 360 struct mbuf *m; /* m_nextpkt linked chain of frames */ 361 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 362 }; 363 364 365 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 366 struct iq_desc { 367 struct rss_header rss; 368 uint8_t cpl[IQ_PAD]; 369 struct rsp_ctrl rsp; 370 }; 371 #undef IQ_PAD 372 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 373 374 enum { 375 /* iq flags */ 376 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 377 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 378 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 379 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 380 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 381 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 382 383 /* iq state */ 384 IQS_DISABLED = 0, 385 IQS_BUSY = 1, 386 IQS_IDLE = 2, 387 388 /* netmap related flags */ 389 NM_OFF = 0, 390 NM_ON = 1, 391 NM_BUSY = 2, 392 }; 393 394 enum { 395 CPL_COOKIE_RESERVED = 0, 396 CPL_COOKIE_FILTER, 397 CPL_COOKIE_DDP0, 398 CPL_COOKIE_DDP1, 399 CPL_COOKIE_TOM, 400 CPL_COOKIE_HASHFILTER, 401 CPL_COOKIE_ETHOFLD, 402 CPL_COOKIE_KERN_TLS, 403 404 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 405 }; 406 407 struct sge_iq; 408 struct rss_header; 409 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 410 struct mbuf *); 411 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 412 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 413 414 /* 415 * Ingress Queue: T4 is producer, driver is consumer. 416 */ 417 struct sge_iq { 418 uint32_t flags; 419 volatile int state; 420 struct adapter *adapter; 421 struct iq_desc *desc; /* KVA of descriptor ring */ 422 int8_t intr_pktc_idx; /* packet count threshold index */ 423 uint8_t gen; /* generation bit */ 424 uint8_t intr_params; /* interrupt holdoff parameters */ 425 int8_t cong; /* congestion settings */ 426 uint16_t qsize; /* size (# of entries) of the queue */ 427 uint16_t sidx; /* index of the entry with the status page */ 428 uint16_t cidx; /* consumer index */ 429 uint16_t cntxt_id; /* SGE context id for the iq */ 430 uint16_t abs_id; /* absolute SGE id for the iq */ 431 int16_t intr_idx; /* interrupt used by the queue */ 432 433 STAILQ_ENTRY(sge_iq) link; 434 435 bus_dma_tag_t desc_tag; 436 bus_dmamap_t desc_map; 437 bus_addr_t ba; /* bus address of descriptor ring */ 438 }; 439 440 enum { 441 /* eq type */ 442 EQ_CTRL = 1, 443 EQ_ETH = 2, 444 EQ_OFLD = 3, 445 446 /* eq flags */ 447 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 448 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 449 EQ_ENABLED = (1 << 3), /* open for business */ 450 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 451 }; 452 453 /* Listed in order of preference. Update t4_sysctls too if you change these */ 454 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 455 456 /* 457 * Egress Queue: driver is producer, T4 is consumer. 458 * 459 * Note: A free list is an egress queue (driver produces the buffers and T4 460 * consumes them) but it's special enough to have its own struct (see sge_fl). 461 */ 462 struct sge_eq { 463 unsigned int flags; /* MUST be first */ 464 unsigned int cntxt_id; /* SGE context id for the eq */ 465 unsigned int abs_id; /* absolute SGE id for the eq */ 466 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 467 uint8_t doorbells; 468 uint8_t tx_chan; /* tx channel used by the eq */ 469 struct mtx eq_lock; 470 471 struct tx_desc *desc; /* KVA of descriptor ring */ 472 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 473 u_int udb_qid; /* relative qid within the doorbell page */ 474 uint16_t sidx; /* index of the entry with the status page */ 475 uint16_t cidx; /* consumer idx (desc idx) */ 476 uint16_t pidx; /* producer idx (desc idx) */ 477 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 478 uint16_t dbidx; /* pidx of the most recent doorbell */ 479 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 480 volatile u_int equiq; /* EQUIQ outstanding */ 481 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 482 483 bus_dma_tag_t desc_tag; 484 bus_dmamap_t desc_map; 485 bus_addr_t ba; /* bus address of descriptor ring */ 486 char lockname[16]; 487 }; 488 489 struct rx_buf_info { 490 uma_zone_t zone; /* zone that this cluster comes from */ 491 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 492 * hwsize[hwidx1] = size1. No spare. */ 493 uint16_t size2; /* hwsize[hwidx2] = size2. 494 * spare in cluster = size1 - size2. */ 495 int8_t hwidx1; /* SGE bufsize idx for size1 */ 496 int8_t hwidx2; /* SGE bufsize idx for size2 */ 497 uint8_t type; /* EXT_xxx type of the cluster */ 498 }; 499 500 enum { 501 NUM_MEMWIN = 3, 502 503 MEMWIN0_APERTURE = 2048, 504 MEMWIN0_BASE = 0x1b800, 505 506 MEMWIN1_APERTURE = 32768, 507 MEMWIN1_BASE = 0x28000, 508 509 MEMWIN2_APERTURE_T4 = 65536, 510 MEMWIN2_BASE_T4 = 0x30000, 511 512 MEMWIN2_APERTURE_T5 = 128 * 1024, 513 MEMWIN2_BASE_T5 = 0x60000, 514 }; 515 516 struct memwin { 517 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 518 uint32_t mw_base; /* constant after setup_memwin */ 519 uint32_t mw_aperture; /* ditto */ 520 uint32_t mw_curpos; /* protected by mw_lock */ 521 }; 522 523 enum { 524 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 525 FL_DOOMED = (1 << 1), /* about to be destroyed */ 526 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 527 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 528 }; 529 530 #define FL_RUNNING_LOW(fl) \ 531 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 532 #define FL_NOT_RUNNING_LOW(fl) \ 533 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 534 535 struct sge_fl { 536 struct mtx fl_lock; 537 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 538 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 539 uint16_t zidx; /* refill zone idx */ 540 uint16_t safe_zidx; 541 uint16_t lowat; /* # of buffers <= this means fl needs help */ 542 int flags; 543 uint16_t buf_boundary; 544 545 /* The 16b idx all deal with hw descriptors */ 546 uint16_t dbidx; /* hw pidx after last doorbell */ 547 uint16_t sidx; /* index of status page */ 548 volatile uint16_t hw_cidx; 549 550 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 551 uint32_t cidx; /* consumer index */ 552 uint32_t pidx; /* producer index */ 553 554 uint32_t dbval; 555 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 556 volatile uint32_t *udb; 557 558 uint64_t cl_allocated; /* # of clusters allocated */ 559 uint64_t cl_recycled; /* # of clusters recycled */ 560 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 561 562 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 563 struct mbuf *m0; 564 struct mbuf **pnext; 565 u_int remaining; 566 567 uint16_t qsize; /* # of hw descriptors (status page included) */ 568 uint16_t cntxt_id; /* SGE context id for the freelist */ 569 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 570 bus_dma_tag_t desc_tag; 571 bus_dmamap_t desc_map; 572 char lockname[16]; 573 bus_addr_t ba; /* bus address of descriptor ring */ 574 }; 575 576 struct mp_ring; 577 578 struct txpkts { 579 uint8_t wr_type; /* type 0 or type 1 */ 580 uint8_t npkt; /* # of packets in this work request */ 581 uint8_t len16; /* # of 16B pieces used by this work request */ 582 uint8_t score; 583 uint8_t max_npkt; /* maximum number of packets allowed */ 584 uint16_t plen; /* total payload (sum of all packets) */ 585 586 /* straight from fw_eth_tx_pkts_vm_wr. */ 587 __u8 ethmacdst[6]; 588 __u8 ethmacsrc[6]; 589 __be16 ethtype; 590 __be16 vlantci; 591 592 struct mbuf *mb[15]; 593 }; 594 595 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 596 struct sge_txq { 597 struct sge_eq eq; /* MUST be first */ 598 599 struct ifnet *ifp; /* the interface this txq belongs to */ 600 struct mp_ring *r; /* tx software ring */ 601 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 602 struct sglist *gl; 603 __be32 cpl_ctrl0; /* for convenience */ 604 int tc_idx; /* traffic class */ 605 uint64_t last_tx; /* cycle count when eth_tx was last called */ 606 struct txpkts txp; 607 608 struct task tx_reclaim_task; 609 /* stats for common events first */ 610 611 uint64_t txcsum; /* # of times hardware assisted with checksum */ 612 uint64_t tso_wrs; /* # of TSO work requests */ 613 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 614 uint64_t imm_wrs; /* # of work requests with immediate data */ 615 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 616 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 617 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 618 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 619 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 620 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 621 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 622 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 623 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 624 uint64_t vxlan_txcsum; 625 626 uint64_t kern_tls_records; 627 uint64_t kern_tls_short; 628 uint64_t kern_tls_partial; 629 uint64_t kern_tls_full; 630 uint64_t kern_tls_octets; 631 uint64_t kern_tls_waste; 632 uint64_t kern_tls_options; 633 uint64_t kern_tls_header; 634 uint64_t kern_tls_fin; 635 uint64_t kern_tls_fin_short; 636 uint64_t kern_tls_cbc; 637 uint64_t kern_tls_gcm; 638 639 /* stats for not-that-common events */ 640 641 /* Optional scratch space for constructing work requests. */ 642 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 643 } __aligned(CACHE_LINE_SIZE); 644 645 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 646 struct sge_rxq { 647 struct sge_iq iq; /* MUST be first */ 648 struct sge_fl fl; /* MUST follow iq */ 649 650 struct ifnet *ifp; /* the interface this rxq belongs to */ 651 struct lro_ctrl lro; /* LRO state */ 652 653 /* stats for common events first */ 654 655 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 656 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 657 uint64_t vxlan_rxcsum; 658 659 /* stats for not-that-common events */ 660 661 } __aligned(CACHE_LINE_SIZE); 662 663 static inline struct sge_rxq * 664 iq_to_rxq(struct sge_iq *iq) 665 { 666 667 return (__containerof(iq, struct sge_rxq, iq)); 668 } 669 670 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 671 struct sge_ofld_rxq { 672 struct sge_iq iq; /* MUST be first */ 673 struct sge_fl fl; /* MUST follow iq */ 674 counter_u64_t rx_iscsi_ddp_setup_ok; 675 counter_u64_t rx_iscsi_ddp_setup_error; 676 uint64_t rx_iscsi_ddp_pdus; 677 uint64_t rx_iscsi_ddp_octets; 678 uint64_t rx_iscsi_fl_pdus; 679 uint64_t rx_iscsi_fl_octets; 680 uint64_t rx_iscsi_padding_errors; 681 uint64_t rx_iscsi_header_digest_errors; 682 uint64_t rx_iscsi_data_digest_errors; 683 u_long rx_toe_tls_records; 684 u_long rx_toe_tls_octets; 685 } __aligned(CACHE_LINE_SIZE); 686 687 static inline struct sge_ofld_rxq * 688 iq_to_ofld_rxq(struct sge_iq *iq) 689 { 690 691 return (__containerof(iq, struct sge_ofld_rxq, iq)); 692 } 693 694 struct wrqe { 695 STAILQ_ENTRY(wrqe) link; 696 struct sge_wrq *wrq; 697 int wr_len; 698 char wr[] __aligned(16); 699 }; 700 701 struct wrq_cookie { 702 TAILQ_ENTRY(wrq_cookie) link; 703 int ndesc; 704 int pidx; 705 }; 706 707 /* 708 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 709 * are of this type. 710 */ 711 struct sge_wrq { 712 struct sge_eq eq; /* MUST be first */ 713 714 struct adapter *adapter; 715 struct task wrq_tx_task; 716 717 /* Tx desc reserved but WR not "committed" yet. */ 718 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 719 720 /* List of WRs ready to go out as soon as descriptors are available. */ 721 STAILQ_HEAD(, wrqe) wr_list; 722 u_int nwr_pending; 723 u_int ndesc_needed; 724 725 /* stats for common events first */ 726 727 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 728 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 729 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 730 731 /* stats for not-that-common events */ 732 733 /* 734 * Scratch space for work requests that wrap around after reaching the 735 * status page, and some information about the last WR that used it. 736 */ 737 uint16_t ss_pidx; 738 uint16_t ss_len; 739 uint8_t ss[SGE_MAX_WR_LEN]; 740 741 } __aligned(CACHE_LINE_SIZE); 742 743 /* ofld_txq: SGE egress queue + miscellaneous items */ 744 struct sge_ofld_txq { 745 struct sge_wrq wrq; 746 counter_u64_t tx_iscsi_pdus; 747 counter_u64_t tx_iscsi_octets; 748 counter_u64_t tx_iscsi_iso_wrs; 749 counter_u64_t tx_toe_tls_records; 750 counter_u64_t tx_toe_tls_octets; 751 } __aligned(CACHE_LINE_SIZE); 752 753 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 754 struct sge_nm_rxq { 755 /* Items used by the driver rx ithread are in this cacheline. */ 756 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 757 u_int nid; /* netmap ring # for this queue */ 758 struct vi_info *vi; 759 760 struct iq_desc *iq_desc; 761 uint16_t iq_abs_id; 762 uint16_t iq_cntxt_id; 763 uint16_t iq_cidx; 764 uint16_t iq_sidx; 765 uint8_t iq_gen; 766 uint32_t fl_sidx; 767 768 /* Items used by netmap rxsync are in this cacheline. */ 769 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 770 uint16_t fl_cntxt_id; 771 uint32_t fl_pidx; 772 uint32_t fl_sidx2; /* copy of fl_sidx */ 773 uint32_t fl_db_val; 774 u_int fl_db_saved; 775 u_int fl_db_threshold; /* in descriptors */ 776 u_int fl_hwidx:4; 777 778 /* 779 * fl_cidx is used by both the ithread and rxsync, the rest are not used 780 * in the rx fast path. 781 */ 782 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 783 784 bus_dma_tag_t iq_desc_tag; 785 bus_dmamap_t iq_desc_map; 786 bus_addr_t iq_ba; 787 int intr_idx; 788 789 bus_dma_tag_t fl_desc_tag; 790 bus_dmamap_t fl_desc_map; 791 bus_addr_t fl_ba; 792 }; 793 794 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 795 struct sge_nm_txq { 796 struct tx_desc *desc; 797 uint16_t cidx; 798 uint16_t pidx; 799 uint16_t sidx; 800 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 801 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 802 uint16_t dbidx; /* pidx of the most recent doorbell */ 803 uint8_t doorbells; 804 volatile uint32_t *udb; 805 u_int udb_qid; 806 u_int cntxt_id; 807 __be32 cpl_ctrl0; /* for convenience */ 808 __be32 op_pkd; /* ditto */ 809 u_int nid; /* netmap ring # for this queue */ 810 811 /* infrequently used items after this */ 812 813 bus_dma_tag_t desc_tag; 814 bus_dmamap_t desc_map; 815 bus_addr_t ba; 816 int iqidx; 817 } __aligned(CACHE_LINE_SIZE); 818 819 struct sge { 820 int nrxq; /* total # of Ethernet rx queues */ 821 int ntxq; /* total # of Ethernet tx queues */ 822 int nofldrxq; /* total # of TOE rx queues */ 823 int nofldtxq; /* total # of TOE tx queues */ 824 int nnmrxq; /* total # of netmap rx queues */ 825 int nnmtxq; /* total # of netmap tx queues */ 826 int niq; /* total # of ingress queues */ 827 int neq; /* total # of egress queues */ 828 829 struct sge_iq fwq; /* Firmware event queue */ 830 struct sge_wrq *ctrlq; /* Control queues */ 831 struct sge_txq *txq; /* NIC tx queues */ 832 struct sge_rxq *rxq; /* NIC rx queues */ 833 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 834 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 835 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 836 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 837 838 uint16_t iq_start; /* first cntxt_id */ 839 uint16_t iq_base; /* first abs_id */ 840 int eq_start; /* first cntxt_id */ 841 int eq_base; /* first abs_id */ 842 int iqmap_sz; 843 int eqmap_sz; 844 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 845 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 846 847 int8_t safe_zidx; 848 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 849 }; 850 851 struct devnames { 852 const char *nexus_name; 853 const char *ifnet_name; 854 const char *vi_ifnet_name; 855 const char *pf03_drv_name; 856 const char *vf_nexus_name; 857 const char *vf_ifnet_name; 858 }; 859 860 struct clip_entry; 861 862 struct adapter { 863 SLIST_ENTRY(adapter) link; 864 device_t dev; 865 struct cdev *cdev; 866 const struct devnames *names; 867 868 /* PCIe register resources */ 869 int regs_rid; 870 struct resource *regs_res; 871 int msix_rid; 872 struct resource *msix_res; 873 bus_space_handle_t bh; 874 bus_space_tag_t bt; 875 bus_size_t mmio_len; 876 int udbs_rid; 877 struct resource *udbs_res; 878 volatile uint8_t *udbs_base; 879 880 unsigned int pf; 881 unsigned int mbox; 882 unsigned int vpd_busy; 883 unsigned int vpd_flag; 884 885 /* Interrupt information */ 886 int intr_type; 887 int intr_count; 888 struct irq { 889 struct resource *res; 890 int rid; 891 void *tag; 892 struct sge_rxq *rxq; 893 struct sge_nm_rxq *nm_rxq; 894 } __aligned(CACHE_LINE_SIZE) *irq; 895 int sge_gts_reg; 896 int sge_kdoorbell_reg; 897 898 bus_dma_tag_t dmat; /* Parent DMA tag */ 899 900 struct sge sge; 901 int lro_timeout; 902 int sc_do_rxcopy; 903 904 int vxlan_port; 905 u_int vxlan_refcount; 906 int rawf_base; 907 int nrawf; 908 909 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 910 struct port_info *port[MAX_NPORTS]; 911 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 912 913 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 914 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 915 u_long clip_mask; 916 int clip_gen; 917 struct timeout_task clip_task; 918 919 void *tom_softc; /* (struct tom_data *) */ 920 struct tom_tunables tt; 921 struct t4_offload_policy *policy; 922 struct rwlock policy_lock; 923 924 void *iwarp_softc; /* (struct c4iw_dev *) */ 925 struct iw_tunables iwt; 926 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 927 void *ccr_softc; /* (struct ccr_softc *) */ 928 struct l2t_data *l2t; /* L2 table */ 929 struct smt_data *smt; /* Source MAC Table */ 930 struct tid_info tids; 931 vmem_t *key_map; 932 struct tls_tunables tlst; 933 934 uint8_t doorbells; 935 int offload_map; /* port_id's with IFCAP_TOE enabled */ 936 int bt_map; /* tx_chan's with BASE-T */ 937 int active_ulds; /* ULDs activated on this adapter */ 938 int flags; 939 int debug_flags; 940 int error_flags; /* Used by error handler and live reset. */ 941 942 char ifp_lockname[16]; 943 struct mtx ifp_lock; 944 struct ifnet *ifp; /* tracer ifp */ 945 struct ifmedia media; 946 int traceq; /* iq used by all tracers, -1 if none */ 947 int tracer_valid; /* bitmap of valid tracers */ 948 int tracer_enabled; /* bitmap of enabled tracers */ 949 950 char fw_version[16]; 951 char tp_version[16]; 952 char er_version[16]; 953 char bs_version[16]; 954 char cfg_file[32]; 955 u_int cfcsum; 956 struct adapter_params params; 957 const struct chip_params *chip_params; 958 struct t4_virt_res vres; 959 960 uint16_t nbmcaps; 961 uint16_t linkcaps; 962 uint16_t switchcaps; 963 uint16_t niccaps; 964 uint16_t toecaps; 965 uint16_t rdmacaps; 966 uint16_t cryptocaps; 967 uint16_t iscsicaps; 968 uint16_t fcoecaps; 969 970 struct sysctl_ctx_list ctx; 971 struct sysctl_oid *ctrlq_oid; 972 struct sysctl_oid *fwq_oid; 973 974 struct mtx sc_lock; 975 char lockname[16]; 976 977 /* Starving free lists */ 978 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 979 TAILQ_HEAD(, sge_fl) sfl; 980 struct callout sfl_callout; 981 982 /* 983 * Driver code that can run when the adapter is suspended must use this 984 * lock or a synchronized_op and check for HW_OFF_LIMITS before 985 * accessing hardware. 986 * 987 * XXX: could be changed to rwlock. wlock in suspend/resume and for 988 * indirect register access, rlock everywhere else. 989 */ 990 struct mtx reg_lock; 991 992 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 993 994 struct mtx tc_lock; 995 struct task tc_task; 996 997 struct task fatal_error_task; 998 struct task reset_task; 999 const void *reset_thread; 1000 int num_resets; 1001 int incarnation; 1002 1003 const char *last_op; 1004 const void *last_op_thr; 1005 int last_op_flags; 1006 1007 int swintr; 1008 int sensor_resets; 1009 1010 struct callout ktls_tick; 1011 }; 1012 1013 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1014 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1015 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1016 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1017 1018 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1019 KASSERT(IS_BUSY(sc) && \ 1020 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1021 ("%s: operation not synchronized.", __func__)) 1022 1023 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1024 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1025 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1026 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1027 1028 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1029 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1030 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1031 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1032 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1033 1034 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1035 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1036 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1037 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1038 1039 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1040 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1041 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1042 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1043 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1044 1045 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1046 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1047 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1048 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1049 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1050 1051 #define for_each_txq(vi, iter, q) \ 1052 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1053 iter < vi->ntxq; ++iter, ++q) 1054 #define for_each_rxq(vi, iter, q) \ 1055 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1056 iter < vi->nrxq; ++iter, ++q) 1057 #define for_each_ofld_txq(vi, iter, q) \ 1058 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1059 iter < vi->nofldtxq; ++iter, ++q) 1060 #define for_each_ofld_rxq(vi, iter, q) \ 1061 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1062 iter < vi->nofldrxq; ++iter, ++q) 1063 #define for_each_nm_txq(vi, iter, q) \ 1064 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1065 iter < vi->nnmtxq; ++iter, ++q) 1066 #define for_each_nm_rxq(vi, iter, q) \ 1067 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1068 iter < vi->nnmrxq; ++iter, ++q) 1069 #define for_each_vi(_pi, _iter, _vi) \ 1070 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1071 ++(_iter), ++(_vi)) 1072 1073 #define IDXINCR(idx, incr, wrap) do { \ 1074 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1075 } while (0) 1076 #define IDXDIFF(head, tail, wrap) \ 1077 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1078 1079 /* One for errors, one for firmware events */ 1080 #define T4_EXTRA_INTR 2 1081 1082 /* One for firmware events */ 1083 #define T4VF_EXTRA_INTR 1 1084 1085 static inline int 1086 forwarding_intr_to_fwq(struct adapter *sc) 1087 { 1088 1089 return (sc->intr_count == 1); 1090 } 1091 1092 /* Works reliably inside a sync_op or with reg_lock held. */ 1093 static inline bool 1094 hw_off_limits(struct adapter *sc) 1095 { 1096 int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1097 1098 return (__predict_false(off_limits != 0)); 1099 } 1100 1101 static inline uint32_t 1102 t4_read_reg(struct adapter *sc, uint32_t reg) 1103 { 1104 if (hw_off_limits(sc)) 1105 MPASS(curthread == sc->reset_thread); 1106 return bus_space_read_4(sc->bt, sc->bh, reg); 1107 } 1108 1109 static inline void 1110 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1111 { 1112 if (hw_off_limits(sc)) 1113 MPASS(curthread == sc->reset_thread); 1114 bus_space_write_4(sc->bt, sc->bh, reg, val); 1115 } 1116 1117 static inline uint64_t 1118 t4_read_reg64(struct adapter *sc, uint32_t reg) 1119 { 1120 if (hw_off_limits(sc)) 1121 MPASS(curthread == sc->reset_thread); 1122 #ifdef __LP64__ 1123 return bus_space_read_8(sc->bt, sc->bh, reg); 1124 #else 1125 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1126 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1127 1128 #endif 1129 } 1130 1131 static inline void 1132 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1133 { 1134 if (hw_off_limits(sc)) 1135 MPASS(curthread == sc->reset_thread); 1136 #ifdef __LP64__ 1137 bus_space_write_8(sc->bt, sc->bh, reg, val); 1138 #else 1139 bus_space_write_4(sc->bt, sc->bh, reg, val); 1140 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1141 #endif 1142 } 1143 1144 static inline void 1145 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1146 { 1147 if (hw_off_limits(sc)) 1148 MPASS(curthread == sc->reset_thread); 1149 *val = pci_read_config(sc->dev, reg, 1); 1150 } 1151 1152 static inline void 1153 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1154 { 1155 if (hw_off_limits(sc)) 1156 MPASS(curthread == sc->reset_thread); 1157 pci_write_config(sc->dev, reg, val, 1); 1158 } 1159 1160 static inline void 1161 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1162 { 1163 1164 if (hw_off_limits(sc)) 1165 MPASS(curthread == sc->reset_thread); 1166 *val = pci_read_config(sc->dev, reg, 2); 1167 } 1168 1169 static inline void 1170 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1171 { 1172 if (hw_off_limits(sc)) 1173 MPASS(curthread == sc->reset_thread); 1174 pci_write_config(sc->dev, reg, val, 2); 1175 } 1176 1177 static inline void 1178 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1179 { 1180 if (hw_off_limits(sc)) 1181 MPASS(curthread == sc->reset_thread); 1182 *val = pci_read_config(sc->dev, reg, 4); 1183 } 1184 1185 static inline void 1186 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1187 { 1188 if (hw_off_limits(sc)) 1189 MPASS(curthread == sc->reset_thread); 1190 pci_write_config(sc->dev, reg, val, 4); 1191 } 1192 1193 static inline struct port_info * 1194 adap2pinfo(struct adapter *sc, int idx) 1195 { 1196 1197 return (sc->port[idx]); 1198 } 1199 1200 static inline void 1201 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1202 { 1203 1204 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1205 } 1206 1207 static inline int 1208 tx_resume_threshold(struct sge_eq *eq) 1209 { 1210 1211 /* not quite the same as qsize / 4, but this will do. */ 1212 return (eq->sidx / 4); 1213 } 1214 1215 static inline int 1216 t4_use_ldst(struct adapter *sc) 1217 { 1218 1219 #ifdef notyet 1220 return (sc->flags & FW_OK || !sc->use_bd); 1221 #else 1222 return (0); 1223 #endif 1224 } 1225 1226 static inline void 1227 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1228 const char *msg, const __be64 *const p, const bool err) 1229 { 1230 1231 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1232 return; 1233 if (p != NULL) { 1234 log(err ? LOG_ERR : LOG_DEBUG, 1235 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1236 "%016llx %016llx %016llx %016llx\n", 1237 device_get_nameunit(sc->dev), mbox, msg, 1238 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1239 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1240 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1241 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1242 } else { 1243 log(err ? LOG_ERR : LOG_DEBUG, 1244 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1245 "%016llx %016llx %016llx %016llx\n", 1246 device_get_nameunit(sc->dev), mbox, msg, 1247 (long long)t4_read_reg64(sc, reg), 1248 (long long)t4_read_reg64(sc, reg + 8), 1249 (long long)t4_read_reg64(sc, reg + 16), 1250 (long long)t4_read_reg64(sc, reg + 24), 1251 (long long)t4_read_reg64(sc, reg + 32), 1252 (long long)t4_read_reg64(sc, reg + 40), 1253 (long long)t4_read_reg64(sc, reg + 48), 1254 (long long)t4_read_reg64(sc, reg + 56)); 1255 } 1256 } 1257 1258 /* t4_main.c */ 1259 extern int t4_ntxq; 1260 extern int t4_nrxq; 1261 extern int t4_intr_types; 1262 extern int t4_tmr_idx; 1263 extern int t4_pktc_idx; 1264 extern unsigned int t4_qsize_rxq; 1265 extern unsigned int t4_qsize_txq; 1266 extern device_method_t cxgbe_methods[]; 1267 1268 int t4_os_find_pci_capability(struct adapter *, int); 1269 int t4_os_pci_save_state(struct adapter *); 1270 int t4_os_pci_restore_state(struct adapter *); 1271 void t4_os_portmod_changed(struct port_info *); 1272 void t4_os_link_changed(struct port_info *); 1273 void t4_iterate(void (*)(struct adapter *, void *), void *); 1274 void t4_init_devnames(struct adapter *); 1275 void t4_add_adapter(struct adapter *); 1276 int t4_detach_common(device_t); 1277 int t4_map_bars_0_and_4(struct adapter *); 1278 int t4_map_bar_2(struct adapter *); 1279 int t4_setup_intr_handlers(struct adapter *); 1280 void t4_sysctls(struct adapter *); 1281 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1282 void doom_vi(struct adapter *, struct vi_info *); 1283 void end_synchronized_op(struct adapter *, int); 1284 int update_mac_settings(struct ifnet *, int); 1285 int adapter_init(struct adapter *); 1286 int vi_init(struct vi_info *); 1287 void vi_sysctls(struct vi_info *); 1288 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1289 int alloc_atid(struct adapter *, void *); 1290 void *lookup_atid(struct adapter *, int); 1291 void free_atid(struct adapter *, int); 1292 void release_tid(struct adapter *, int, struct sge_wrq *); 1293 int cxgbe_media_change(struct ifnet *); 1294 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1295 void t4_os_cim_err(struct adapter *); 1296 1297 #ifdef KERN_TLS 1298 /* t6_kern_tls.c */ 1299 int t6_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1300 struct m_snd_tag **); 1301 void t6_ktls_modload(void); 1302 void t6_ktls_modunload(void); 1303 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1304 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1305 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1306 #endif 1307 1308 /* t4_keyctx.c */ 1309 struct auth_hash; 1310 union authctx; 1311 #ifdef KERN_TLS 1312 struct ktls_session; 1313 struct tls_key_req; 1314 struct tls_keyctx; 1315 #endif 1316 1317 void t4_aes_getdeckey(void *, const void *, unsigned int); 1318 void t4_copy_partial_hash(int, union authctx *, void *); 1319 void t4_init_gmac_hash(const char *, int, char *); 1320 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1321 char *); 1322 #ifdef KERN_TLS 1323 u_int t4_tls_key_info_size(const struct ktls_session *); 1324 int t4_tls_proto_ver(const struct ktls_session *); 1325 int t4_tls_cipher_mode(const struct ktls_session *); 1326 int t4_tls_auth_mode(const struct ktls_session *); 1327 int t4_tls_hmac_ctrl(const struct ktls_session *); 1328 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1329 int t4_alloc_tls_keyid(struct adapter *); 1330 void t4_free_tls_keyid(struct adapter *, int); 1331 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1332 struct tls_key_req *); 1333 #endif 1334 1335 #ifdef DEV_NETMAP 1336 /* t4_netmap.c */ 1337 struct sge_nm_rxq; 1338 void cxgbe_nm_attach(struct vi_info *); 1339 void cxgbe_nm_detach(struct vi_info *); 1340 void service_nm_rxq(struct sge_nm_rxq *); 1341 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1342 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1343 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1344 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1345 #endif 1346 1347 /* t4_sge.c */ 1348 void t4_sge_modload(void); 1349 void t4_sge_modunload(void); 1350 uint64_t t4_sge_extfree_refs(void); 1351 void t4_tweak_chip_settings(struct adapter *); 1352 int t4_verify_chip_settings(struct adapter *); 1353 void t4_init_rx_buf_info(struct adapter *); 1354 int t4_create_dma_tag(struct adapter *); 1355 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1356 struct sysctl_oid_list *); 1357 int t4_destroy_dma_tag(struct adapter *); 1358 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1359 bus_addr_t *, void **); 1360 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1361 void *); 1362 void free_fl_buffers(struct adapter *, struct sge_fl *); 1363 int t4_setup_adapter_queues(struct adapter *); 1364 int t4_teardown_adapter_queues(struct adapter *); 1365 int t4_setup_vi_queues(struct vi_info *); 1366 int t4_teardown_vi_queues(struct vi_info *); 1367 void t4_intr_all(void *); 1368 void t4_intr(void *); 1369 #ifdef DEV_NETMAP 1370 void t4_nm_intr(void *); 1371 void t4_vi_intr(void *); 1372 #endif 1373 void t4_intr_err(void *); 1374 void t4_intr_evt(void *); 1375 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1376 void t4_update_fl_bufsize(struct ifnet *); 1377 struct mbuf *alloc_wr_mbuf(int, int); 1378 int parse_pkt(struct mbuf **, bool); 1379 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1380 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1381 int tnl_cong(struct port_info *, int); 1382 void t4_register_an_handler(an_handler_t); 1383 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1384 void t4_register_cpl_handler(int, cpl_handler_t); 1385 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1386 #ifdef RATELIMIT 1387 int ethofld_transmit(struct ifnet *, struct mbuf *); 1388 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1389 #endif 1390 1391 /* t4_tracer.c */ 1392 struct t4_tracer; 1393 void t4_tracer_modload(void); 1394 void t4_tracer_modunload(void); 1395 void t4_tracer_port_detach(struct adapter *); 1396 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1397 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1398 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1399 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1400 1401 /* t4_sched.c */ 1402 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1403 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1404 int t4_init_tx_sched(struct adapter *); 1405 int t4_free_tx_sched(struct adapter *); 1406 void t4_update_tx_sched(struct adapter *); 1407 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1408 void t4_release_cl_rl(struct adapter *, int, int); 1409 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1410 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1411 #ifdef RATELIMIT 1412 void t4_init_etid_table(struct adapter *); 1413 void t4_free_etid_table(struct adapter *); 1414 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1415 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1416 struct m_snd_tag **); 1417 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1418 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1419 #endif 1420 1421 /* t4_filter.c */ 1422 int get_filter_mode(struct adapter *, uint32_t *); 1423 int set_filter_mode(struct adapter *, uint32_t); 1424 int set_filter_mask(struct adapter *, uint32_t); 1425 int get_filter(struct adapter *, struct t4_filter *); 1426 int set_filter(struct adapter *, struct t4_filter *); 1427 int del_filter(struct adapter *, struct t4_filter *); 1428 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1429 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1430 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1431 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1432 void free_hftid_hash(struct tid_info *); 1433 1434 static inline struct wrqe * 1435 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1436 { 1437 int len = offsetof(struct wrqe, wr) + wr_len; 1438 struct wrqe *wr; 1439 1440 wr = malloc(len, M_CXGBE, M_NOWAIT); 1441 if (__predict_false(wr == NULL)) 1442 return (NULL); 1443 wr->wr_len = wr_len; 1444 wr->wrq = wrq; 1445 return (wr); 1446 } 1447 1448 static inline void * 1449 wrtod(struct wrqe *wr) 1450 { 1451 return (&wr->wr[0]); 1452 } 1453 1454 static inline void 1455 free_wrqe(struct wrqe *wr) 1456 { 1457 free(wr, M_CXGBE); 1458 } 1459 1460 static inline void 1461 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1462 { 1463 struct sge_wrq *wrq = wr->wrq; 1464 1465 TXQ_LOCK(wrq); 1466 t4_wrq_tx_locked(sc, wrq, wr); 1467 TXQ_UNLOCK(wrq); 1468 } 1469 1470 static inline int 1471 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1472 int len) 1473 { 1474 1475 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1476 } 1477 1478 static inline int 1479 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1480 const uint32_t *val, int len) 1481 { 1482 1483 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1484 } 1485 1486 /* Number of len16 -> number of descriptors */ 1487 static inline int 1488 tx_len16_to_desc(int len16) 1489 { 1490 1491 return (howmany(len16, EQ_ESIZE / 16)); 1492 } 1493 #endif 1494