1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <netinet/in.h> 58 #include <netinet/tcp_lro.h> 59 60 #include "offload.h" 61 #include "t4_ioctl.h" 62 #include "common/t4_msg.h" 63 #include "firmware/t4fw_interface.h" 64 65 #define KTR_CXGBE KTR_SPARE3 66 MALLOC_DECLARE(M_CXGBE); 67 #define CXGBE_UNIMPLEMENTED(s) \ 68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 69 70 #if defined(__i386__) || defined(__amd64__) 71 static __inline void 72 prefetch(void *x) 73 { 74 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 75 } 76 #else 77 #define prefetch(x) __builtin_prefetch(x) 78 #endif 79 80 #ifndef SYSCTL_ADD_UQUAD 81 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 82 #define sysctl_handle_64 sysctl_handle_quad 83 #define CTLTYPE_U64 CTLTYPE_QUAD 84 #endif 85 86 SYSCTL_DECL(_hw_cxgbe); 87 88 struct adapter; 89 typedef struct adapter adapter_t; 90 91 enum { 92 /* 93 * All ingress queues use this entry size. Note that the firmware event 94 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 95 * be at least 64. 96 */ 97 IQ_ESIZE = 64, 98 99 /* Default queue sizes for all kinds of ingress queues */ 100 FW_IQ_QSIZE = 256, 101 RX_IQ_QSIZE = 1024, 102 103 /* All egress queues use this entry size */ 104 EQ_ESIZE = 64, 105 106 /* Default queue sizes for all kinds of egress queues */ 107 CTRL_EQ_QSIZE = 1024, 108 TX_EQ_QSIZE = 1024, 109 110 #if MJUMPAGESIZE != MCLBYTES 111 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 112 #else 113 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 114 #endif 115 CL_METADATA_SIZE = CACHE_LINE_SIZE, 116 117 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 118 TX_SGL_SEGS = 39, 119 TX_SGL_SEGS_TSO = 38, 120 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 122 }; 123 124 enum { 125 /* adapter intr_type */ 126 INTR_INTX = (1 << 0), 127 INTR_MSI = (1 << 1), 128 INTR_MSIX = (1 << 2) 129 }; 130 131 enum { 132 XGMAC_MTU = (1 << 0), 133 XGMAC_PROMISC = (1 << 1), 134 XGMAC_ALLMULTI = (1 << 2), 135 XGMAC_VLANEX = (1 << 3), 136 XGMAC_UCADDR = (1 << 4), 137 XGMAC_MCADDRS = (1 << 5), 138 139 XGMAC_ALL = 0xffff 140 }; 141 142 enum { 143 /* flags understood by begin_synchronized_op */ 144 HOLD_LOCK = (1 << 0), 145 SLEEP_OK = (1 << 1), 146 INTR_OK = (1 << 2), 147 148 /* flags understood by end_synchronized_op */ 149 LOCK_HELD = HOLD_LOCK, 150 }; 151 152 enum { 153 /* adapter flags */ 154 FULL_INIT_DONE = (1 << 0), 155 FW_OK = (1 << 1), 156 CHK_MBOX_ACCESS = (1 << 2), 157 MASTER_PF = (1 << 3), 158 ADAP_SYSCTL_CTX = (1 << 4), 159 ADAP_ERR = (1 << 5), 160 BUF_PACKING_OK = (1 << 6), 161 IS_VF = (1 << 7), 162 KERN_TLS_OK = (1 << 8), 163 164 CXGBE_BUSY = (1 << 9), 165 166 /* port flags */ 167 HAS_TRACEQ = (1 << 3), 168 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 169 170 /* VI flags */ 171 DOOMED = (1 << 0), 172 VI_INIT_DONE = (1 << 1), 173 VI_SYSCTL_CTX = (1 << 2), 174 175 /* adapter debug_flags */ 176 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 177 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 178 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 179 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 180 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 181 }; 182 183 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 184 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 185 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 186 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 187 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 188 189 struct vi_info { 190 device_t dev; 191 struct port_info *pi; 192 193 struct ifnet *ifp; 194 195 unsigned long flags; 196 int if_flags; 197 198 uint16_t *rss, *nm_rss; 199 uint16_t viid; /* opaque VI identifier */ 200 uint16_t smt_idx; 201 uint16_t vin; 202 uint8_t vfvld; 203 int16_t xact_addr_filt;/* index of exact MAC address filter */ 204 uint16_t rss_size; /* size of VI's RSS table slice */ 205 uint16_t rss_base; /* start of VI's RSS table slice */ 206 int hashen; 207 208 int nintr; 209 int first_intr; 210 211 /* These need to be int as they are used in sysctl */ 212 int ntxq; /* # of tx queues */ 213 int first_txq; /* index of first tx queue */ 214 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 215 int nrxq; /* # of rx queues */ 216 int first_rxq; /* index of first rx queue */ 217 int nofldtxq; /* # of offload tx queues */ 218 int first_ofld_txq; /* index of first offload tx queue */ 219 int nofldrxq; /* # of offload rx queues */ 220 int first_ofld_rxq; /* index of first offload rx queue */ 221 int nnmtxq; 222 int first_nm_txq; 223 int nnmrxq; 224 int first_nm_rxq; 225 int tmr_idx; 226 int ofld_tmr_idx; 227 int pktc_idx; 228 int ofld_pktc_idx; 229 int qsize_rxq; 230 int qsize_txq; 231 232 struct timeval last_refreshed; 233 struct fw_vi_stats_vf stats; 234 235 struct callout tick; 236 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 237 238 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 239 }; 240 241 struct tx_ch_rl_params { 242 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 243 uint32_t maxrate; 244 }; 245 246 enum { 247 CLRL_USER = (1 << 0), /* allocated manually. */ 248 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 249 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 250 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 251 }; 252 253 struct tx_cl_rl_params { 254 int refcount; 255 uint8_t flags; 256 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 257 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 258 enum fw_sched_params_mode mode; /* aggr or per-flow */ 259 uint32_t maxrate; 260 uint16_t pktsize; 261 uint16_t burstsize; 262 }; 263 264 /* Tx scheduler parameters for a channel/port */ 265 struct tx_sched_params { 266 /* Channel Rate Limiter */ 267 struct tx_ch_rl_params ch_rl; 268 269 /* Class WRR */ 270 /* XXX */ 271 272 /* Class Rate Limiter (including the default pktsize and burstsize). */ 273 int pktsize; 274 int burstsize; 275 struct tx_cl_rl_params cl_rl[]; 276 }; 277 278 struct port_info { 279 device_t dev; 280 struct adapter *adapter; 281 282 struct vi_info *vi; 283 int nvi; 284 int up_vis; 285 int uld_vis; 286 287 struct tx_sched_params *sched_params; 288 289 struct mtx pi_lock; 290 char lockname[16]; 291 unsigned long flags; 292 293 uint8_t lport; /* associated offload logical port */ 294 int8_t mdio_addr; 295 uint8_t port_type; 296 uint8_t mod_type; 297 uint8_t port_id; 298 uint8_t tx_chan; 299 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 300 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 301 302 struct link_config link_cfg; 303 struct ifmedia media; 304 305 struct timeval last_refreshed; 306 struct port_stats stats; 307 u_int tnl_cong_drops; 308 u_int tx_parse_error; 309 u_long tx_tls_records; 310 u_long tx_tls_octets; 311 u_long rx_tls_records; 312 u_long rx_tls_octets; 313 314 struct callout tick; 315 }; 316 317 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 318 319 /* Where the cluster came from, how it has been carved up. */ 320 struct cluster_layout { 321 int8_t zidx; 322 int8_t hwidx; 323 uint16_t region1; /* mbufs laid out within this region */ 324 /* region2 is the DMA region */ 325 uint16_t region3; /* cluster_metadata within this region */ 326 }; 327 328 struct cluster_metadata { 329 u_int refcount; 330 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 331 }; 332 333 struct fl_sdesc { 334 caddr_t cl; 335 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 336 struct cluster_layout cll; 337 }; 338 339 struct tx_desc { 340 __be64 flit[8]; 341 }; 342 343 struct tx_sdesc { 344 struct mbuf *m; /* m_nextpkt linked chain of frames */ 345 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 346 }; 347 348 349 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 350 struct iq_desc { 351 struct rss_header rss; 352 uint8_t cpl[IQ_PAD]; 353 struct rsp_ctrl rsp; 354 }; 355 #undef IQ_PAD 356 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 357 358 enum { 359 /* iq flags */ 360 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 361 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 362 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 363 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 364 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 365 366 /* iq state */ 367 IQS_DISABLED = 0, 368 IQS_BUSY = 1, 369 IQS_IDLE = 2, 370 371 /* netmap related flags */ 372 NM_OFF = 0, 373 NM_ON = 1, 374 NM_BUSY = 2, 375 }; 376 377 enum { 378 CPL_COOKIE_RESERVED = 0, 379 CPL_COOKIE_FILTER, 380 CPL_COOKIE_DDP0, 381 CPL_COOKIE_DDP1, 382 CPL_COOKIE_TOM, 383 CPL_COOKIE_HASHFILTER, 384 CPL_COOKIE_ETHOFLD, 385 CPL_COOKIE_KERN_TLS, 386 387 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 388 }; 389 390 struct sge_iq; 391 struct rss_header; 392 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 393 struct mbuf *); 394 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 395 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 396 397 /* 398 * Ingress Queue: T4 is producer, driver is consumer. 399 */ 400 struct sge_iq { 401 uint32_t flags; 402 volatile int state; 403 struct adapter *adapter; 404 struct iq_desc *desc; /* KVA of descriptor ring */ 405 int8_t intr_pktc_idx; /* packet count threshold index */ 406 uint8_t gen; /* generation bit */ 407 uint8_t intr_params; /* interrupt holdoff parameters */ 408 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 409 uint16_t qsize; /* size (# of entries) of the queue */ 410 uint16_t sidx; /* index of the entry with the status page */ 411 uint16_t cidx; /* consumer index */ 412 uint16_t cntxt_id; /* SGE context id for the iq */ 413 uint16_t abs_id; /* absolute SGE id for the iq */ 414 415 STAILQ_ENTRY(sge_iq) link; 416 417 bus_dma_tag_t desc_tag; 418 bus_dmamap_t desc_map; 419 bus_addr_t ba; /* bus address of descriptor ring */ 420 }; 421 422 enum { 423 EQ_CTRL = 1, 424 EQ_ETH = 2, 425 EQ_OFLD = 3, 426 427 /* eq flags */ 428 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 429 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 430 EQ_ENABLED = (1 << 3), /* open for business */ 431 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 432 }; 433 434 /* Listed in order of preference. Update t4_sysctls too if you change these */ 435 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 436 437 /* 438 * Egress Queue: driver is producer, T4 is consumer. 439 * 440 * Note: A free list is an egress queue (driver produces the buffers and T4 441 * consumes them) but it's special enough to have its own struct (see sge_fl). 442 */ 443 struct sge_eq { 444 unsigned int flags; /* MUST be first */ 445 unsigned int cntxt_id; /* SGE context id for the eq */ 446 unsigned int abs_id; /* absolute SGE id for the eq */ 447 struct mtx eq_lock; 448 449 struct tx_desc *desc; /* KVA of descriptor ring */ 450 uint8_t doorbells; 451 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 452 u_int udb_qid; /* relative qid within the doorbell page */ 453 uint16_t sidx; /* index of the entry with the status page */ 454 uint16_t cidx; /* consumer idx (desc idx) */ 455 uint16_t pidx; /* producer idx (desc idx) */ 456 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 457 uint16_t dbidx; /* pidx of the most recent doorbell */ 458 uint16_t iqid; /* iq that gets egr_update for the eq */ 459 uint8_t tx_chan; /* tx channel used by the eq */ 460 volatile u_int equiq; /* EQUIQ outstanding */ 461 462 bus_dma_tag_t desc_tag; 463 bus_dmamap_t desc_map; 464 bus_addr_t ba; /* bus address of descriptor ring */ 465 char lockname[16]; 466 }; 467 468 struct sw_zone_info { 469 uma_zone_t zone; /* zone that this cluster comes from */ 470 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 471 int type; /* EXT_xxx type of the cluster */ 472 int8_t head_hwidx; 473 int8_t tail_hwidx; 474 }; 475 476 struct hw_buf_info { 477 int8_t zidx; /* backpointer to zone; -ve means unused */ 478 int8_t next; /* next hwidx for this zone; -1 means no more */ 479 int size; 480 }; 481 482 enum { 483 NUM_MEMWIN = 3, 484 485 MEMWIN0_APERTURE = 2048, 486 MEMWIN0_BASE = 0x1b800, 487 488 MEMWIN1_APERTURE = 32768, 489 MEMWIN1_BASE = 0x28000, 490 491 MEMWIN2_APERTURE_T4 = 65536, 492 MEMWIN2_BASE_T4 = 0x30000, 493 494 MEMWIN2_APERTURE_T5 = 128 * 1024, 495 MEMWIN2_BASE_T5 = 0x60000, 496 }; 497 498 struct memwin { 499 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 500 uint32_t mw_base; /* constant after setup_memwin */ 501 uint32_t mw_aperture; /* ditto */ 502 uint32_t mw_curpos; /* protected by mw_lock */ 503 }; 504 505 enum { 506 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 507 FL_DOOMED = (1 << 1), /* about to be destroyed */ 508 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 509 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 510 }; 511 512 #define FL_RUNNING_LOW(fl) \ 513 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 514 #define FL_NOT_RUNNING_LOW(fl) \ 515 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 516 517 struct sge_fl { 518 struct mtx fl_lock; 519 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 520 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 521 struct cluster_layout cll_def; /* default refill zone, layout */ 522 uint16_t lowat; /* # of buffers <= this means fl needs help */ 523 int flags; 524 uint16_t buf_boundary; 525 526 /* The 16b idx all deal with hw descriptors */ 527 uint16_t dbidx; /* hw pidx after last doorbell */ 528 uint16_t sidx; /* index of status page */ 529 volatile uint16_t hw_cidx; 530 531 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 532 uint32_t cidx; /* consumer index */ 533 uint32_t pidx; /* producer index */ 534 535 uint32_t dbval; 536 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 537 volatile uint32_t *udb; 538 539 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 540 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 541 uint64_t cl_allocated; /* # of clusters allocated */ 542 uint64_t cl_recycled; /* # of clusters recycled */ 543 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 544 545 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 546 struct mbuf *m0; 547 struct mbuf **pnext; 548 u_int remaining; 549 550 uint16_t qsize; /* # of hw descriptors (status page included) */ 551 uint16_t cntxt_id; /* SGE context id for the freelist */ 552 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 553 bus_dma_tag_t desc_tag; 554 bus_dmamap_t desc_map; 555 char lockname[16]; 556 bus_addr_t ba; /* bus address of descriptor ring */ 557 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 558 }; 559 560 struct mp_ring; 561 562 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 563 struct sge_txq { 564 struct sge_eq eq; /* MUST be first */ 565 566 struct ifnet *ifp; /* the interface this txq belongs to */ 567 struct mp_ring *r; /* tx software ring */ 568 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 569 struct sglist *gl; 570 __be32 cpl_ctrl0; /* for convenience */ 571 int tc_idx; /* traffic class */ 572 573 struct task tx_reclaim_task; 574 /* stats for common events first */ 575 576 uint64_t txcsum; /* # of times hardware assisted with checksum */ 577 uint64_t tso_wrs; /* # of TSO work requests */ 578 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 579 uint64_t imm_wrs; /* # of work requests with immediate data */ 580 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 581 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 582 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 583 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 584 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 585 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 586 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 587 uint64_t tls_wrs; /* # of TLS work requests */ 588 589 uint64_t kern_tls_records; 590 uint64_t kern_tls_short; 591 uint64_t kern_tls_partial; 592 uint64_t kern_tls_full; 593 uint64_t kern_tls_octets; 594 uint64_t kern_tls_waste; 595 uint64_t kern_tls_options; 596 uint64_t kern_tls_header; 597 uint64_t kern_tls_fin; 598 uint64_t kern_tls_fin_short; 599 uint64_t kern_tls_cbc; 600 uint64_t kern_tls_gcm; 601 602 /* stats for not-that-common events */ 603 604 /* Optional scratch space for constructing work requests. */ 605 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 606 } __aligned(CACHE_LINE_SIZE); 607 608 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 609 struct sge_rxq { 610 struct sge_iq iq; /* MUST be first */ 611 struct sge_fl fl; /* MUST follow iq */ 612 613 struct ifnet *ifp; /* the interface this rxq belongs to */ 614 #if defined(INET) || defined(INET6) 615 struct lro_ctrl lro; /* LRO state */ 616 #endif 617 618 /* stats for common events first */ 619 620 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 621 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 622 623 /* stats for not-that-common events */ 624 625 } __aligned(CACHE_LINE_SIZE); 626 627 static inline struct sge_rxq * 628 iq_to_rxq(struct sge_iq *iq) 629 { 630 631 return (__containerof(iq, struct sge_rxq, iq)); 632 } 633 634 635 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 636 struct sge_ofld_rxq { 637 struct sge_iq iq; /* MUST be first */ 638 struct sge_fl fl; /* MUST follow iq */ 639 } __aligned(CACHE_LINE_SIZE); 640 641 static inline struct sge_ofld_rxq * 642 iq_to_ofld_rxq(struct sge_iq *iq) 643 { 644 645 return (__containerof(iq, struct sge_ofld_rxq, iq)); 646 } 647 648 struct wrqe { 649 STAILQ_ENTRY(wrqe) link; 650 struct sge_wrq *wrq; 651 int wr_len; 652 char wr[] __aligned(16); 653 }; 654 655 struct wrq_cookie { 656 TAILQ_ENTRY(wrq_cookie) link; 657 int ndesc; 658 int pidx; 659 }; 660 661 /* 662 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 663 * and offload tx queues are of this type. 664 */ 665 struct sge_wrq { 666 struct sge_eq eq; /* MUST be first */ 667 668 struct adapter *adapter; 669 struct task wrq_tx_task; 670 671 /* Tx desc reserved but WR not "committed" yet. */ 672 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 673 674 /* List of WRs ready to go out as soon as descriptors are available. */ 675 STAILQ_HEAD(, wrqe) wr_list; 676 u_int nwr_pending; 677 u_int ndesc_needed; 678 679 /* stats for common events first */ 680 681 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 682 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 683 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 684 685 /* stats for not-that-common events */ 686 687 /* 688 * Scratch space for work requests that wrap around after reaching the 689 * status page, and some information about the last WR that used it. 690 */ 691 uint16_t ss_pidx; 692 uint16_t ss_len; 693 uint8_t ss[SGE_MAX_WR_LEN]; 694 695 } __aligned(CACHE_LINE_SIZE); 696 697 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 698 struct sge_nm_rxq { 699 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 700 struct vi_info *vi; 701 702 struct iq_desc *iq_desc; 703 uint16_t iq_abs_id; 704 uint16_t iq_cntxt_id; 705 uint16_t iq_cidx; 706 uint16_t iq_sidx; 707 uint8_t iq_gen; 708 709 __be64 *fl_desc; 710 uint16_t fl_cntxt_id; 711 uint32_t fl_cidx; 712 uint32_t fl_pidx; 713 uint32_t fl_sidx; 714 uint32_t fl_db_val; 715 u_int fl_hwidx:4; 716 717 u_int fl_db_saved; 718 u_int nid; /* netmap ring # for this queue */ 719 720 /* infrequently used items after this */ 721 722 bus_dma_tag_t iq_desc_tag; 723 bus_dmamap_t iq_desc_map; 724 bus_addr_t iq_ba; 725 int intr_idx; 726 727 bus_dma_tag_t fl_desc_tag; 728 bus_dmamap_t fl_desc_map; 729 bus_addr_t fl_ba; 730 } __aligned(CACHE_LINE_SIZE); 731 732 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 733 struct sge_nm_txq { 734 struct tx_desc *desc; 735 uint16_t cidx; 736 uint16_t pidx; 737 uint16_t sidx; 738 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 739 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 740 uint16_t dbidx; /* pidx of the most recent doorbell */ 741 uint8_t doorbells; 742 volatile uint32_t *udb; 743 u_int udb_qid; 744 u_int cntxt_id; 745 __be32 cpl_ctrl0; /* for convenience */ 746 u_int nid; /* netmap ring # for this queue */ 747 748 /* infrequently used items after this */ 749 750 bus_dma_tag_t desc_tag; 751 bus_dmamap_t desc_map; 752 bus_addr_t ba; 753 int iqidx; 754 } __aligned(CACHE_LINE_SIZE); 755 756 struct sge { 757 int nrxq; /* total # of Ethernet rx queues */ 758 int ntxq; /* total # of Ethernet tx queues */ 759 int nofldrxq; /* total # of TOE rx queues */ 760 int nofldtxq; /* total # of TOE tx queues */ 761 int nnmrxq; /* total # of netmap rx queues */ 762 int nnmtxq; /* total # of netmap tx queues */ 763 int niq; /* total # of ingress queues */ 764 int neq; /* total # of egress queues */ 765 766 struct sge_iq fwq; /* Firmware event queue */ 767 struct sge_wrq *ctrlq; /* Control queues */ 768 struct sge_txq *txq; /* NIC tx queues */ 769 struct sge_rxq *rxq; /* NIC rx queues */ 770 struct sge_wrq *ofld_txq; /* TOE tx queues */ 771 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 772 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 773 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 774 775 uint16_t iq_start; /* first cntxt_id */ 776 uint16_t iq_base; /* first abs_id */ 777 int eq_start; /* first cntxt_id */ 778 int eq_base; /* first abs_id */ 779 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 780 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 781 782 int8_t safe_hwidx1; /* may not have room for metadata */ 783 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 784 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 785 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 786 }; 787 788 struct devnames { 789 const char *nexus_name; 790 const char *ifnet_name; 791 const char *vi_ifnet_name; 792 const char *pf03_drv_name; 793 const char *vf_nexus_name; 794 const char *vf_ifnet_name; 795 }; 796 797 struct clip_entry; 798 799 struct adapter { 800 SLIST_ENTRY(adapter) link; 801 device_t dev; 802 struct cdev *cdev; 803 const struct devnames *names; 804 805 /* PCIe register resources */ 806 int regs_rid; 807 struct resource *regs_res; 808 int msix_rid; 809 struct resource *msix_res; 810 bus_space_handle_t bh; 811 bus_space_tag_t bt; 812 bus_size_t mmio_len; 813 int udbs_rid; 814 struct resource *udbs_res; 815 volatile uint8_t *udbs_base; 816 817 unsigned int pf; 818 unsigned int mbox; 819 unsigned int vpd_busy; 820 unsigned int vpd_flag; 821 822 /* Interrupt information */ 823 int intr_type; 824 int intr_count; 825 struct irq { 826 struct resource *res; 827 int rid; 828 void *tag; 829 struct sge_rxq *rxq; 830 struct sge_nm_rxq *nm_rxq; 831 } __aligned(CACHE_LINE_SIZE) *irq; 832 int sge_gts_reg; 833 int sge_kdoorbell_reg; 834 835 bus_dma_tag_t dmat; /* Parent DMA tag */ 836 837 struct sge sge; 838 int lro_timeout; 839 int sc_do_rxcopy; 840 841 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 842 struct port_info *port[MAX_NPORTS]; 843 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 844 845 struct mtx clip_table_lock; 846 TAILQ_HEAD(, clip_entry) clip_table; 847 int clip_gen; 848 849 void *tom_softc; /* (struct tom_data *) */ 850 struct tom_tunables tt; 851 struct t4_offload_policy *policy; 852 struct rwlock policy_lock; 853 854 void *iwarp_softc; /* (struct c4iw_dev *) */ 855 struct iw_tunables iwt; 856 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 857 void *ccr_softc; /* (struct ccr_softc *) */ 858 struct l2t_data *l2t; /* L2 table */ 859 struct smt_data *smt; /* Source MAC Table */ 860 struct tid_info tids; 861 vmem_t *key_map; 862 struct tls_tunables tlst; 863 864 uint8_t doorbells; 865 int offload_map; /* ports with IFCAP_TOE enabled */ 866 int active_ulds; /* ULDs activated on this adapter */ 867 int flags; 868 int debug_flags; 869 870 char ifp_lockname[16]; 871 struct mtx ifp_lock; 872 struct ifnet *ifp; /* tracer ifp */ 873 struct ifmedia media; 874 int traceq; /* iq used by all tracers, -1 if none */ 875 int tracer_valid; /* bitmap of valid tracers */ 876 int tracer_enabled; /* bitmap of enabled tracers */ 877 878 char fw_version[16]; 879 char tp_version[16]; 880 char er_version[16]; 881 char bs_version[16]; 882 char cfg_file[32]; 883 u_int cfcsum; 884 struct adapter_params params; 885 const struct chip_params *chip_params; 886 struct t4_virt_res vres; 887 888 uint16_t nbmcaps; 889 uint16_t linkcaps; 890 uint16_t switchcaps; 891 uint16_t niccaps; 892 uint16_t toecaps; 893 uint16_t rdmacaps; 894 uint16_t cryptocaps; 895 uint16_t iscsicaps; 896 uint16_t fcoecaps; 897 898 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 899 900 struct mtx sc_lock; 901 char lockname[16]; 902 903 /* Starving free lists */ 904 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 905 TAILQ_HEAD(, sge_fl) sfl; 906 struct callout sfl_callout; 907 908 struct mtx reg_lock; /* for indirect register access */ 909 910 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 911 912 struct mtx tc_lock; 913 struct task tc_task; 914 915 const char *last_op; 916 const void *last_op_thr; 917 int last_op_flags; 918 919 int swintr; 920 int sensor_resets; 921 922 struct callout ktls_tick; 923 }; 924 925 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 926 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 927 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 928 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 929 930 #define ASSERT_SYNCHRONIZED_OP(sc) \ 931 KASSERT(IS_BUSY(sc) && \ 932 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 933 ("%s: operation not synchronized.", __func__)) 934 935 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 936 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 937 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 938 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 939 940 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 941 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 942 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 943 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 944 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 945 946 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 947 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 948 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 949 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 950 951 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 952 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 953 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 954 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 955 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 956 957 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 958 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 959 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 960 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 961 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 962 963 #define for_each_txq(vi, iter, q) \ 964 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 965 iter < vi->ntxq; ++iter, ++q) 966 #define for_each_rxq(vi, iter, q) \ 967 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 968 iter < vi->nrxq; ++iter, ++q) 969 #define for_each_ofld_txq(vi, iter, q) \ 970 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 971 iter < vi->nofldtxq; ++iter, ++q) 972 #define for_each_ofld_rxq(vi, iter, q) \ 973 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 974 iter < vi->nofldrxq; ++iter, ++q) 975 #define for_each_nm_txq(vi, iter, q) \ 976 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 977 iter < vi->nnmtxq; ++iter, ++q) 978 #define for_each_nm_rxq(vi, iter, q) \ 979 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 980 iter < vi->nnmrxq; ++iter, ++q) 981 #define for_each_vi(_pi, _iter, _vi) \ 982 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 983 ++(_iter), ++(_vi)) 984 985 #define IDXINCR(idx, incr, wrap) do { \ 986 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 987 } while (0) 988 #define IDXDIFF(head, tail, wrap) \ 989 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 990 991 /* One for errors, one for firmware events */ 992 #define T4_EXTRA_INTR 2 993 994 /* One for firmware events */ 995 #define T4VF_EXTRA_INTR 1 996 997 static inline int 998 forwarding_intr_to_fwq(struct adapter *sc) 999 { 1000 1001 return (sc->intr_count == 1); 1002 } 1003 1004 static inline uint32_t 1005 t4_read_reg(struct adapter *sc, uint32_t reg) 1006 { 1007 1008 return bus_space_read_4(sc->bt, sc->bh, reg); 1009 } 1010 1011 static inline void 1012 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1013 { 1014 1015 bus_space_write_4(sc->bt, sc->bh, reg, val); 1016 } 1017 1018 static inline uint64_t 1019 t4_read_reg64(struct adapter *sc, uint32_t reg) 1020 { 1021 1022 #ifdef __LP64__ 1023 return bus_space_read_8(sc->bt, sc->bh, reg); 1024 #else 1025 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1026 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1027 1028 #endif 1029 } 1030 1031 static inline void 1032 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1033 { 1034 1035 #ifdef __LP64__ 1036 bus_space_write_8(sc->bt, sc->bh, reg, val); 1037 #else 1038 bus_space_write_4(sc->bt, sc->bh, reg, val); 1039 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1040 #endif 1041 } 1042 1043 static inline void 1044 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1045 { 1046 1047 *val = pci_read_config(sc->dev, reg, 1); 1048 } 1049 1050 static inline void 1051 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1052 { 1053 1054 pci_write_config(sc->dev, reg, val, 1); 1055 } 1056 1057 static inline void 1058 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1059 { 1060 1061 *val = pci_read_config(sc->dev, reg, 2); 1062 } 1063 1064 static inline void 1065 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1066 { 1067 1068 pci_write_config(sc->dev, reg, val, 2); 1069 } 1070 1071 static inline void 1072 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1073 { 1074 1075 *val = pci_read_config(sc->dev, reg, 4); 1076 } 1077 1078 static inline void 1079 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1080 { 1081 1082 pci_write_config(sc->dev, reg, val, 4); 1083 } 1084 1085 static inline struct port_info * 1086 adap2pinfo(struct adapter *sc, int idx) 1087 { 1088 1089 return (sc->port[idx]); 1090 } 1091 1092 static inline void 1093 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1094 { 1095 1096 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1097 } 1098 1099 static inline int 1100 tx_resume_threshold(struct sge_eq *eq) 1101 { 1102 1103 /* not quite the same as qsize / 4, but this will do. */ 1104 return (eq->sidx / 4); 1105 } 1106 1107 static inline int 1108 t4_use_ldst(struct adapter *sc) 1109 { 1110 1111 #ifdef notyet 1112 return (sc->flags & FW_OK || !sc->use_bd); 1113 #else 1114 return (0); 1115 #endif 1116 } 1117 1118 static inline void 1119 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1120 const char *msg, const __be64 *const p, const bool err) 1121 { 1122 1123 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1124 return; 1125 if (p != NULL) { 1126 log(err ? LOG_ERR : LOG_DEBUG, 1127 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1128 "%016llx %016llx %016llx %016llx\n", 1129 device_get_nameunit(sc->dev), mbox, msg, 1130 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1131 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1132 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1133 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1134 } else { 1135 log(err ? LOG_ERR : LOG_DEBUG, 1136 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1137 "%016llx %016llx %016llx %016llx\n", 1138 device_get_nameunit(sc->dev), mbox, msg, 1139 (long long)t4_read_reg64(sc, reg), 1140 (long long)t4_read_reg64(sc, reg + 8), 1141 (long long)t4_read_reg64(sc, reg + 16), 1142 (long long)t4_read_reg64(sc, reg + 24), 1143 (long long)t4_read_reg64(sc, reg + 32), 1144 (long long)t4_read_reg64(sc, reg + 40), 1145 (long long)t4_read_reg64(sc, reg + 48), 1146 (long long)t4_read_reg64(sc, reg + 56)); 1147 } 1148 } 1149 1150 /* t4_main.c */ 1151 extern int t4_ntxq; 1152 extern int t4_nrxq; 1153 extern int t4_intr_types; 1154 extern int t4_tmr_idx; 1155 extern int t4_pktc_idx; 1156 extern unsigned int t4_qsize_rxq; 1157 extern unsigned int t4_qsize_txq; 1158 extern device_method_t cxgbe_methods[]; 1159 1160 int t4_os_find_pci_capability(struct adapter *, int); 1161 int t4_os_pci_save_state(struct adapter *); 1162 int t4_os_pci_restore_state(struct adapter *); 1163 void t4_os_portmod_changed(struct port_info *); 1164 void t4_os_link_changed(struct port_info *); 1165 void t4_iterate(void (*)(struct adapter *, void *), void *); 1166 void t4_init_devnames(struct adapter *); 1167 void t4_add_adapter(struct adapter *); 1168 int t4_detach_common(device_t); 1169 int t4_map_bars_0_and_4(struct adapter *); 1170 int t4_map_bar_2(struct adapter *); 1171 int t4_setup_intr_handlers(struct adapter *); 1172 void t4_sysctls(struct adapter *); 1173 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1174 void doom_vi(struct adapter *, struct vi_info *); 1175 void end_synchronized_op(struct adapter *, int); 1176 int update_mac_settings(struct ifnet *, int); 1177 int adapter_full_init(struct adapter *); 1178 int adapter_full_uninit(struct adapter *); 1179 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1180 void cxgbe_snd_tag_init(struct cxgbe_snd_tag *, struct ifnet *, int); 1181 int vi_full_init(struct vi_info *); 1182 int vi_full_uninit(struct vi_info *); 1183 void vi_sysctls(struct vi_info *); 1184 void vi_tick(void *); 1185 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1186 int alloc_atid(struct adapter *, void *); 1187 void *lookup_atid(struct adapter *, int); 1188 void free_atid(struct adapter *, int); 1189 void release_tid(struct adapter *, int, struct sge_wrq *); 1190 int cxgbe_media_change(struct ifnet *); 1191 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1192 bool t4_os_dump_cimla(struct adapter *, int, bool); 1193 void t4_os_dump_devlog(struct adapter *); 1194 1195 #ifdef KERN_TLS 1196 /* t4_kern_tls.c */ 1197 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1198 struct m_snd_tag **); 1199 void cxgbe_tls_tag_free(struct m_snd_tag *); 1200 void t6_ktls_modload(void); 1201 void t6_ktls_modunload(void); 1202 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1203 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1204 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1205 #endif 1206 1207 /* t4_keyctx.c */ 1208 struct auth_hash; 1209 union authctx; 1210 1211 void t4_aes_getdeckey(void *, const void *, unsigned int); 1212 void t4_copy_partial_hash(int, union authctx *, void *); 1213 void t4_init_gmac_hash(const char *, int, char *); 1214 void t4_init_hmac_digest(struct auth_hash *, u_int, char *, int, char *); 1215 1216 #ifdef DEV_NETMAP 1217 /* t4_netmap.c */ 1218 struct sge_nm_rxq; 1219 void cxgbe_nm_attach(struct vi_info *); 1220 void cxgbe_nm_detach(struct vi_info *); 1221 void service_nm_rxq(struct sge_nm_rxq *); 1222 #endif 1223 1224 /* t4_sge.c */ 1225 void t4_sge_modload(void); 1226 void t4_sge_modunload(void); 1227 uint64_t t4_sge_extfree_refs(void); 1228 void t4_tweak_chip_settings(struct adapter *); 1229 int t4_read_chip_settings(struct adapter *); 1230 int t4_create_dma_tag(struct adapter *); 1231 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1232 struct sysctl_oid_list *); 1233 int t4_destroy_dma_tag(struct adapter *); 1234 int t4_setup_adapter_queues(struct adapter *); 1235 int t4_teardown_adapter_queues(struct adapter *); 1236 int t4_setup_vi_queues(struct vi_info *); 1237 int t4_teardown_vi_queues(struct vi_info *); 1238 void t4_intr_all(void *); 1239 void t4_intr(void *); 1240 #ifdef DEV_NETMAP 1241 void t4_nm_intr(void *); 1242 void t4_vi_intr(void *); 1243 #endif 1244 void t4_intr_err(void *); 1245 void t4_intr_evt(void *); 1246 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1247 void t4_update_fl_bufsize(struct ifnet *); 1248 struct mbuf *alloc_wr_mbuf(int, int); 1249 int parse_pkt(struct adapter *, struct mbuf **); 1250 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1251 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1252 int tnl_cong(struct port_info *, int); 1253 void t4_register_an_handler(an_handler_t); 1254 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1255 void t4_register_cpl_handler(int, cpl_handler_t); 1256 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1257 #ifdef RATELIMIT 1258 int ethofld_transmit(struct ifnet *, struct mbuf *); 1259 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1260 #endif 1261 1262 /* t4_tracer.c */ 1263 struct t4_tracer; 1264 void t4_tracer_modload(void); 1265 void t4_tracer_modunload(void); 1266 void t4_tracer_port_detach(struct adapter *); 1267 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1268 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1269 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1270 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1271 1272 /* t4_sched.c */ 1273 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1274 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1275 int t4_init_tx_sched(struct adapter *); 1276 int t4_free_tx_sched(struct adapter *); 1277 void t4_update_tx_sched(struct adapter *); 1278 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1279 void t4_release_cl_rl(struct adapter *, int, int); 1280 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1281 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1282 #ifdef RATELIMIT 1283 void t4_init_etid_table(struct adapter *); 1284 void t4_free_etid_table(struct adapter *); 1285 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1286 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1287 struct m_snd_tag **); 1288 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1289 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1290 void cxgbe_rate_tag_free(struct m_snd_tag *); 1291 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1292 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1293 #endif 1294 1295 /* t4_filter.c */ 1296 int get_filter_mode(struct adapter *, uint32_t *); 1297 int set_filter_mode(struct adapter *, uint32_t); 1298 int get_filter(struct adapter *, struct t4_filter *); 1299 int set_filter(struct adapter *, struct t4_filter *); 1300 int del_filter(struct adapter *, struct t4_filter *); 1301 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1302 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1303 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1304 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1305 void free_hftid_hash(struct tid_info *); 1306 1307 static inline struct wrqe * 1308 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1309 { 1310 int len = offsetof(struct wrqe, wr) + wr_len; 1311 struct wrqe *wr; 1312 1313 wr = malloc(len, M_CXGBE, M_NOWAIT); 1314 if (__predict_false(wr == NULL)) 1315 return (NULL); 1316 wr->wr_len = wr_len; 1317 wr->wrq = wrq; 1318 return (wr); 1319 } 1320 1321 static inline void * 1322 wrtod(struct wrqe *wr) 1323 { 1324 return (&wr->wr[0]); 1325 } 1326 1327 static inline void 1328 free_wrqe(struct wrqe *wr) 1329 { 1330 free(wr, M_CXGBE); 1331 } 1332 1333 static inline void 1334 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1335 { 1336 struct sge_wrq *wrq = wr->wrq; 1337 1338 TXQ_LOCK(wrq); 1339 t4_wrq_tx_locked(sc, wrq, wr); 1340 TXQ_UNLOCK(wrq); 1341 } 1342 1343 static inline int 1344 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1345 int len) 1346 { 1347 1348 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1349 } 1350 1351 static inline int 1352 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1353 const uint32_t *val, int len) 1354 { 1355 1356 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1357 } 1358 #endif 1359