1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 #define KTR_CXGBE KTR_SPARE3 61 MALLOC_DECLARE(M_CXGBE); 62 #define CXGBE_UNIMPLEMENTED(s) \ 63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 64 65 #if defined(__i386__) || defined(__amd64__) 66 static __inline void 67 prefetch(void *x) 68 { 69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 70 } 71 #else 72 #define prefetch(x) 73 #endif 74 75 #ifndef SYSCTL_ADD_UQUAD 76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 77 #define sysctl_handle_64 sysctl_handle_quad 78 #define CTLTYPE_U64 CTLTYPE_QUAD 79 #endif 80 81 #if (__FreeBSD_version >= 900030) || \ 82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 83 #define SBUF_DRAIN 1 84 #endif 85 86 #ifdef __amd64__ 87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 KASSERT(tag == X86_BUS_SPACE_MEM, 93 ("%s: can only handle mem space", __func__)); 94 95 return (*(volatile uint64_t *)(handle + offset)); 96 } 97 98 static __inline void 99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 100 bus_size_t offset, uint64_t value) 101 { 102 KASSERT(tag == X86_BUS_SPACE_MEM, 103 ("%s: can only handle mem space", __func__)); 104 105 *(volatile uint64_t *)(bsh + offset) = value; 106 } 107 #else 108 static __inline uint64_t 109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 110 bus_size_t offset) 111 { 112 return (uint64_t)bus_space_read_4(tag, handle, offset) + 113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 114 } 115 116 static __inline void 117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 118 bus_size_t offset, uint64_t value) 119 { 120 bus_space_write_4(tag, bsh, offset, value); 121 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 122 } 123 #endif 124 125 struct adapter; 126 typedef struct adapter adapter_t; 127 128 enum { 129 /* 130 * All ingress queues use this entry size. Note that the firmware event 131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 132 * be at least 64. 133 */ 134 IQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of ingress queues */ 137 FW_IQ_QSIZE = 256, 138 RX_IQ_QSIZE = 1024, 139 140 /* All egress queues use this entry size */ 141 EQ_ESIZE = 64, 142 143 /* Default queue sizes for all kinds of egress queues */ 144 CTRL_EQ_QSIZE = 128, 145 TX_EQ_QSIZE = 1024, 146 147 #if MJUMPAGESIZE != MCLBYTES 148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 149 #else 150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 151 #endif 152 CL_METADATA_SIZE = CACHE_LINE_SIZE, 153 154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 155 TX_SGL_SEGS = 39, 156 TX_SGL_SEGS_TSO = 38, 157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 158 }; 159 160 enum { 161 /* adapter intr_type */ 162 INTR_INTX = (1 << 0), 163 INTR_MSI = (1 << 1), 164 INTR_MSIX = (1 << 2) 165 }; 166 167 enum { 168 XGMAC_MTU = (1 << 0), 169 XGMAC_PROMISC = (1 << 1), 170 XGMAC_ALLMULTI = (1 << 2), 171 XGMAC_VLANEX = (1 << 3), 172 XGMAC_UCADDR = (1 << 4), 173 XGMAC_MCADDRS = (1 << 5), 174 175 XGMAC_ALL = 0xffff 176 }; 177 178 enum { 179 /* flags understood by begin_synchronized_op */ 180 HOLD_LOCK = (1 << 0), 181 SLEEP_OK = (1 << 1), 182 INTR_OK = (1 << 2), 183 184 /* flags understood by end_synchronized_op */ 185 LOCK_HELD = HOLD_LOCK, 186 }; 187 188 enum { 189 /* adapter flags */ 190 FULL_INIT_DONE = (1 << 0), 191 FW_OK = (1 << 1), 192 /* INTR_DIRECT = (1 << 2), No longer used. */ 193 MASTER_PF = (1 << 3), 194 ADAP_SYSCTL_CTX = (1 << 4), 195 /* TOM_INIT_DONE= (1 << 5), No longer used */ 196 BUF_PACKING_OK = (1 << 6), 197 198 CXGBE_BUSY = (1 << 9), 199 200 /* port flags */ 201 HAS_TRACEQ = (1 << 3), 202 203 /* VI flags */ 204 DOOMED = (1 << 0), 205 VI_INIT_DONE = (1 << 1), 206 VI_SYSCTL_CTX = (1 << 2), 207 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 208 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 209 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 210 VI_NETMAP = (1 << 6), 211 212 /* adapter debug_flags */ 213 DF_DUMP_MBOX = (1 << 0), 214 }; 215 216 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 217 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 218 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 219 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 220 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 221 222 struct vi_info { 223 device_t dev; 224 struct port_info *pi; 225 226 struct ifnet *ifp; 227 struct ifmedia media; 228 229 unsigned long flags; 230 int if_flags; 231 232 uint16_t *rss; 233 uint16_t viid; 234 int16_t xact_addr_filt;/* index of exact MAC address filter */ 235 uint16_t rss_size; /* size of VI's RSS table slice */ 236 uint16_t rss_base; /* start of VI's RSS table slice */ 237 238 eventhandler_tag vlan_c; 239 240 int nintr; 241 int first_intr; 242 243 /* These need to be int as they are used in sysctl */ 244 int ntxq; /* # of tx queues */ 245 int first_txq; /* index of first tx queue */ 246 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 247 int nrxq; /* # of rx queues */ 248 int first_rxq; /* index of first rx queue */ 249 #ifdef TCP_OFFLOAD 250 int nofldtxq; /* # of offload tx queues */ 251 int first_ofld_txq; /* index of first offload tx queue */ 252 int nofldrxq; /* # of offload rx queues */ 253 int first_ofld_rxq; /* index of first offload rx queue */ 254 #endif 255 int tmr_idx; 256 int pktc_idx; 257 int qsize_rxq; 258 int qsize_txq; 259 260 struct timeval last_refreshed; 261 struct fw_vi_stats_vf stats; 262 263 struct callout tick; 264 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 265 266 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 267 }; 268 269 struct port_info { 270 device_t dev; 271 struct adapter *adapter; 272 273 struct vi_info *vi; 274 int nvi; 275 int up_vis; 276 int uld_vis; 277 278 struct mtx pi_lock; 279 char lockname[16]; 280 unsigned long flags; 281 282 uint8_t lport; /* associated offload logical port */ 283 int8_t mdio_addr; 284 uint8_t port_type; 285 uint8_t mod_type; 286 uint8_t port_id; 287 uint8_t tx_chan; 288 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 289 290 int linkdnrc; 291 struct link_config link_cfg; 292 293 struct timeval last_refreshed; 294 struct port_stats stats; 295 u_int tnl_cong_drops; 296 u_int tx_parse_error; 297 298 struct callout tick; 299 }; 300 301 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 302 303 /* Where the cluster came from, how it has been carved up. */ 304 struct cluster_layout { 305 int8_t zidx; 306 int8_t hwidx; 307 uint16_t region1; /* mbufs laid out within this region */ 308 /* region2 is the DMA region */ 309 uint16_t region3; /* cluster_metadata within this region */ 310 }; 311 312 struct cluster_metadata { 313 u_int refcount; 314 #ifdef INVARIANTS 315 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 316 #endif 317 }; 318 319 struct fl_sdesc { 320 caddr_t cl; 321 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 322 struct cluster_layout cll; 323 }; 324 325 struct tx_desc { 326 __be64 flit[8]; 327 }; 328 329 struct tx_sdesc { 330 struct mbuf *m; /* m_nextpkt linked chain of frames */ 331 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 332 }; 333 334 335 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 336 struct iq_desc { 337 struct rss_header rss; 338 uint8_t cpl[IQ_PAD]; 339 struct rsp_ctrl rsp; 340 }; 341 #undef IQ_PAD 342 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 343 344 enum { 345 /* iq flags */ 346 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 347 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 348 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 349 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 350 351 /* iq state */ 352 IQS_DISABLED = 0, 353 IQS_BUSY = 1, 354 IQS_IDLE = 2, 355 }; 356 357 /* 358 * Ingress Queue: T4 is producer, driver is consumer. 359 */ 360 struct sge_iq { 361 uint32_t flags; 362 volatile int state; 363 struct adapter *adapter; 364 struct iq_desc *desc; /* KVA of descriptor ring */ 365 int8_t intr_pktc_idx; /* packet count threshold index */ 366 uint8_t gen; /* generation bit */ 367 uint8_t intr_params; /* interrupt holdoff parameters */ 368 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 369 uint16_t qsize; /* size (# of entries) of the queue */ 370 uint16_t sidx; /* index of the entry with the status page */ 371 uint16_t cidx; /* consumer index */ 372 uint16_t cntxt_id; /* SGE context id for the iq */ 373 uint16_t abs_id; /* absolute SGE id for the iq */ 374 375 STAILQ_ENTRY(sge_iq) link; 376 377 bus_dma_tag_t desc_tag; 378 bus_dmamap_t desc_map; 379 bus_addr_t ba; /* bus address of descriptor ring */ 380 }; 381 382 enum { 383 EQ_CTRL = 1, 384 EQ_ETH = 2, 385 EQ_OFLD = 3, 386 387 /* eq flags */ 388 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 389 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 390 EQ_ENABLED = (1 << 3), /* open for business */ 391 }; 392 393 /* Listed in order of preference. Update t4_sysctls too if you change these */ 394 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 395 396 /* 397 * Egress Queue: driver is producer, T4 is consumer. 398 * 399 * Note: A free list is an egress queue (driver produces the buffers and T4 400 * consumes them) but it's special enough to have its own struct (see sge_fl). 401 */ 402 struct sge_eq { 403 unsigned int flags; /* MUST be first */ 404 unsigned int cntxt_id; /* SGE context id for the eq */ 405 struct mtx eq_lock; 406 407 struct tx_desc *desc; /* KVA of descriptor ring */ 408 uint16_t doorbells; 409 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 410 u_int udb_qid; /* relative qid within the doorbell page */ 411 uint16_t sidx; /* index of the entry with the status page */ 412 uint16_t cidx; /* consumer idx (desc idx) */ 413 uint16_t pidx; /* producer idx (desc idx) */ 414 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 415 uint16_t dbidx; /* pidx of the most recent doorbell */ 416 uint16_t iqid; /* iq that gets egr_update for the eq */ 417 uint8_t tx_chan; /* tx channel used by the eq */ 418 volatile u_int equiq; /* EQUIQ outstanding */ 419 420 bus_dma_tag_t desc_tag; 421 bus_dmamap_t desc_map; 422 bus_addr_t ba; /* bus address of descriptor ring */ 423 char lockname[16]; 424 }; 425 426 struct sw_zone_info { 427 uma_zone_t zone; /* zone that this cluster comes from */ 428 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 429 int type; /* EXT_xxx type of the cluster */ 430 int8_t head_hwidx; 431 int8_t tail_hwidx; 432 }; 433 434 struct hw_buf_info { 435 int8_t zidx; /* backpointer to zone; -ve means unused */ 436 int8_t next; /* next hwidx for this zone; -1 means no more */ 437 int size; 438 }; 439 440 enum { 441 NUM_MEMWIN = 3, 442 443 MEMWIN0_APERTURE = 2048, 444 MEMWIN0_BASE = 0x1b800, 445 446 MEMWIN1_APERTURE = 32768, 447 MEMWIN1_BASE = 0x28000, 448 449 MEMWIN2_APERTURE_T4 = 65536, 450 MEMWIN2_BASE_T4 = 0x30000, 451 452 MEMWIN2_APERTURE_T5 = 128 * 1024, 453 MEMWIN2_BASE_T5 = 0x60000, 454 }; 455 456 struct memwin { 457 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 458 uint32_t mw_base; /* constant after setup_memwin */ 459 uint32_t mw_aperture; /* ditto */ 460 uint32_t mw_curpos; /* protected by mw_lock */ 461 }; 462 463 enum { 464 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 465 FL_DOOMED = (1 << 1), /* about to be destroyed */ 466 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 467 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 468 }; 469 470 #define FL_RUNNING_LOW(fl) \ 471 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 472 #define FL_NOT_RUNNING_LOW(fl) \ 473 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 474 475 struct sge_fl { 476 struct mtx fl_lock; 477 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 478 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 479 struct cluster_layout cll_def; /* default refill zone, layout */ 480 uint16_t lowat; /* # of buffers <= this means fl needs help */ 481 int flags; 482 uint16_t buf_boundary; 483 484 /* The 16b idx all deal with hw descriptors */ 485 uint16_t dbidx; /* hw pidx after last doorbell */ 486 uint16_t sidx; /* index of status page */ 487 volatile uint16_t hw_cidx; 488 489 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 490 uint32_t cidx; /* consumer index */ 491 uint32_t pidx; /* producer index */ 492 493 uint32_t dbval; 494 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 495 volatile uint32_t *udb; 496 497 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 498 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 499 uint64_t cl_allocated; /* # of clusters allocated */ 500 uint64_t cl_recycled; /* # of clusters recycled */ 501 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 502 503 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 504 struct mbuf *m0; 505 struct mbuf **pnext; 506 u_int remaining; 507 508 uint16_t qsize; /* # of hw descriptors (status page included) */ 509 uint16_t cntxt_id; /* SGE context id for the freelist */ 510 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 511 bus_dma_tag_t desc_tag; 512 bus_dmamap_t desc_map; 513 char lockname[16]; 514 bus_addr_t ba; /* bus address of descriptor ring */ 515 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 516 }; 517 518 struct mp_ring; 519 520 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 521 struct sge_txq { 522 struct sge_eq eq; /* MUST be first */ 523 524 struct ifnet *ifp; /* the interface this txq belongs to */ 525 struct mp_ring *r; /* tx software ring */ 526 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 527 struct sglist *gl; 528 __be32 cpl_ctrl0; /* for convenience */ 529 530 struct task tx_reclaim_task; 531 /* stats for common events first */ 532 533 uint64_t txcsum; /* # of times hardware assisted with checksum */ 534 uint64_t tso_wrs; /* # of TSO work requests */ 535 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 536 uint64_t imm_wrs; /* # of work requests with immediate data */ 537 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 538 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 539 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 540 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 541 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 542 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 543 544 /* stats for not-that-common events */ 545 } __aligned(CACHE_LINE_SIZE); 546 547 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 548 struct sge_rxq { 549 struct sge_iq iq; /* MUST be first */ 550 struct sge_fl fl; /* MUST follow iq */ 551 552 struct ifnet *ifp; /* the interface this rxq belongs to */ 553 #if defined(INET) || defined(INET6) 554 struct lro_ctrl lro; /* LRO state */ 555 #endif 556 557 /* stats for common events first */ 558 559 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 560 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 561 562 /* stats for not-that-common events */ 563 564 } __aligned(CACHE_LINE_SIZE); 565 566 static inline struct sge_rxq * 567 iq_to_rxq(struct sge_iq *iq) 568 { 569 570 return (__containerof(iq, struct sge_rxq, iq)); 571 } 572 573 574 #ifdef TCP_OFFLOAD 575 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 576 struct sge_ofld_rxq { 577 struct sge_iq iq; /* MUST be first */ 578 struct sge_fl fl; /* MUST follow iq */ 579 } __aligned(CACHE_LINE_SIZE); 580 581 static inline struct sge_ofld_rxq * 582 iq_to_ofld_rxq(struct sge_iq *iq) 583 { 584 585 return (__containerof(iq, struct sge_ofld_rxq, iq)); 586 } 587 #endif 588 589 struct wrqe { 590 STAILQ_ENTRY(wrqe) link; 591 struct sge_wrq *wrq; 592 int wr_len; 593 char wr[] __aligned(16); 594 }; 595 596 struct wrq_cookie { 597 TAILQ_ENTRY(wrq_cookie) link; 598 int ndesc; 599 int pidx; 600 }; 601 602 /* 603 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 604 * and offload tx queues are of this type. 605 */ 606 struct sge_wrq { 607 struct sge_eq eq; /* MUST be first */ 608 609 struct adapter *adapter; 610 struct task wrq_tx_task; 611 612 /* Tx desc reserved but WR not "committed" yet. */ 613 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 614 615 /* List of WRs ready to go out as soon as descriptors are available. */ 616 STAILQ_HEAD(, wrqe) wr_list; 617 u_int nwr_pending; 618 u_int ndesc_needed; 619 620 /* stats for common events first */ 621 622 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 623 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 624 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 625 626 /* stats for not-that-common events */ 627 628 /* 629 * Scratch space for work requests that wrap around after reaching the 630 * status page, and some infomation about the last WR that used it. 631 */ 632 uint16_t ss_pidx; 633 uint16_t ss_len; 634 uint8_t ss[SGE_MAX_WR_LEN]; 635 636 } __aligned(CACHE_LINE_SIZE); 637 638 639 #ifdef DEV_NETMAP 640 struct sge_nm_rxq { 641 struct vi_info *vi; 642 643 struct iq_desc *iq_desc; 644 uint16_t iq_abs_id; 645 uint16_t iq_cntxt_id; 646 uint16_t iq_cidx; 647 uint16_t iq_sidx; 648 uint8_t iq_gen; 649 650 __be64 *fl_desc; 651 uint16_t fl_cntxt_id; 652 uint32_t fl_cidx; 653 uint32_t fl_pidx; 654 uint32_t fl_sidx; 655 uint32_t fl_db_val; 656 u_int fl_hwidx:4; 657 658 u_int nid; /* netmap ring # for this queue */ 659 660 /* infrequently used items after this */ 661 662 bus_dma_tag_t iq_desc_tag; 663 bus_dmamap_t iq_desc_map; 664 bus_addr_t iq_ba; 665 int intr_idx; 666 667 bus_dma_tag_t fl_desc_tag; 668 bus_dmamap_t fl_desc_map; 669 bus_addr_t fl_ba; 670 } __aligned(CACHE_LINE_SIZE); 671 672 struct sge_nm_txq { 673 struct tx_desc *desc; 674 uint16_t cidx; 675 uint16_t pidx; 676 uint16_t sidx; 677 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 678 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 679 uint16_t dbidx; /* pidx of the most recent doorbell */ 680 uint16_t doorbells; 681 volatile uint32_t *udb; 682 u_int udb_qid; 683 u_int cntxt_id; 684 __be32 cpl_ctrl0; /* for convenience */ 685 u_int nid; /* netmap ring # for this queue */ 686 687 /* infrequently used items after this */ 688 689 bus_dma_tag_t desc_tag; 690 bus_dmamap_t desc_map; 691 bus_addr_t ba; 692 int iqidx; 693 } __aligned(CACHE_LINE_SIZE); 694 #endif 695 696 struct sge { 697 int nrxq; /* total # of Ethernet rx queues */ 698 int ntxq; /* total # of Ethernet tx tx queues */ 699 #ifdef TCP_OFFLOAD 700 int nofldrxq; /* total # of TOE rx queues */ 701 int nofldtxq; /* total # of TOE tx queues */ 702 #endif 703 #ifdef DEV_NETMAP 704 int nnmrxq; /* total # of netmap rx queues */ 705 int nnmtxq; /* total # of netmap tx queues */ 706 #endif 707 int niq; /* total # of ingress queues */ 708 int neq; /* total # of egress queues */ 709 710 struct sge_iq fwq; /* Firmware event queue */ 711 struct sge_wrq mgmtq; /* Management queue (control queue) */ 712 struct sge_wrq *ctrlq; /* Control queues */ 713 struct sge_txq *txq; /* NIC tx queues */ 714 struct sge_rxq *rxq; /* NIC rx queues */ 715 #ifdef TCP_OFFLOAD 716 struct sge_wrq *ofld_txq; /* TOE tx queues */ 717 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 718 #endif 719 #ifdef DEV_NETMAP 720 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 721 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 722 #endif 723 724 uint16_t iq_start; 725 int eq_start; 726 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 727 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 728 729 int8_t safe_hwidx1; /* may not have room for metadata */ 730 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 731 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 732 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 733 }; 734 735 struct rss_header; 736 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 737 struct mbuf *); 738 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 739 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 740 741 struct adapter { 742 SLIST_ENTRY(adapter) link; 743 device_t dev; 744 struct cdev *cdev; 745 746 /* PCIe register resources */ 747 int regs_rid; 748 struct resource *regs_res; 749 int msix_rid; 750 struct resource *msix_res; 751 bus_space_handle_t bh; 752 bus_space_tag_t bt; 753 bus_size_t mmio_len; 754 int udbs_rid; 755 struct resource *udbs_res; 756 volatile uint8_t *udbs_base; 757 758 unsigned int pf; 759 unsigned int mbox; 760 unsigned int vpd_busy; 761 unsigned int vpd_flag; 762 763 /* Interrupt information */ 764 int intr_type; 765 int intr_count; 766 struct irq { 767 struct resource *res; 768 int rid; 769 void *tag; 770 } *irq; 771 772 bus_dma_tag_t dmat; /* Parent DMA tag */ 773 774 struct sge sge; 775 int lro_timeout; 776 777 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 778 struct port_info *port[MAX_NPORTS]; 779 uint8_t chan_map[MAX_NCHAN]; 780 781 #ifdef TCP_OFFLOAD 782 void *tom_softc; /* (struct tom_data *) */ 783 struct tom_tunables tt; 784 void *iwarp_softc; /* (struct c4iw_dev *) */ 785 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 786 #endif 787 struct l2t_data *l2t; /* L2 table */ 788 struct tid_info tids; 789 790 uint16_t doorbells; 791 #ifdef TCP_OFFLOAD 792 int offload_map; /* ports with IFCAP_TOE enabled */ 793 int active_ulds; /* ULDs activated on this adapter */ 794 #endif 795 int flags; 796 int debug_flags; 797 798 char ifp_lockname[16]; 799 struct mtx ifp_lock; 800 struct ifnet *ifp; /* tracer ifp */ 801 struct ifmedia media; 802 int traceq; /* iq used by all tracers, -1 if none */ 803 int tracer_valid; /* bitmap of valid tracers */ 804 int tracer_enabled; /* bitmap of enabled tracers */ 805 806 char fw_version[32]; 807 char cfg_file[32]; 808 u_int cfcsum; 809 struct adapter_params params; 810 const struct chip_params *chip_params; 811 struct t4_virt_res vres; 812 813 uint16_t linkcaps; 814 uint16_t niccaps; 815 uint16_t toecaps; 816 uint16_t rdmacaps; 817 uint16_t iscsicaps; 818 uint16_t fcoecaps; 819 820 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 821 822 struct mtx sc_lock; 823 char lockname[16]; 824 825 /* Starving free lists */ 826 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 827 TAILQ_HEAD(, sge_fl) sfl; 828 struct callout sfl_callout; 829 830 struct mtx reg_lock; /* for indirect register access */ 831 832 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 833 834 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 835 fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */ 836 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 837 838 #ifdef INVARIANTS 839 const char *last_op; 840 const void *last_op_thr; 841 int last_op_flags; 842 #endif 843 844 int sc_do_rxcopy; 845 }; 846 847 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 848 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 849 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 850 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 851 852 #define ASSERT_SYNCHRONIZED_OP(sc) \ 853 KASSERT(IS_BUSY(sc) && \ 854 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 855 ("%s: operation not synchronized.", __func__)) 856 857 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 858 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 859 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 860 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 861 862 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 863 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 864 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 865 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 866 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 867 868 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 869 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 870 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 871 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 872 873 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 874 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 875 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 876 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 877 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 878 879 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 880 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 881 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 882 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 883 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 884 885 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 886 do { \ 887 if (sc->debug_flags & DF_DUMP_MBOX) { \ 888 log(LOG_NOTICE, \ 889 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 890 "%016llx %016llx %016llx %016llx\n", \ 891 device_get_nameunit(sc->dev), mbox, \ 892 (unsigned long long)t4_read_reg64(sc, data_reg), \ 893 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 894 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 895 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 896 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 897 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 898 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 899 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 900 } \ 901 } while (0) 902 903 #define for_each_txq(vi, iter, q) \ 904 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 905 iter < vi->ntxq; ++iter, ++q) 906 #define for_each_rxq(vi, iter, q) \ 907 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 908 iter < vi->nrxq; ++iter, ++q) 909 #define for_each_ofld_txq(vi, iter, q) \ 910 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 911 iter < vi->nofldtxq; ++iter, ++q) 912 #define for_each_ofld_rxq(vi, iter, q) \ 913 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 914 iter < vi->nofldrxq; ++iter, ++q) 915 #define for_each_nm_txq(vi, iter, q) \ 916 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_txq], iter = 0; \ 917 iter < vi->ntxq; ++iter, ++q) 918 #define for_each_nm_rxq(vi, iter, q) \ 919 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_rxq], iter = 0; \ 920 iter < vi->nrxq; ++iter, ++q) 921 #define for_each_vi(_pi, _iter, _vi) \ 922 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 923 ++(_iter), ++(_vi)) 924 925 #define IDXINCR(idx, incr, wrap) do { \ 926 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 927 } while (0) 928 #define IDXDIFF(head, tail, wrap) \ 929 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 930 931 /* One for errors, one for firmware events */ 932 #define T4_EXTRA_INTR 2 933 934 static inline uint32_t 935 t4_read_reg(struct adapter *sc, uint32_t reg) 936 { 937 938 return bus_space_read_4(sc->bt, sc->bh, reg); 939 } 940 941 static inline void 942 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 943 { 944 945 bus_space_write_4(sc->bt, sc->bh, reg, val); 946 } 947 948 static inline uint64_t 949 t4_read_reg64(struct adapter *sc, uint32_t reg) 950 { 951 952 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 953 } 954 955 static inline void 956 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 957 { 958 959 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 960 } 961 962 static inline void 963 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 964 { 965 966 *val = pci_read_config(sc->dev, reg, 1); 967 } 968 969 static inline void 970 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 971 { 972 973 pci_write_config(sc->dev, reg, val, 1); 974 } 975 976 static inline void 977 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 978 { 979 980 *val = pci_read_config(sc->dev, reg, 2); 981 } 982 983 static inline void 984 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 985 { 986 987 pci_write_config(sc->dev, reg, val, 2); 988 } 989 990 static inline void 991 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 992 { 993 994 *val = pci_read_config(sc->dev, reg, 4); 995 } 996 997 static inline void 998 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 999 { 1000 1001 pci_write_config(sc->dev, reg, val, 4); 1002 } 1003 1004 static inline struct port_info * 1005 adap2pinfo(struct adapter *sc, int idx) 1006 { 1007 1008 return (sc->port[idx]); 1009 } 1010 1011 static inline void 1012 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1013 { 1014 1015 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1016 } 1017 1018 static inline bool 1019 is_10G_port(const struct port_info *pi) 1020 { 1021 1022 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1023 } 1024 1025 static inline bool 1026 is_40G_port(const struct port_info *pi) 1027 { 1028 1029 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1030 } 1031 1032 static inline int 1033 port_top_speed(const struct port_info *pi) 1034 { 1035 1036 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1037 return (100); 1038 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1039 return (40); 1040 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1041 return (10); 1042 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1043 return (1); 1044 1045 return (0); 1046 } 1047 1048 static inline int 1049 tx_resume_threshold(struct sge_eq *eq) 1050 { 1051 1052 /* not quite the same as qsize / 4, but this will do. */ 1053 return (eq->sidx / 4); 1054 } 1055 1056 static inline int 1057 t4_use_ldst(struct adapter *sc) 1058 { 1059 1060 #ifdef notyet 1061 return (sc->flags & FW_OK || !sc->use_bd); 1062 #else 1063 return (0); 1064 #endif 1065 } 1066 1067 /* t4_main.c */ 1068 int t4_os_find_pci_capability(struct adapter *, int); 1069 int t4_os_pci_save_state(struct adapter *); 1070 int t4_os_pci_restore_state(struct adapter *); 1071 void t4_os_portmod_changed(const struct adapter *, int); 1072 void t4_os_link_changed(struct adapter *, int, int, int); 1073 void t4_iterate(void (*)(struct adapter *, void *), void *); 1074 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 1075 int t4_register_an_handler(struct adapter *, an_handler_t); 1076 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 1077 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1078 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1079 void doom_vi(struct adapter *, struct vi_info *); 1080 void end_synchronized_op(struct adapter *, int); 1081 int update_mac_settings(struct ifnet *, int); 1082 int adapter_full_init(struct adapter *); 1083 int adapter_full_uninit(struct adapter *); 1084 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1085 int vi_full_init(struct vi_info *); 1086 int vi_full_uninit(struct vi_info *); 1087 void vi_sysctls(struct vi_info *); 1088 void vi_tick(void *); 1089 1090 #ifdef DEV_NETMAP 1091 /* t4_netmap.c */ 1092 int create_netmap_ifnet(struct port_info *); 1093 int destroy_netmap_ifnet(struct port_info *); 1094 void t4_nm_intr(void *); 1095 #endif 1096 1097 /* t4_sge.c */ 1098 void t4_sge_modload(void); 1099 void t4_sge_modunload(void); 1100 uint64_t t4_sge_extfree_refs(void); 1101 void t4_init_sge_cpl_handlers(struct adapter *); 1102 void t4_tweak_chip_settings(struct adapter *); 1103 int t4_read_chip_settings(struct adapter *); 1104 int t4_create_dma_tag(struct adapter *); 1105 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1106 struct sysctl_oid_list *); 1107 int t4_destroy_dma_tag(struct adapter *); 1108 int t4_setup_adapter_queues(struct adapter *); 1109 int t4_teardown_adapter_queues(struct adapter *); 1110 int t4_setup_vi_queues(struct vi_info *); 1111 int t4_teardown_vi_queues(struct vi_info *); 1112 void t4_intr_all(void *); 1113 void t4_intr(void *); 1114 void t4_intr_err(void *); 1115 void t4_intr_evt(void *); 1116 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1117 void t4_update_fl_bufsize(struct ifnet *); 1118 int parse_pkt(struct mbuf **); 1119 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1120 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1121 int tnl_cong(struct port_info *, int); 1122 1123 /* t4_tracer.c */ 1124 struct t4_tracer; 1125 void t4_tracer_modload(void); 1126 void t4_tracer_modunload(void); 1127 void t4_tracer_port_detach(struct adapter *); 1128 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1129 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1130 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1131 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1132 1133 static inline struct wrqe * 1134 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1135 { 1136 int len = offsetof(struct wrqe, wr) + wr_len; 1137 struct wrqe *wr; 1138 1139 wr = malloc(len, M_CXGBE, M_NOWAIT); 1140 if (__predict_false(wr == NULL)) 1141 return (NULL); 1142 wr->wr_len = wr_len; 1143 wr->wrq = wrq; 1144 return (wr); 1145 } 1146 1147 static inline void * 1148 wrtod(struct wrqe *wr) 1149 { 1150 return (&wr->wr[0]); 1151 } 1152 1153 static inline void 1154 free_wrqe(struct wrqe *wr) 1155 { 1156 free(wr, M_CXGBE); 1157 } 1158 1159 static inline void 1160 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1161 { 1162 struct sge_wrq *wrq = wr->wrq; 1163 1164 TXQ_LOCK(wrq); 1165 t4_wrq_tx_locked(sc, wrq, wr); 1166 TXQ_UNLOCK(wrq); 1167 } 1168 1169 #endif 1170