1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 #if defined(__i386__) || defined(__amd64__) 72 static __inline void 73 prefetch(void *x) 74 { 75 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 76 } 77 #else 78 #define prefetch(x) __builtin_prefetch(x) 79 #endif 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 ADAP_SYSCTL_CTX = (1 << 4), 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 167 CXGBE_BUSY = (1 << 9), 168 HW_OFF_LIMITS = (1 << 10), /* off limits to all except reset_thread */ 169 170 /* port flags */ 171 HAS_TRACEQ = (1 << 3), 172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 173 174 /* VI flags */ 175 DOOMED = (1 << 0), 176 VI_INIT_DONE = (1 << 1), 177 VI_SYSCTL_CTX = (1 << 2), 178 TX_USES_VM_WR = (1 << 3), 179 VI_SKIP_STATS = (1 << 4), 180 181 /* adapter debug_flags */ 182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 187 }; 188 189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 194 195 struct vi_info { 196 device_t dev; 197 struct port_info *pi; 198 struct adapter *adapter; 199 200 struct ifnet *ifp; 201 struct pfil_head *pfil; 202 203 unsigned long flags; 204 int if_flags; 205 206 uint16_t *rss, *nm_rss; 207 uint16_t viid; /* opaque VI identifier */ 208 uint16_t smt_idx; 209 uint16_t vin; 210 uint8_t vfvld; 211 int16_t xact_addr_filt;/* index of exact MAC address filter */ 212 uint16_t rss_size; /* size of VI's RSS table slice */ 213 uint16_t rss_base; /* start of VI's RSS table slice */ 214 int hashen; 215 216 int nintr; 217 int first_intr; 218 219 /* These need to be int as they are used in sysctl */ 220 int ntxq; /* # of tx queues */ 221 int first_txq; /* index of first tx queue */ 222 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 223 int nrxq; /* # of rx queues */ 224 int first_rxq; /* index of first rx queue */ 225 int nofldtxq; /* # of offload tx queues */ 226 int first_ofld_txq; /* index of first offload tx queue */ 227 int nofldrxq; /* # of offload rx queues */ 228 int first_ofld_rxq; /* index of first offload rx queue */ 229 int nnmtxq; 230 int first_nm_txq; 231 int nnmrxq; 232 int first_nm_rxq; 233 int tmr_idx; 234 int ofld_tmr_idx; 235 int pktc_idx; 236 int ofld_pktc_idx; 237 int qsize_rxq; 238 int qsize_txq; 239 240 struct timeval last_refreshed; 241 struct fw_vi_stats_vf stats; 242 struct mtx tick_mtx; 243 struct callout tick; 244 245 struct sysctl_ctx_list ctx; 246 struct sysctl_oid *rxq_oid; 247 struct sysctl_oid *txq_oid; 248 struct sysctl_oid *nm_rxq_oid; 249 struct sysctl_oid *nm_txq_oid; 250 struct sysctl_oid *ofld_rxq_oid; 251 struct sysctl_oid *ofld_txq_oid; 252 253 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 254 }; 255 256 struct tx_ch_rl_params { 257 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 258 uint32_t maxrate; 259 }; 260 261 enum { 262 CLRL_USER = (1 << 0), /* allocated manually. */ 263 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 264 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 265 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 266 }; 267 268 struct tx_cl_rl_params { 269 int refcount; 270 uint8_t flags; 271 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 272 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 273 enum fw_sched_params_mode mode; /* aggr or per-flow */ 274 uint32_t maxrate; 275 uint16_t pktsize; 276 uint16_t burstsize; 277 }; 278 279 /* Tx scheduler parameters for a channel/port */ 280 struct tx_sched_params { 281 /* Channel Rate Limiter */ 282 struct tx_ch_rl_params ch_rl; 283 284 /* Class WRR */ 285 /* XXX */ 286 287 /* Class Rate Limiter (including the default pktsize and burstsize). */ 288 int pktsize; 289 int burstsize; 290 struct tx_cl_rl_params cl_rl[]; 291 }; 292 293 struct port_info { 294 device_t dev; 295 struct adapter *adapter; 296 297 struct vi_info *vi; 298 int nvi; 299 int up_vis; 300 int uld_vis; 301 bool vxlan_tcam_entry; 302 303 struct tx_sched_params *sched_params; 304 305 struct mtx pi_lock; 306 char lockname[16]; 307 unsigned long flags; 308 309 uint8_t lport; /* associated offload logical port */ 310 int8_t mdio_addr; 311 uint8_t port_type; 312 uint8_t mod_type; 313 uint8_t port_id; 314 uint8_t tx_chan; 315 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 316 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 317 uint8_t rx_c_chan; /* rx TP c-channel */ 318 319 struct link_config link_cfg; 320 struct ifmedia media; 321 322 struct port_stats stats; 323 u_int tnl_cong_drops; 324 u_int tx_parse_error; 325 int fcs_reg; 326 uint64_t fcs_base; 327 }; 328 329 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 330 331 struct cluster_metadata { 332 uma_zone_t zone; 333 caddr_t cl; 334 u_int refcount; 335 }; 336 337 struct fl_sdesc { 338 caddr_t cl; 339 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 340 int16_t moff; /* offset of metadata from cl */ 341 uint8_t zidx; 342 }; 343 344 struct tx_desc { 345 __be64 flit[8]; 346 }; 347 348 struct tx_sdesc { 349 struct mbuf *m; /* m_nextpkt linked chain of frames */ 350 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 351 }; 352 353 354 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 355 struct iq_desc { 356 struct rss_header rss; 357 uint8_t cpl[IQ_PAD]; 358 struct rsp_ctrl rsp; 359 }; 360 #undef IQ_PAD 361 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 362 363 enum { 364 /* iq flags */ 365 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 366 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 367 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 368 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 369 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 370 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 371 372 /* iq state */ 373 IQS_DISABLED = 0, 374 IQS_BUSY = 1, 375 IQS_IDLE = 2, 376 377 /* netmap related flags */ 378 NM_OFF = 0, 379 NM_ON = 1, 380 NM_BUSY = 2, 381 }; 382 383 enum { 384 CPL_COOKIE_RESERVED = 0, 385 CPL_COOKIE_FILTER, 386 CPL_COOKIE_DDP0, 387 CPL_COOKIE_DDP1, 388 CPL_COOKIE_TOM, 389 CPL_COOKIE_HASHFILTER, 390 CPL_COOKIE_ETHOFLD, 391 CPL_COOKIE_KERN_TLS, 392 393 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 394 }; 395 396 struct sge_iq; 397 struct rss_header; 398 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 399 struct mbuf *); 400 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 401 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 402 403 /* 404 * Ingress Queue: T4 is producer, driver is consumer. 405 */ 406 struct sge_iq { 407 uint32_t flags; 408 volatile int state; 409 struct adapter *adapter; 410 struct iq_desc *desc; /* KVA of descriptor ring */ 411 int8_t intr_pktc_idx; /* packet count threshold index */ 412 uint8_t gen; /* generation bit */ 413 uint8_t intr_params; /* interrupt holdoff parameters */ 414 int8_t cong; /* congestion settings */ 415 uint16_t qsize; /* size (# of entries) of the queue */ 416 uint16_t sidx; /* index of the entry with the status page */ 417 uint16_t cidx; /* consumer index */ 418 uint16_t cntxt_id; /* SGE context id for the iq */ 419 uint16_t abs_id; /* absolute SGE id for the iq */ 420 int16_t intr_idx; /* interrupt used by the queue */ 421 422 STAILQ_ENTRY(sge_iq) link; 423 424 bus_dma_tag_t desc_tag; 425 bus_dmamap_t desc_map; 426 bus_addr_t ba; /* bus address of descriptor ring */ 427 }; 428 429 enum { 430 /* eq type */ 431 EQ_CTRL = 1, 432 EQ_ETH = 2, 433 EQ_OFLD = 3, 434 435 /* eq flags */ 436 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 437 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 438 EQ_ENABLED = (1 << 3), /* open for business */ 439 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 440 }; 441 442 /* Listed in order of preference. Update t4_sysctls too if you change these */ 443 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 444 445 /* 446 * Egress Queue: driver is producer, T4 is consumer. 447 * 448 * Note: A free list is an egress queue (driver produces the buffers and T4 449 * consumes them) but it's special enough to have its own struct (see sge_fl). 450 */ 451 struct sge_eq { 452 unsigned int flags; /* MUST be first */ 453 unsigned int cntxt_id; /* SGE context id for the eq */ 454 unsigned int abs_id; /* absolute SGE id for the eq */ 455 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 456 uint8_t doorbells; 457 uint8_t tx_chan; /* tx channel used by the eq */ 458 struct mtx eq_lock; 459 460 struct tx_desc *desc; /* KVA of descriptor ring */ 461 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 462 u_int udb_qid; /* relative qid within the doorbell page */ 463 uint16_t sidx; /* index of the entry with the status page */ 464 uint16_t cidx; /* consumer idx (desc idx) */ 465 uint16_t pidx; /* producer idx (desc idx) */ 466 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 467 uint16_t dbidx; /* pidx of the most recent doorbell */ 468 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 469 volatile u_int equiq; /* EQUIQ outstanding */ 470 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 471 472 bus_dma_tag_t desc_tag; 473 bus_dmamap_t desc_map; 474 bus_addr_t ba; /* bus address of descriptor ring */ 475 char lockname[16]; 476 }; 477 478 struct rx_buf_info { 479 uma_zone_t zone; /* zone that this cluster comes from */ 480 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 481 * hwsize[hwidx1] = size1. No spare. */ 482 uint16_t size2; /* hwsize[hwidx2] = size2. 483 * spare in cluster = size1 - size2. */ 484 int8_t hwidx1; /* SGE bufsize idx for size1 */ 485 int8_t hwidx2; /* SGE bufsize idx for size2 */ 486 uint8_t type; /* EXT_xxx type of the cluster */ 487 }; 488 489 enum { 490 NUM_MEMWIN = 3, 491 492 MEMWIN0_APERTURE = 2048, 493 MEMWIN0_BASE = 0x1b800, 494 495 MEMWIN1_APERTURE = 32768, 496 MEMWIN1_BASE = 0x28000, 497 498 MEMWIN2_APERTURE_T4 = 65536, 499 MEMWIN2_BASE_T4 = 0x30000, 500 501 MEMWIN2_APERTURE_T5 = 128 * 1024, 502 MEMWIN2_BASE_T5 = 0x60000, 503 }; 504 505 struct memwin { 506 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 507 uint32_t mw_base; /* constant after setup_memwin */ 508 uint32_t mw_aperture; /* ditto */ 509 uint32_t mw_curpos; /* protected by mw_lock */ 510 }; 511 512 enum { 513 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 514 FL_DOOMED = (1 << 1), /* about to be destroyed */ 515 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 516 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 517 }; 518 519 #define FL_RUNNING_LOW(fl) \ 520 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 521 #define FL_NOT_RUNNING_LOW(fl) \ 522 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 523 524 struct sge_fl { 525 struct mtx fl_lock; 526 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 527 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 528 uint16_t zidx; /* refill zone idx */ 529 uint16_t safe_zidx; 530 uint16_t lowat; /* # of buffers <= this means fl needs help */ 531 int flags; 532 uint16_t buf_boundary; 533 534 /* The 16b idx all deal with hw descriptors */ 535 uint16_t dbidx; /* hw pidx after last doorbell */ 536 uint16_t sidx; /* index of status page */ 537 volatile uint16_t hw_cidx; 538 539 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 540 uint32_t cidx; /* consumer index */ 541 uint32_t pidx; /* producer index */ 542 543 uint32_t dbval; 544 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 545 volatile uint32_t *udb; 546 547 uint64_t cl_allocated; /* # of clusters allocated */ 548 uint64_t cl_recycled; /* # of clusters recycled */ 549 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 550 551 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 552 struct mbuf *m0; 553 struct mbuf **pnext; 554 u_int remaining; 555 556 uint16_t qsize; /* # of hw descriptors (status page included) */ 557 uint16_t cntxt_id; /* SGE context id for the freelist */ 558 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 559 bus_dma_tag_t desc_tag; 560 bus_dmamap_t desc_map; 561 char lockname[16]; 562 bus_addr_t ba; /* bus address of descriptor ring */ 563 }; 564 565 struct mp_ring; 566 567 struct txpkts { 568 uint8_t wr_type; /* type 0 or type 1 */ 569 uint8_t npkt; /* # of packets in this work request */ 570 uint8_t len16; /* # of 16B pieces used by this work request */ 571 uint8_t score; 572 uint8_t max_npkt; /* maximum number of packets allowed */ 573 uint16_t plen; /* total payload (sum of all packets) */ 574 575 /* straight from fw_eth_tx_pkts_vm_wr. */ 576 __u8 ethmacdst[6]; 577 __u8 ethmacsrc[6]; 578 __be16 ethtype; 579 __be16 vlantci; 580 581 struct mbuf *mb[15]; 582 }; 583 584 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 585 struct sge_txq { 586 struct sge_eq eq; /* MUST be first */ 587 588 struct ifnet *ifp; /* the interface this txq belongs to */ 589 struct mp_ring *r; /* tx software ring */ 590 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 591 struct sglist *gl; 592 __be32 cpl_ctrl0; /* for convenience */ 593 int tc_idx; /* traffic class */ 594 uint64_t last_tx; /* cycle count when eth_tx was last called */ 595 struct txpkts txp; 596 597 struct task tx_reclaim_task; 598 /* stats for common events first */ 599 600 uint64_t txcsum; /* # of times hardware assisted with checksum */ 601 uint64_t tso_wrs; /* # of TSO work requests */ 602 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 603 uint64_t imm_wrs; /* # of work requests with immediate data */ 604 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 605 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 606 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 607 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 608 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 609 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 610 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 611 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 612 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 613 uint64_t vxlan_txcsum; 614 615 uint64_t kern_tls_records; 616 uint64_t kern_tls_short; 617 uint64_t kern_tls_partial; 618 uint64_t kern_tls_full; 619 uint64_t kern_tls_octets; 620 uint64_t kern_tls_waste; 621 uint64_t kern_tls_options; 622 uint64_t kern_tls_header; 623 uint64_t kern_tls_fin; 624 uint64_t kern_tls_fin_short; 625 uint64_t kern_tls_cbc; 626 uint64_t kern_tls_gcm; 627 628 /* stats for not-that-common events */ 629 630 /* Optional scratch space for constructing work requests. */ 631 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 632 } __aligned(CACHE_LINE_SIZE); 633 634 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 635 struct sge_rxq { 636 struct sge_iq iq; /* MUST be first */ 637 struct sge_fl fl; /* MUST follow iq */ 638 639 struct ifnet *ifp; /* the interface this rxq belongs to */ 640 struct lro_ctrl lro; /* LRO state */ 641 642 /* stats for common events first */ 643 644 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 645 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 646 uint64_t vxlan_rxcsum; 647 648 /* stats for not-that-common events */ 649 650 } __aligned(CACHE_LINE_SIZE); 651 652 static inline struct sge_rxq * 653 iq_to_rxq(struct sge_iq *iq) 654 { 655 656 return (__containerof(iq, struct sge_rxq, iq)); 657 } 658 659 660 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 661 struct sge_ofld_rxq { 662 struct sge_iq iq; /* MUST be first */ 663 struct sge_fl fl; /* MUST follow iq */ 664 u_long rx_toe_tls_records; 665 u_long rx_toe_tls_octets; 666 } __aligned(CACHE_LINE_SIZE); 667 668 static inline struct sge_ofld_rxq * 669 iq_to_ofld_rxq(struct sge_iq *iq) 670 { 671 672 return (__containerof(iq, struct sge_ofld_rxq, iq)); 673 } 674 675 struct wrqe { 676 STAILQ_ENTRY(wrqe) link; 677 struct sge_wrq *wrq; 678 int wr_len; 679 char wr[] __aligned(16); 680 }; 681 682 struct wrq_cookie { 683 TAILQ_ENTRY(wrq_cookie) link; 684 int ndesc; 685 int pidx; 686 }; 687 688 /* 689 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 690 * are of this type. 691 */ 692 struct sge_wrq { 693 struct sge_eq eq; /* MUST be first */ 694 695 struct adapter *adapter; 696 struct task wrq_tx_task; 697 698 /* Tx desc reserved but WR not "committed" yet. */ 699 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 700 701 /* List of WRs ready to go out as soon as descriptors are available. */ 702 STAILQ_HEAD(, wrqe) wr_list; 703 u_int nwr_pending; 704 u_int ndesc_needed; 705 706 /* stats for common events first */ 707 708 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 709 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 710 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 711 712 /* stats for not-that-common events */ 713 714 /* 715 * Scratch space for work requests that wrap around after reaching the 716 * status page, and some information about the last WR that used it. 717 */ 718 uint16_t ss_pidx; 719 uint16_t ss_len; 720 uint8_t ss[SGE_MAX_WR_LEN]; 721 722 } __aligned(CACHE_LINE_SIZE); 723 724 /* ofld_txq: SGE egress queue + miscellaneous items */ 725 struct sge_ofld_txq { 726 struct sge_wrq wrq; 727 counter_u64_t tx_iscsi_pdus; 728 counter_u64_t tx_iscsi_octets; 729 counter_u64_t tx_toe_tls_records; 730 counter_u64_t tx_toe_tls_octets; 731 } __aligned(CACHE_LINE_SIZE); 732 733 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 734 struct sge_nm_rxq { 735 /* Items used by the driver rx ithread are in this cacheline. */ 736 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 737 u_int nid; /* netmap ring # for this queue */ 738 struct vi_info *vi; 739 740 struct iq_desc *iq_desc; 741 uint16_t iq_abs_id; 742 uint16_t iq_cntxt_id; 743 uint16_t iq_cidx; 744 uint16_t iq_sidx; 745 uint8_t iq_gen; 746 uint32_t fl_sidx; 747 748 /* Items used by netmap rxsync are in this cacheline. */ 749 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 750 uint16_t fl_cntxt_id; 751 uint32_t fl_pidx; 752 uint32_t fl_sidx2; /* copy of fl_sidx */ 753 uint32_t fl_db_val; 754 u_int fl_db_saved; 755 u_int fl_db_threshold; /* in descriptors */ 756 u_int fl_hwidx:4; 757 758 /* 759 * fl_cidx is used by both the ithread and rxsync, the rest are not used 760 * in the rx fast path. 761 */ 762 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 763 764 bus_dma_tag_t iq_desc_tag; 765 bus_dmamap_t iq_desc_map; 766 bus_addr_t iq_ba; 767 int intr_idx; 768 769 bus_dma_tag_t fl_desc_tag; 770 bus_dmamap_t fl_desc_map; 771 bus_addr_t fl_ba; 772 }; 773 774 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 775 struct sge_nm_txq { 776 struct tx_desc *desc; 777 uint16_t cidx; 778 uint16_t pidx; 779 uint16_t sidx; 780 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 781 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 782 uint16_t dbidx; /* pidx of the most recent doorbell */ 783 uint8_t doorbells; 784 volatile uint32_t *udb; 785 u_int udb_qid; 786 u_int cntxt_id; 787 __be32 cpl_ctrl0; /* for convenience */ 788 __be32 op_pkd; /* ditto */ 789 u_int nid; /* netmap ring # for this queue */ 790 791 /* infrequently used items after this */ 792 793 bus_dma_tag_t desc_tag; 794 bus_dmamap_t desc_map; 795 bus_addr_t ba; 796 int iqidx; 797 } __aligned(CACHE_LINE_SIZE); 798 799 struct sge { 800 int nrxq; /* total # of Ethernet rx queues */ 801 int ntxq; /* total # of Ethernet tx queues */ 802 int nofldrxq; /* total # of TOE rx queues */ 803 int nofldtxq; /* total # of TOE tx queues */ 804 int nnmrxq; /* total # of netmap rx queues */ 805 int nnmtxq; /* total # of netmap tx queues */ 806 int niq; /* total # of ingress queues */ 807 int neq; /* total # of egress queues */ 808 809 struct sge_iq fwq; /* Firmware event queue */ 810 struct sge_wrq *ctrlq; /* Control queues */ 811 struct sge_txq *txq; /* NIC tx queues */ 812 struct sge_rxq *rxq; /* NIC rx queues */ 813 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 814 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 815 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 816 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 817 818 uint16_t iq_start; /* first cntxt_id */ 819 uint16_t iq_base; /* first abs_id */ 820 int eq_start; /* first cntxt_id */ 821 int eq_base; /* first abs_id */ 822 int iqmap_sz; 823 int eqmap_sz; 824 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 825 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 826 827 int8_t safe_zidx; 828 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 829 }; 830 831 struct devnames { 832 const char *nexus_name; 833 const char *ifnet_name; 834 const char *vi_ifnet_name; 835 const char *pf03_drv_name; 836 const char *vf_nexus_name; 837 const char *vf_ifnet_name; 838 }; 839 840 struct clip_entry; 841 842 struct adapter { 843 SLIST_ENTRY(adapter) link; 844 device_t dev; 845 struct cdev *cdev; 846 const struct devnames *names; 847 848 /* PCIe register resources */ 849 int regs_rid; 850 struct resource *regs_res; 851 int msix_rid; 852 struct resource *msix_res; 853 bus_space_handle_t bh; 854 bus_space_tag_t bt; 855 bus_size_t mmio_len; 856 int udbs_rid; 857 struct resource *udbs_res; 858 volatile uint8_t *udbs_base; 859 860 unsigned int pf; 861 unsigned int mbox; 862 unsigned int vpd_busy; 863 unsigned int vpd_flag; 864 865 /* Interrupt information */ 866 int intr_type; 867 int intr_count; 868 struct irq { 869 struct resource *res; 870 int rid; 871 void *tag; 872 struct sge_rxq *rxq; 873 struct sge_nm_rxq *nm_rxq; 874 } __aligned(CACHE_LINE_SIZE) *irq; 875 int sge_gts_reg; 876 int sge_kdoorbell_reg; 877 878 bus_dma_tag_t dmat; /* Parent DMA tag */ 879 880 struct sge sge; 881 int lro_timeout; 882 int sc_do_rxcopy; 883 884 int vxlan_port; 885 u_int vxlan_refcount; 886 int rawf_base; 887 int nrawf; 888 889 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 890 struct task async_event_task; 891 struct port_info *port[MAX_NPORTS]; 892 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 893 894 struct mtx clip_table_lock; 895 TAILQ_HEAD(, clip_entry) clip_table; 896 int clip_gen; 897 898 void *tom_softc; /* (struct tom_data *) */ 899 struct tom_tunables tt; 900 struct t4_offload_policy *policy; 901 struct rwlock policy_lock; 902 903 void *iwarp_softc; /* (struct c4iw_dev *) */ 904 struct iw_tunables iwt; 905 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 906 void *ccr_softc; /* (struct ccr_softc *) */ 907 struct l2t_data *l2t; /* L2 table */ 908 struct smt_data *smt; /* Source MAC Table */ 909 struct tid_info tids; 910 vmem_t *key_map; 911 struct tls_tunables tlst; 912 913 uint8_t doorbells; 914 int offload_map; /* ports with IFCAP_TOE enabled */ 915 int active_ulds; /* ULDs activated on this adapter */ 916 int flags; 917 int debug_flags; 918 919 char ifp_lockname[16]; 920 struct mtx ifp_lock; 921 struct ifnet *ifp; /* tracer ifp */ 922 struct ifmedia media; 923 int traceq; /* iq used by all tracers, -1 if none */ 924 int tracer_valid; /* bitmap of valid tracers */ 925 int tracer_enabled; /* bitmap of enabled tracers */ 926 927 char fw_version[16]; 928 char tp_version[16]; 929 char er_version[16]; 930 char bs_version[16]; 931 char cfg_file[32]; 932 u_int cfcsum; 933 struct adapter_params params; 934 const struct chip_params *chip_params; 935 struct t4_virt_res vres; 936 937 uint16_t nbmcaps; 938 uint16_t linkcaps; 939 uint16_t switchcaps; 940 uint16_t niccaps; 941 uint16_t toecaps; 942 uint16_t rdmacaps; 943 uint16_t cryptocaps; 944 uint16_t iscsicaps; 945 uint16_t fcoecaps; 946 947 struct sysctl_ctx_list ctx; 948 struct sysctl_oid *ctrlq_oid; 949 struct sysctl_oid *fwq_oid; 950 951 struct mtx sc_lock; 952 char lockname[16]; 953 954 /* Starving free lists */ 955 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 956 TAILQ_HEAD(, sge_fl) sfl; 957 struct callout sfl_callout; 958 959 /* 960 * Driver code that can run when the adapter is suspended must use this 961 * lock or a synchronized_op and check for HW_OFF_LIMITS before 962 * accessing hardware. 963 * 964 * XXX: could be changed to rwlock. wlock in suspend/resume and for 965 * indirect register access, rlock everywhere else. 966 */ 967 struct mtx reg_lock; 968 969 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 970 971 struct mtx tc_lock; 972 struct task tc_task; 973 974 struct task reset_task; 975 const void *reset_thread; 976 int num_resets; 977 int incarnation; 978 979 const char *last_op; 980 const void *last_op_thr; 981 int last_op_flags; 982 983 int swintr; 984 int sensor_resets; 985 986 struct callout ktls_tick; 987 }; 988 989 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 990 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 991 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 992 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 993 994 #define ASSERT_SYNCHRONIZED_OP(sc) \ 995 KASSERT(IS_BUSY(sc) && \ 996 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 997 ("%s: operation not synchronized.", __func__)) 998 999 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1000 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1001 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1002 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1003 1004 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1005 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1006 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1007 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1008 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1009 1010 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1011 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1012 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1013 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1014 1015 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1016 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1017 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1018 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1019 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1020 1021 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1022 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1023 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1024 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1025 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1026 1027 #define for_each_txq(vi, iter, q) \ 1028 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1029 iter < vi->ntxq; ++iter, ++q) 1030 #define for_each_rxq(vi, iter, q) \ 1031 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1032 iter < vi->nrxq; ++iter, ++q) 1033 #define for_each_ofld_txq(vi, iter, q) \ 1034 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1035 iter < vi->nofldtxq; ++iter, ++q) 1036 #define for_each_ofld_rxq(vi, iter, q) \ 1037 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1038 iter < vi->nofldrxq; ++iter, ++q) 1039 #define for_each_nm_txq(vi, iter, q) \ 1040 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1041 iter < vi->nnmtxq; ++iter, ++q) 1042 #define for_each_nm_rxq(vi, iter, q) \ 1043 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1044 iter < vi->nnmrxq; ++iter, ++q) 1045 #define for_each_vi(_pi, _iter, _vi) \ 1046 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1047 ++(_iter), ++(_vi)) 1048 1049 #define IDXINCR(idx, incr, wrap) do { \ 1050 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1051 } while (0) 1052 #define IDXDIFF(head, tail, wrap) \ 1053 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1054 1055 /* One for errors, one for firmware events */ 1056 #define T4_EXTRA_INTR 2 1057 1058 /* One for firmware events */ 1059 #define T4VF_EXTRA_INTR 1 1060 1061 static inline int 1062 forwarding_intr_to_fwq(struct adapter *sc) 1063 { 1064 1065 return (sc->intr_count == 1); 1066 } 1067 1068 /* Works reliably inside a sync_op or with reg_lock held. */ 1069 static inline bool 1070 hw_off_limits(struct adapter *sc) 1071 { 1072 return (__predict_false(sc->flags & HW_OFF_LIMITS)); 1073 } 1074 1075 static inline uint32_t 1076 t4_read_reg(struct adapter *sc, uint32_t reg) 1077 { 1078 if (hw_off_limits(sc)) 1079 MPASS(curthread == sc->reset_thread); 1080 return bus_space_read_4(sc->bt, sc->bh, reg); 1081 } 1082 1083 static inline void 1084 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1085 { 1086 if (hw_off_limits(sc)) 1087 MPASS(curthread == sc->reset_thread); 1088 bus_space_write_4(sc->bt, sc->bh, reg, val); 1089 } 1090 1091 static inline uint64_t 1092 t4_read_reg64(struct adapter *sc, uint32_t reg) 1093 { 1094 if (hw_off_limits(sc)) 1095 MPASS(curthread == sc->reset_thread); 1096 #ifdef __LP64__ 1097 return bus_space_read_8(sc->bt, sc->bh, reg); 1098 #else 1099 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1100 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1101 1102 #endif 1103 } 1104 1105 static inline void 1106 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1107 { 1108 if (hw_off_limits(sc)) 1109 MPASS(curthread == sc->reset_thread); 1110 #ifdef __LP64__ 1111 bus_space_write_8(sc->bt, sc->bh, reg, val); 1112 #else 1113 bus_space_write_4(sc->bt, sc->bh, reg, val); 1114 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1115 #endif 1116 } 1117 1118 static inline void 1119 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1120 { 1121 if (hw_off_limits(sc)) 1122 MPASS(curthread == sc->reset_thread); 1123 *val = pci_read_config(sc->dev, reg, 1); 1124 } 1125 1126 static inline void 1127 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1128 { 1129 if (hw_off_limits(sc)) 1130 MPASS(curthread == sc->reset_thread); 1131 pci_write_config(sc->dev, reg, val, 1); 1132 } 1133 1134 static inline void 1135 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1136 { 1137 1138 if (hw_off_limits(sc)) 1139 MPASS(curthread == sc->reset_thread); 1140 *val = pci_read_config(sc->dev, reg, 2); 1141 } 1142 1143 static inline void 1144 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1145 { 1146 if (hw_off_limits(sc)) 1147 MPASS(curthread == sc->reset_thread); 1148 pci_write_config(sc->dev, reg, val, 2); 1149 } 1150 1151 static inline void 1152 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1153 { 1154 if (hw_off_limits(sc)) 1155 MPASS(curthread == sc->reset_thread); 1156 *val = pci_read_config(sc->dev, reg, 4); 1157 } 1158 1159 static inline void 1160 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1161 { 1162 if (hw_off_limits(sc)) 1163 MPASS(curthread == sc->reset_thread); 1164 pci_write_config(sc->dev, reg, val, 4); 1165 } 1166 1167 static inline struct port_info * 1168 adap2pinfo(struct adapter *sc, int idx) 1169 { 1170 1171 return (sc->port[idx]); 1172 } 1173 1174 static inline void 1175 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1176 { 1177 1178 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1179 } 1180 1181 static inline int 1182 tx_resume_threshold(struct sge_eq *eq) 1183 { 1184 1185 /* not quite the same as qsize / 4, but this will do. */ 1186 return (eq->sidx / 4); 1187 } 1188 1189 static inline int 1190 t4_use_ldst(struct adapter *sc) 1191 { 1192 1193 #ifdef notyet 1194 return (sc->flags & FW_OK || !sc->use_bd); 1195 #else 1196 return (0); 1197 #endif 1198 } 1199 1200 static inline void 1201 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1202 const char *msg, const __be64 *const p, const bool err) 1203 { 1204 1205 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1206 return; 1207 if (p != NULL) { 1208 log(err ? LOG_ERR : LOG_DEBUG, 1209 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1210 "%016llx %016llx %016llx %016llx\n", 1211 device_get_nameunit(sc->dev), mbox, msg, 1212 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1213 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1214 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1215 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1216 } else { 1217 log(err ? LOG_ERR : LOG_DEBUG, 1218 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1219 "%016llx %016llx %016llx %016llx\n", 1220 device_get_nameunit(sc->dev), mbox, msg, 1221 (long long)t4_read_reg64(sc, reg), 1222 (long long)t4_read_reg64(sc, reg + 8), 1223 (long long)t4_read_reg64(sc, reg + 16), 1224 (long long)t4_read_reg64(sc, reg + 24), 1225 (long long)t4_read_reg64(sc, reg + 32), 1226 (long long)t4_read_reg64(sc, reg + 40), 1227 (long long)t4_read_reg64(sc, reg + 48), 1228 (long long)t4_read_reg64(sc, reg + 56)); 1229 } 1230 } 1231 1232 /* t4_main.c */ 1233 extern int t4_ntxq; 1234 extern int t4_nrxq; 1235 extern int t4_intr_types; 1236 extern int t4_tmr_idx; 1237 extern int t4_pktc_idx; 1238 extern unsigned int t4_qsize_rxq; 1239 extern unsigned int t4_qsize_txq; 1240 extern device_method_t cxgbe_methods[]; 1241 1242 int t4_os_find_pci_capability(struct adapter *, int); 1243 int t4_os_pci_save_state(struct adapter *); 1244 int t4_os_pci_restore_state(struct adapter *); 1245 void t4_os_portmod_changed(struct port_info *); 1246 void t4_os_link_changed(struct port_info *); 1247 void t4_iterate(void (*)(struct adapter *, void *), void *); 1248 void t4_init_devnames(struct adapter *); 1249 void t4_add_adapter(struct adapter *); 1250 int t4_detach_common(device_t); 1251 int t4_map_bars_0_and_4(struct adapter *); 1252 int t4_map_bar_2(struct adapter *); 1253 int t4_setup_intr_handlers(struct adapter *); 1254 void t4_sysctls(struct adapter *); 1255 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1256 void doom_vi(struct adapter *, struct vi_info *); 1257 void end_synchronized_op(struct adapter *, int); 1258 int update_mac_settings(struct ifnet *, int); 1259 int adapter_init(struct adapter *); 1260 int vi_init(struct vi_info *); 1261 void vi_sysctls(struct vi_info *); 1262 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1263 int alloc_atid(struct adapter *, void *); 1264 void *lookup_atid(struct adapter *, int); 1265 void free_atid(struct adapter *, int); 1266 void release_tid(struct adapter *, int, struct sge_wrq *); 1267 int cxgbe_media_change(struct ifnet *); 1268 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1269 bool t4_os_dump_cimla(struct adapter *, int, bool); 1270 void t4_os_dump_devlog(struct adapter *); 1271 1272 #ifdef KERN_TLS 1273 /* t4_kern_tls.c */ 1274 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1275 struct m_snd_tag **); 1276 void cxgbe_tls_tag_free(struct m_snd_tag *); 1277 void t6_ktls_modload(void); 1278 void t6_ktls_modunload(void); 1279 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1280 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1281 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1282 #endif 1283 1284 /* t4_keyctx.c */ 1285 struct auth_hash; 1286 union authctx; 1287 1288 void t4_aes_getdeckey(void *, const void *, unsigned int); 1289 void t4_copy_partial_hash(int, union authctx *, void *); 1290 void t4_init_gmac_hash(const char *, int, char *); 1291 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *); 1292 1293 #ifdef DEV_NETMAP 1294 /* t4_netmap.c */ 1295 struct sge_nm_rxq; 1296 void cxgbe_nm_attach(struct vi_info *); 1297 void cxgbe_nm_detach(struct vi_info *); 1298 void service_nm_rxq(struct sge_nm_rxq *); 1299 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1300 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1301 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1302 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1303 #endif 1304 1305 /* t4_sge.c */ 1306 void t4_sge_modload(void); 1307 void t4_sge_modunload(void); 1308 uint64_t t4_sge_extfree_refs(void); 1309 void t4_tweak_chip_settings(struct adapter *); 1310 int t4_verify_chip_settings(struct adapter *); 1311 void t4_init_rx_buf_info(struct adapter *); 1312 int t4_create_dma_tag(struct adapter *); 1313 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1314 struct sysctl_oid_list *); 1315 int t4_destroy_dma_tag(struct adapter *); 1316 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1317 bus_addr_t *, void **); 1318 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1319 void *); 1320 void free_fl_buffers(struct adapter *, struct sge_fl *); 1321 int t4_setup_adapter_queues(struct adapter *); 1322 int t4_teardown_adapter_queues(struct adapter *); 1323 int t4_setup_vi_queues(struct vi_info *); 1324 int t4_teardown_vi_queues(struct vi_info *); 1325 void t4_intr_all(void *); 1326 void t4_intr(void *); 1327 #ifdef DEV_NETMAP 1328 void t4_nm_intr(void *); 1329 void t4_vi_intr(void *); 1330 #endif 1331 void t4_intr_err(void *); 1332 void t4_intr_evt(void *); 1333 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1334 void t4_update_fl_bufsize(struct ifnet *); 1335 struct mbuf *alloc_wr_mbuf(int, int); 1336 int parse_pkt(struct mbuf **, bool); 1337 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1338 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1339 int tnl_cong(struct port_info *, int); 1340 void t4_register_an_handler(an_handler_t); 1341 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1342 void t4_register_cpl_handler(int, cpl_handler_t); 1343 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1344 #ifdef RATELIMIT 1345 int ethofld_transmit(struct ifnet *, struct mbuf *); 1346 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1347 #endif 1348 1349 /* t4_tracer.c */ 1350 struct t4_tracer; 1351 void t4_tracer_modload(void); 1352 void t4_tracer_modunload(void); 1353 void t4_tracer_port_detach(struct adapter *); 1354 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1355 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1356 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1357 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1358 1359 /* t4_sched.c */ 1360 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1361 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1362 int t4_init_tx_sched(struct adapter *); 1363 int t4_free_tx_sched(struct adapter *); 1364 void t4_update_tx_sched(struct adapter *); 1365 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1366 void t4_release_cl_rl(struct adapter *, int, int); 1367 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1368 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1369 #ifdef RATELIMIT 1370 void t4_init_etid_table(struct adapter *); 1371 void t4_free_etid_table(struct adapter *); 1372 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1373 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1374 struct m_snd_tag **); 1375 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1376 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1377 void cxgbe_rate_tag_free(struct m_snd_tag *); 1378 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1379 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1380 #endif 1381 1382 /* t4_filter.c */ 1383 int get_filter_mode(struct adapter *, uint32_t *); 1384 int set_filter_mode(struct adapter *, uint32_t); 1385 int set_filter_mask(struct adapter *, uint32_t); 1386 int get_filter(struct adapter *, struct t4_filter *); 1387 int set_filter(struct adapter *, struct t4_filter *); 1388 int del_filter(struct adapter *, struct t4_filter *); 1389 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1390 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1391 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1392 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1393 void free_hftid_hash(struct tid_info *); 1394 1395 static inline struct wrqe * 1396 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1397 { 1398 int len = offsetof(struct wrqe, wr) + wr_len; 1399 struct wrqe *wr; 1400 1401 wr = malloc(len, M_CXGBE, M_NOWAIT); 1402 if (__predict_false(wr == NULL)) 1403 return (NULL); 1404 wr->wr_len = wr_len; 1405 wr->wrq = wrq; 1406 return (wr); 1407 } 1408 1409 static inline void * 1410 wrtod(struct wrqe *wr) 1411 { 1412 return (&wr->wr[0]); 1413 } 1414 1415 static inline void 1416 free_wrqe(struct wrqe *wr) 1417 { 1418 free(wr, M_CXGBE); 1419 } 1420 1421 static inline void 1422 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1423 { 1424 struct sge_wrq *wrq = wr->wrq; 1425 1426 TXQ_LOCK(wrq); 1427 t4_wrq_tx_locked(sc, wrq, wr); 1428 TXQ_UNLOCK(wrq); 1429 } 1430 1431 static inline int 1432 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1433 int len) 1434 { 1435 1436 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1437 } 1438 1439 static inline int 1440 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1441 const uint32_t *val, int len) 1442 { 1443 1444 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1445 } 1446 1447 /* Number of len16 -> number of descriptors */ 1448 static inline int 1449 tx_len16_to_desc(int len16) 1450 { 1451 1452 return (howmany(len16, EQ_ESIZE / 16)); 1453 } 1454 #endif 1455