1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/bus.h> 35 #include <sys/rman.h> 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcireg.h> 40 #include <machine/bus.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_media.h> 46 #include <netinet/tcp_lro.h> 47 48 #include "offload.h" 49 #include "common/t4fw_interface.h" 50 51 #define T4_FWNAME "t4fw" 52 53 MALLOC_DECLARE(M_CXGBE); 54 #define CXGBE_UNIMPLEMENTED(s) \ 55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56 57 #if defined(__i386__) || defined(__amd64__) 58 static __inline void 59 prefetch(void *x) 60 { 61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62 } 63 #else 64 #define prefetch(x) 65 #endif 66 67 #ifdef __amd64__ 68 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 69 static __inline uint64_t 70 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 71 bus_size_t offset) 72 { 73 KASSERT(tag == X86_BUS_SPACE_MEM, 74 ("%s: can only handle mem space", __func__)); 75 76 return (*(volatile uint64_t *)(handle + offset)); 77 } 78 79 static __inline void 80 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 81 bus_size_t offset, uint64_t value) 82 { 83 KASSERT(tag == X86_BUS_SPACE_MEM, 84 ("%s: can only handle mem space", __func__)); 85 86 *(volatile uint64_t *)(bsh + offset) = value; 87 } 88 #else 89 static __inline uint64_t 90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 91 bus_size_t offset) 92 { 93 return (uint64_t)bus_space_read_4(tag, handle, offset) + 94 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 95 } 96 97 static __inline void 98 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 99 bus_size_t offset, uint64_t value) 100 { 101 bus_space_write_4(tag, bsh, offset, value); 102 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 103 } 104 #endif 105 106 struct adapter; 107 typedef struct adapter adapter_t; 108 109 enum { 110 FW_IQ_QSIZE = 256, 111 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 112 113 RX_IQ_QSIZE = 1024, 114 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 115 116 RX_FL_ESIZE = 64, /* 8 64bit addresses */ 117 118 #if MJUMPAGESIZE != MCLBYTES 119 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 120 #else 121 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 122 #endif 123 124 TX_EQ_QSIZE = 1024, 125 TX_EQ_ESIZE = 64, 126 TX_SGL_SEGS = 36, 127 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 128 }; 129 130 enum { 131 /* adapter flags */ 132 FULL_INIT_DONE = (1 << 0), 133 FW_OK = (1 << 1), 134 INTR_FWD = (1 << 2), 135 136 CXGBE_BUSY = (1 << 9), 137 138 /* port flags */ 139 DOOMED = (1 << 0), 140 VI_ENABLED = (1 << 1), 141 }; 142 143 #define IS_DOOMED(pi) (pi->flags & DOOMED) 144 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 145 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 146 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 147 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 148 149 struct port_info { 150 device_t dev; 151 struct adapter *adapter; 152 153 struct ifnet *ifp; 154 struct ifmedia media; 155 156 struct mtx pi_lock; 157 char lockname[16]; 158 unsigned long flags; 159 int if_flags; 160 161 uint16_t viid; 162 int16_t xact_addr_filt;/* index of exact MAC address filter */ 163 uint16_t rss_size; /* size of VI's RSS table slice */ 164 uint8_t lport; /* associated offload logical port */ 165 int8_t mdio_addr; 166 uint8_t port_type; 167 uint8_t mod_type; 168 uint8_t port_id; 169 uint8_t tx_chan; 170 171 /* These need to be int as they are used in sysctl */ 172 int ntxq; /* # of tx queues */ 173 int first_txq; /* index of first tx queue */ 174 int nrxq; /* # of rx queues */ 175 int first_rxq; /* index of first rx queue */ 176 int tmr_idx; 177 int pktc_idx; 178 int qsize_rxq; 179 int qsize_txq; 180 181 struct link_config link_cfg; 182 struct port_stats stats; 183 184 struct taskqueue *tq; 185 struct callout tick; 186 struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */ 187 struct sysctl_oid *oid_rxq; 188 struct sysctl_oid *oid_txq; 189 190 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 191 }; 192 193 struct fl_sdesc { 194 struct mbuf *m; 195 bus_dmamap_t map; 196 caddr_t cl; 197 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 198 #ifdef INVARIANTS 199 __be64 ba_tag; 200 #endif 201 }; 202 203 struct tx_desc { 204 __be64 flit[8]; 205 }; 206 207 struct tx_map { 208 struct mbuf *m; 209 bus_dmamap_t map; 210 }; 211 212 struct tx_sdesc { 213 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 214 uint8_t map_used; /* # of frames sent out in the WR */ 215 }; 216 217 typedef void (iq_intr_handler_t)(void *); 218 219 enum { 220 /* iq flags */ 221 IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ 222 IQ_STARTED = (1 << 2), /* started */ 223 }; 224 225 /* 226 * Ingress Queue: T4 is producer, driver is consumer. 227 */ 228 struct sge_iq { 229 bus_dma_tag_t desc_tag; 230 bus_dmamap_t desc_map; 231 bus_addr_t ba; /* bus address of descriptor ring */ 232 char lockname[16]; 233 uint32_t flags; 234 uint16_t abs_id; /* absolute SGE id for the iq */ 235 int8_t intr_pktc_idx; /* packet count threshold index */ 236 int8_t pad0; 237 iq_intr_handler_t *handler; 238 __be64 *desc; /* KVA of descriptor ring */ 239 240 struct mtx iq_lock; 241 struct adapter *adapter; 242 const __be64 *cdesc; /* current descriptor */ 243 uint8_t gen; /* generation bit */ 244 uint8_t intr_params; /* interrupt holdoff parameters */ 245 uint8_t intr_next; /* holdoff for next interrupt */ 246 uint8_t esize; /* size (bytes) of each entry in the queue */ 247 uint16_t qsize; /* size (# of entries) of the queue */ 248 uint16_t cidx; /* consumer index */ 249 uint16_t cntxt_id; /* SGE context id for the iq */ 250 }; 251 252 enum { 253 /* eq flags */ 254 EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ 255 EQ_STARTED = (1 << 2), /* started */ 256 EQ_STALLED = (1 << 3), /* currently stalled */ 257 }; 258 259 /* 260 * Egress Queue: driver is producer, T4 is consumer. 261 * 262 * Note: A free list is an egress queue (driver produces the buffers and T4 263 * consumes them) but it's special enough to have its own struct (see sge_fl). 264 */ 265 struct sge_eq { 266 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 267 bus_dma_tag_t desc_tag; 268 bus_dmamap_t desc_map; 269 char lockname[16]; 270 unsigned int flags; 271 struct mtx eq_lock; 272 273 struct tx_desc *desc; /* KVA of descriptor ring */ 274 bus_addr_t ba; /* bus address of descriptor ring */ 275 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 276 struct buf_ring *br; /* tx buffer ring */ 277 struct sge_qstat *spg; /* status page, for convenience */ 278 uint16_t cap; /* max # of desc, for convenience */ 279 uint16_t avail; /* available descriptors, for convenience */ 280 uint16_t qsize; /* size (# of entries) of the queue */ 281 uint16_t cidx; /* consumer idx (desc idx) */ 282 uint16_t pidx; /* producer idx (desc idx) */ 283 uint16_t pending; /* # of descriptors used since last doorbell */ 284 uint16_t iqid; /* iq that gets egr_update for the eq */ 285 uint32_t cntxt_id; /* SGE context id for the eq */ 286 287 /* DMA maps used for tx */ 288 struct tx_map *maps; 289 uint32_t map_total; /* # of DMA maps */ 290 uint32_t map_pidx; /* next map to be used */ 291 uint32_t map_cidx; /* reclaimed up to this index */ 292 uint32_t map_avail; /* # of available maps */ 293 } __aligned(CACHE_LINE_SIZE); 294 295 struct sge_fl { 296 bus_dma_tag_t desc_tag; 297 bus_dmamap_t desc_map; 298 bus_dma_tag_t tag[FL_BUF_SIZES]; 299 uint8_t tag_idx; 300 struct mtx fl_lock; 301 char lockname[16]; 302 303 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 304 bus_addr_t ba; /* bus address of descriptor ring */ 305 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 306 uint32_t cap; /* max # of buffers, for convenience */ 307 uint16_t qsize; /* size (# of entries) of the queue */ 308 uint16_t cntxt_id; /* SGE context id for the freelist */ 309 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 310 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 311 uint32_t needed; /* # of buffers needed to fill up fl. */ 312 uint32_t pending; /* # of bufs allocated since last doorbell */ 313 unsigned int dmamap_failed; 314 }; 315 316 /* txq: SGE egress queue + miscellaneous items */ 317 struct sge_txq { 318 struct sge_eq eq; /* MUST be first */ 319 struct mbuf *m; /* held up due to temporary resource shortage */ 320 struct task resume_tx; 321 322 struct ifnet *ifp; /* the interface this txq belongs to */ 323 324 /* stats for common events first */ 325 326 uint64_t txcsum; /* # of times hardware assisted with checksum */ 327 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 328 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 329 uint64_t imm_wrs; /* # of work requests with immediate data */ 330 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 331 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 332 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 333 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 334 335 /* stats for not-that-common events */ 336 337 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 338 uint32_t no_desc; /* out of hardware descriptors */ 339 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */ 340 }; 341 342 enum { 343 RXQ_LRO_ENABLED = (1 << 0) 344 }; 345 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 346 struct sge_rxq { 347 struct sge_iq iq; /* MUST be first */ 348 struct sge_fl fl; 349 350 struct ifnet *ifp; /* the interface this rxq belongs to */ 351 unsigned int flags; 352 #ifdef INET 353 struct lro_ctrl lro; /* LRO state */ 354 #endif 355 356 /* stats for common events first */ 357 358 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 359 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 360 361 /* stats for not-that-common events */ 362 363 } __aligned(CACHE_LINE_SIZE); 364 365 struct sge { 366 uint16_t timer_val[SGE_NTIMERS]; 367 uint8_t counter_val[SGE_NCOUNTERS]; 368 369 int nrxq; /* total rx queues (all ports and the rest) */ 370 int ntxq; /* total tx queues (all ports and the rest) */ 371 int niq; /* total ingress queues */ 372 int neq; /* total egress queues */ 373 374 struct sge_iq fwq; /* Firmware event queue */ 375 struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */ 376 struct sge_txq *txq; /* NIC tx queues */ 377 struct sge_rxq *rxq; /* NIC rx queues */ 378 379 uint16_t iq_start; 380 int eq_start; 381 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 382 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 383 }; 384 385 struct adapter { 386 device_t dev; 387 struct cdev *cdev; 388 389 /* PCIe register resources */ 390 int regs_rid; 391 struct resource *regs_res; 392 int msix_rid; 393 struct resource *msix_res; 394 bus_space_handle_t bh; 395 bus_space_tag_t bt; 396 bus_size_t mmio_len; 397 398 unsigned int pf; 399 unsigned int mbox; 400 401 /* Interrupt information */ 402 int intr_type; 403 int intr_count; 404 struct irq { 405 struct resource *res; 406 int rid; 407 void *tag; 408 } *irq; 409 410 bus_dma_tag_t dmat; /* Parent DMA tag */ 411 412 struct sge sge; 413 414 struct port_info *port[MAX_NPORTS]; 415 uint8_t chan_map[NCHAN]; 416 417 struct tid_info tids; 418 419 int registered_device_map; 420 int open_device_map; 421 int flags; 422 423 char fw_version[32]; 424 struct adapter_params params; 425 struct t4_virt_res vres; 426 427 struct mtx sc_lock; 428 char lockname[16]; 429 }; 430 431 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 432 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 433 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 434 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 435 436 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 437 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 438 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 439 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 440 441 #define IQ_LOCK(iq) mtx_lock(&(iq)->iq_lock) 442 #define IQ_UNLOCK(iq) mtx_unlock(&(iq)->iq_lock) 443 #define IQ_LOCK_ASSERT_OWNED(iq) mtx_assert(&(iq)->iq_lock, MA_OWNED) 444 #define IQ_LOCK_ASSERT_NOTOWNED(iq) mtx_assert(&(iq)->iq_lock, MA_NOTOWNED) 445 446 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 447 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 448 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 449 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 450 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 451 452 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 453 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 454 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 455 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 456 457 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 458 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 459 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 460 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 461 462 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 463 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 464 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 465 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 466 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 467 468 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 469 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 470 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 471 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 472 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 473 474 #define for_each_txq(pi, iter, txq) \ 475 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 476 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 477 #define for_each_rxq(pi, iter, rxq) \ 478 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 479 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 480 481 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 482 483 static inline uint32_t 484 t4_read_reg(struct adapter *sc, uint32_t reg) 485 { 486 return bus_space_read_4(sc->bt, sc->bh, reg); 487 } 488 489 static inline void 490 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 491 { 492 bus_space_write_4(sc->bt, sc->bh, reg, val); 493 } 494 495 static inline uint64_t 496 t4_read_reg64(struct adapter *sc, uint32_t reg) 497 { 498 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 499 } 500 501 static inline void 502 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 503 { 504 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 505 } 506 507 static inline void 508 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 509 { 510 *val = pci_read_config(sc->dev, reg, 1); 511 } 512 513 static inline void 514 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 515 { 516 pci_write_config(sc->dev, reg, val, 1); 517 } 518 519 static inline void 520 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 521 { 522 *val = pci_read_config(sc->dev, reg, 2); 523 } 524 525 static inline void 526 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 527 { 528 pci_write_config(sc->dev, reg, val, 2); 529 } 530 531 static inline void 532 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 533 { 534 *val = pci_read_config(sc->dev, reg, 4); 535 } 536 537 static inline void 538 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 539 { 540 pci_write_config(sc->dev, reg, val, 4); 541 } 542 543 static inline struct port_info * 544 adap2pinfo(struct adapter *sc, int idx) 545 { 546 return (sc->port[idx]); 547 } 548 549 static inline void 550 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 551 { 552 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 553 } 554 555 static inline bool is_10G_port(const struct port_info *pi) 556 { 557 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 558 } 559 560 /* t4_main.c */ 561 void cxgbe_txq_start(void *, int); 562 int t4_os_find_pci_capability(struct adapter *, int); 563 int t4_os_pci_save_state(struct adapter *); 564 int t4_os_pci_restore_state(struct adapter *); 565 void t4_os_portmod_changed(const struct adapter *, int); 566 void t4_os_link_changed(struct adapter *, int, int); 567 568 /* t4_sge.c */ 569 void t4_sge_modload(void); 570 void t4_sge_init(struct adapter *); 571 int t4_create_dma_tag(struct adapter *); 572 int t4_destroy_dma_tag(struct adapter *); 573 int t4_setup_adapter_iqs(struct adapter *); 574 int t4_teardown_adapter_iqs(struct adapter *); 575 int t4_setup_eth_queues(struct port_info *); 576 int t4_teardown_eth_queues(struct port_info *); 577 void t4_intr_all(void *); 578 void t4_intr_fwd(void *); 579 void t4_intr_err(void *); 580 void t4_intr_evt(void *); 581 void t4_intr_data(void *); 582 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 583 void t4_update_fl_bufsize(struct ifnet *); 584 585 #endif 586