1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/types.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/rwlock.h> 43 #include <sys/sx.h> 44 #include <sys/vmem.h> 45 #include <vm/uma.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <machine/bus.h> 50 #include <sys/socket.h> 51 #include <sys/sysctl.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <netinet/in.h> 57 #include <netinet/tcp_lro.h> 58 59 #include "offload.h" 60 #include "t4_ioctl.h" 61 #include "common/t4_msg.h" 62 #include "firmware/t4fw_interface.h" 63 64 #define KTR_CXGBE KTR_SPARE3 65 MALLOC_DECLARE(M_CXGBE); 66 #define CXGBE_UNIMPLEMENTED(s) \ 67 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 68 69 #if defined(__i386__) || defined(__amd64__) 70 static __inline void 71 prefetch(void *x) 72 { 73 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 74 } 75 #else 76 #define prefetch(x) __builtin_prefetch(x) 77 #endif 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 SYSCTL_DECL(_hw_cxgbe); 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 1024, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 120 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 121 }; 122 123 enum { 124 /* adapter intr_type */ 125 INTR_INTX = (1 << 0), 126 INTR_MSI = (1 << 1), 127 INTR_MSIX = (1 << 2) 128 }; 129 130 enum { 131 XGMAC_MTU = (1 << 0), 132 XGMAC_PROMISC = (1 << 1), 133 XGMAC_ALLMULTI = (1 << 2), 134 XGMAC_VLANEX = (1 << 3), 135 XGMAC_UCADDR = (1 << 4), 136 XGMAC_MCADDRS = (1 << 5), 137 138 XGMAC_ALL = 0xffff 139 }; 140 141 enum { 142 /* flags understood by begin_synchronized_op */ 143 HOLD_LOCK = (1 << 0), 144 SLEEP_OK = (1 << 1), 145 INTR_OK = (1 << 2), 146 147 /* flags understood by end_synchronized_op */ 148 LOCK_HELD = HOLD_LOCK, 149 }; 150 151 enum { 152 /* adapter flags */ 153 FULL_INIT_DONE = (1 << 0), 154 FW_OK = (1 << 1), 155 CHK_MBOX_ACCESS = (1 << 2), 156 MASTER_PF = (1 << 3), 157 ADAP_SYSCTL_CTX = (1 << 4), 158 /* TOM_INIT_DONE= (1 << 5), No longer used */ 159 BUF_PACKING_OK = (1 << 6), 160 IS_VF = (1 << 7), 161 162 CXGBE_BUSY = (1 << 9), 163 164 /* port flags */ 165 HAS_TRACEQ = (1 << 3), 166 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 167 168 /* VI flags */ 169 DOOMED = (1 << 0), 170 VI_INIT_DONE = (1 << 1), 171 VI_SYSCTL_CTX = (1 << 2), 172 173 /* adapter debug_flags */ 174 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 175 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 176 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 177 }; 178 179 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 180 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 181 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 182 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 183 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 184 185 struct vi_info { 186 device_t dev; 187 struct port_info *pi; 188 189 struct ifnet *ifp; 190 191 unsigned long flags; 192 int if_flags; 193 194 uint16_t *rss, *nm_rss; 195 int smt_idx; /* for convenience */ 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint16_t rss_base; /* start of VI's RSS table slice */ 200 int hashen; 201 202 int nintr; 203 int first_intr; 204 205 /* These need to be int as they are used in sysctl */ 206 int ntxq; /* # of tx queues */ 207 int first_txq; /* index of first tx queue */ 208 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 209 int nrxq; /* # of rx queues */ 210 int first_rxq; /* index of first rx queue */ 211 int nofldtxq; /* # of offload tx queues */ 212 int first_ofld_txq; /* index of first offload tx queue */ 213 int nofldrxq; /* # of offload rx queues */ 214 int first_ofld_rxq; /* index of first offload rx queue */ 215 int nnmtxq; 216 int first_nm_txq; 217 int nnmrxq; 218 int first_nm_rxq; 219 int tmr_idx; 220 int ofld_tmr_idx; 221 int pktc_idx; 222 int ofld_pktc_idx; 223 int qsize_rxq; 224 int qsize_txq; 225 226 struct timeval last_refreshed; 227 struct fw_vi_stats_vf stats; 228 229 struct callout tick; 230 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 231 232 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 233 }; 234 235 struct tx_ch_rl_params { 236 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 237 uint32_t maxrate; 238 }; 239 240 enum { 241 CLRL_USER = (1 << 0), /* allocated manually. */ 242 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 243 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 244 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 245 }; 246 247 struct tx_cl_rl_params { 248 int refcount; 249 uint8_t flags; 250 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 251 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 252 enum fw_sched_params_mode mode; /* aggr or per-flow */ 253 uint32_t maxrate; 254 uint16_t pktsize; 255 uint16_t burstsize; 256 }; 257 258 /* Tx scheduler parameters for a channel/port */ 259 struct tx_sched_params { 260 /* Channel Rate Limiter */ 261 struct tx_ch_rl_params ch_rl; 262 263 /* Class WRR */ 264 /* XXX */ 265 266 /* Class Rate Limiter (including the default pktsize and burstsize). */ 267 int pktsize; 268 int burstsize; 269 struct tx_cl_rl_params cl_rl[]; 270 }; 271 272 struct port_info { 273 device_t dev; 274 struct adapter *adapter; 275 276 struct vi_info *vi; 277 int nvi; 278 int up_vis; 279 int uld_vis; 280 281 struct tx_sched_params *sched_params; 282 283 struct mtx pi_lock; 284 char lockname[16]; 285 unsigned long flags; 286 287 uint8_t lport; /* associated offload logical port */ 288 int8_t mdio_addr; 289 uint8_t port_type; 290 uint8_t mod_type; 291 uint8_t port_id; 292 uint8_t tx_chan; 293 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 294 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 295 296 struct link_config link_cfg; 297 struct ifmedia media; 298 299 struct timeval last_refreshed; 300 struct port_stats stats; 301 u_int tnl_cong_drops; 302 u_int tx_parse_error; 303 u_long tx_tls_records; 304 u_long tx_tls_octets; 305 u_long rx_tls_records; 306 u_long rx_tls_octets; 307 308 struct callout tick; 309 }; 310 311 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 312 313 /* Where the cluster came from, how it has been carved up. */ 314 struct cluster_layout { 315 int8_t zidx; 316 int8_t hwidx; 317 uint16_t region1; /* mbufs laid out within this region */ 318 /* region2 is the DMA region */ 319 uint16_t region3; /* cluster_metadata within this region */ 320 }; 321 322 struct cluster_metadata { 323 u_int refcount; 324 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 325 }; 326 327 struct fl_sdesc { 328 caddr_t cl; 329 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 330 struct cluster_layout cll; 331 }; 332 333 struct tx_desc { 334 __be64 flit[8]; 335 }; 336 337 struct tx_sdesc { 338 struct mbuf *m; /* m_nextpkt linked chain of frames */ 339 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 340 }; 341 342 343 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 344 struct iq_desc { 345 struct rss_header rss; 346 uint8_t cpl[IQ_PAD]; 347 struct rsp_ctrl rsp; 348 }; 349 #undef IQ_PAD 350 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 351 352 enum { 353 /* iq flags */ 354 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 355 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 356 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 357 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 358 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 359 360 /* iq state */ 361 IQS_DISABLED = 0, 362 IQS_BUSY = 1, 363 IQS_IDLE = 2, 364 365 /* netmap related flags */ 366 NM_OFF = 0, 367 NM_ON = 1, 368 NM_BUSY = 2, 369 }; 370 371 enum { 372 CPL_COOKIE_RESERVED = 0, 373 CPL_COOKIE_FILTER, 374 CPL_COOKIE_DDP0, 375 CPL_COOKIE_DDP1, 376 CPL_COOKIE_TOM, 377 CPL_COOKIE_HASHFILTER, 378 CPL_COOKIE_ETHOFLD, 379 CPL_COOKIE_AVAILABLE3, 380 381 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 382 }; 383 384 struct sge_iq; 385 struct rss_header; 386 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 387 struct mbuf *); 388 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 389 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 390 391 /* 392 * Ingress Queue: T4 is producer, driver is consumer. 393 */ 394 struct sge_iq { 395 uint32_t flags; 396 volatile int state; 397 struct adapter *adapter; 398 struct iq_desc *desc; /* KVA of descriptor ring */ 399 int8_t intr_pktc_idx; /* packet count threshold index */ 400 uint8_t gen; /* generation bit */ 401 uint8_t intr_params; /* interrupt holdoff parameters */ 402 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 403 uint16_t qsize; /* size (# of entries) of the queue */ 404 uint16_t sidx; /* index of the entry with the status page */ 405 uint16_t cidx; /* consumer index */ 406 uint16_t cntxt_id; /* SGE context id for the iq */ 407 uint16_t abs_id; /* absolute SGE id for the iq */ 408 409 STAILQ_ENTRY(sge_iq) link; 410 411 bus_dma_tag_t desc_tag; 412 bus_dmamap_t desc_map; 413 bus_addr_t ba; /* bus address of descriptor ring */ 414 }; 415 416 enum { 417 EQ_CTRL = 1, 418 EQ_ETH = 2, 419 EQ_OFLD = 3, 420 421 /* eq flags */ 422 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 423 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 424 EQ_ENABLED = (1 << 3), /* open for business */ 425 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 426 }; 427 428 /* Listed in order of preference. Update t4_sysctls too if you change these */ 429 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 430 431 /* 432 * Egress Queue: driver is producer, T4 is consumer. 433 * 434 * Note: A free list is an egress queue (driver produces the buffers and T4 435 * consumes them) but it's special enough to have its own struct (see sge_fl). 436 */ 437 struct sge_eq { 438 unsigned int flags; /* MUST be first */ 439 unsigned int cntxt_id; /* SGE context id for the eq */ 440 unsigned int abs_id; /* absolute SGE id for the eq */ 441 struct mtx eq_lock; 442 443 struct tx_desc *desc; /* KVA of descriptor ring */ 444 uint8_t doorbells; 445 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 446 u_int udb_qid; /* relative qid within the doorbell page */ 447 uint16_t sidx; /* index of the entry with the status page */ 448 uint16_t cidx; /* consumer idx (desc idx) */ 449 uint16_t pidx; /* producer idx (desc idx) */ 450 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 451 uint16_t dbidx; /* pidx of the most recent doorbell */ 452 uint16_t iqid; /* iq that gets egr_update for the eq */ 453 uint8_t tx_chan; /* tx channel used by the eq */ 454 volatile u_int equiq; /* EQUIQ outstanding */ 455 456 bus_dma_tag_t desc_tag; 457 bus_dmamap_t desc_map; 458 bus_addr_t ba; /* bus address of descriptor ring */ 459 char lockname[16]; 460 }; 461 462 struct sw_zone_info { 463 uma_zone_t zone; /* zone that this cluster comes from */ 464 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 465 int type; /* EXT_xxx type of the cluster */ 466 int8_t head_hwidx; 467 int8_t tail_hwidx; 468 }; 469 470 struct hw_buf_info { 471 int8_t zidx; /* backpointer to zone; -ve means unused */ 472 int8_t next; /* next hwidx for this zone; -1 means no more */ 473 int size; 474 }; 475 476 enum { 477 NUM_MEMWIN = 3, 478 479 MEMWIN0_APERTURE = 2048, 480 MEMWIN0_BASE = 0x1b800, 481 482 MEMWIN1_APERTURE = 32768, 483 MEMWIN1_BASE = 0x28000, 484 485 MEMWIN2_APERTURE_T4 = 65536, 486 MEMWIN2_BASE_T4 = 0x30000, 487 488 MEMWIN2_APERTURE_T5 = 128 * 1024, 489 MEMWIN2_BASE_T5 = 0x60000, 490 }; 491 492 struct memwin { 493 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 494 uint32_t mw_base; /* constant after setup_memwin */ 495 uint32_t mw_aperture; /* ditto */ 496 uint32_t mw_curpos; /* protected by mw_lock */ 497 }; 498 499 enum { 500 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 501 FL_DOOMED = (1 << 1), /* about to be destroyed */ 502 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 503 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 504 }; 505 506 #define FL_RUNNING_LOW(fl) \ 507 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 508 #define FL_NOT_RUNNING_LOW(fl) \ 509 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 510 511 struct sge_fl { 512 struct mtx fl_lock; 513 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 514 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 515 struct cluster_layout cll_def; /* default refill zone, layout */ 516 uint16_t lowat; /* # of buffers <= this means fl needs help */ 517 int flags; 518 uint16_t buf_boundary; 519 520 /* The 16b idx all deal with hw descriptors */ 521 uint16_t dbidx; /* hw pidx after last doorbell */ 522 uint16_t sidx; /* index of status page */ 523 volatile uint16_t hw_cidx; 524 525 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 526 uint32_t cidx; /* consumer index */ 527 uint32_t pidx; /* producer index */ 528 529 uint32_t dbval; 530 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 531 volatile uint32_t *udb; 532 533 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 534 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 535 uint64_t cl_allocated; /* # of clusters allocated */ 536 uint64_t cl_recycled; /* # of clusters recycled */ 537 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 538 539 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 540 struct mbuf *m0; 541 struct mbuf **pnext; 542 u_int remaining; 543 544 uint16_t qsize; /* # of hw descriptors (status page included) */ 545 uint16_t cntxt_id; /* SGE context id for the freelist */ 546 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 547 bus_dma_tag_t desc_tag; 548 bus_dmamap_t desc_map; 549 char lockname[16]; 550 bus_addr_t ba; /* bus address of descriptor ring */ 551 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 552 }; 553 554 struct mp_ring; 555 556 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 557 struct sge_txq { 558 struct sge_eq eq; /* MUST be first */ 559 560 struct ifnet *ifp; /* the interface this txq belongs to */ 561 struct mp_ring *r; /* tx software ring */ 562 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 563 struct sglist *gl; 564 __be32 cpl_ctrl0; /* for convenience */ 565 int tc_idx; /* traffic class */ 566 567 struct task tx_reclaim_task; 568 /* stats for common events first */ 569 570 uint64_t txcsum; /* # of times hardware assisted with checksum */ 571 uint64_t tso_wrs; /* # of TSO work requests */ 572 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 573 uint64_t imm_wrs; /* # of work requests with immediate data */ 574 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 575 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 576 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 577 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 578 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 579 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 580 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 581 582 /* stats for not-that-common events */ 583 } __aligned(CACHE_LINE_SIZE); 584 585 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 586 struct sge_rxq { 587 struct sge_iq iq; /* MUST be first */ 588 struct sge_fl fl; /* MUST follow iq */ 589 590 struct ifnet *ifp; /* the interface this rxq belongs to */ 591 #if defined(INET) || defined(INET6) 592 struct lro_ctrl lro; /* LRO state */ 593 #endif 594 595 /* stats for common events first */ 596 597 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 598 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 599 600 /* stats for not-that-common events */ 601 602 } __aligned(CACHE_LINE_SIZE); 603 604 static inline struct sge_rxq * 605 iq_to_rxq(struct sge_iq *iq) 606 { 607 608 return (__containerof(iq, struct sge_rxq, iq)); 609 } 610 611 612 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 613 struct sge_ofld_rxq { 614 struct sge_iq iq; /* MUST be first */ 615 struct sge_fl fl; /* MUST follow iq */ 616 } __aligned(CACHE_LINE_SIZE); 617 618 static inline struct sge_ofld_rxq * 619 iq_to_ofld_rxq(struct sge_iq *iq) 620 { 621 622 return (__containerof(iq, struct sge_ofld_rxq, iq)); 623 } 624 625 struct wrqe { 626 STAILQ_ENTRY(wrqe) link; 627 struct sge_wrq *wrq; 628 int wr_len; 629 char wr[] __aligned(16); 630 }; 631 632 struct wrq_cookie { 633 TAILQ_ENTRY(wrq_cookie) link; 634 int ndesc; 635 int pidx; 636 }; 637 638 /* 639 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 640 * and offload tx queues are of this type. 641 */ 642 struct sge_wrq { 643 struct sge_eq eq; /* MUST be first */ 644 645 struct adapter *adapter; 646 struct task wrq_tx_task; 647 648 /* Tx desc reserved but WR not "committed" yet. */ 649 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 650 651 /* List of WRs ready to go out as soon as descriptors are available. */ 652 STAILQ_HEAD(, wrqe) wr_list; 653 u_int nwr_pending; 654 u_int ndesc_needed; 655 656 /* stats for common events first */ 657 658 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 659 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 660 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 661 662 /* stats for not-that-common events */ 663 664 /* 665 * Scratch space for work requests that wrap around after reaching the 666 * status page, and some information about the last WR that used it. 667 */ 668 uint16_t ss_pidx; 669 uint16_t ss_len; 670 uint8_t ss[SGE_MAX_WR_LEN]; 671 672 } __aligned(CACHE_LINE_SIZE); 673 674 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 675 struct sge_nm_rxq { 676 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 677 struct vi_info *vi; 678 679 struct iq_desc *iq_desc; 680 uint16_t iq_abs_id; 681 uint16_t iq_cntxt_id; 682 uint16_t iq_cidx; 683 uint16_t iq_sidx; 684 uint8_t iq_gen; 685 686 __be64 *fl_desc; 687 uint16_t fl_cntxt_id; 688 uint32_t fl_cidx; 689 uint32_t fl_pidx; 690 uint32_t fl_sidx; 691 uint32_t fl_db_val; 692 u_int fl_hwidx:4; 693 694 u_int fl_db_saved; 695 u_int nid; /* netmap ring # for this queue */ 696 697 /* infrequently used items after this */ 698 699 bus_dma_tag_t iq_desc_tag; 700 bus_dmamap_t iq_desc_map; 701 bus_addr_t iq_ba; 702 int intr_idx; 703 704 bus_dma_tag_t fl_desc_tag; 705 bus_dmamap_t fl_desc_map; 706 bus_addr_t fl_ba; 707 } __aligned(CACHE_LINE_SIZE); 708 709 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 710 struct sge_nm_txq { 711 struct tx_desc *desc; 712 uint16_t cidx; 713 uint16_t pidx; 714 uint16_t sidx; 715 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 716 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 717 uint16_t dbidx; /* pidx of the most recent doorbell */ 718 uint8_t doorbells; 719 volatile uint32_t *udb; 720 u_int udb_qid; 721 u_int cntxt_id; 722 __be32 cpl_ctrl0; /* for convenience */ 723 u_int nid; /* netmap ring # for this queue */ 724 725 /* infrequently used items after this */ 726 727 bus_dma_tag_t desc_tag; 728 bus_dmamap_t desc_map; 729 bus_addr_t ba; 730 int iqidx; 731 } __aligned(CACHE_LINE_SIZE); 732 733 struct sge { 734 int nrxq; /* total # of Ethernet rx queues */ 735 int ntxq; /* total # of Ethernet tx queues */ 736 int nofldrxq; /* total # of TOE rx queues */ 737 int nofldtxq; /* total # of TOE tx queues */ 738 int nnmrxq; /* total # of netmap rx queues */ 739 int nnmtxq; /* total # of netmap tx queues */ 740 int niq; /* total # of ingress queues */ 741 int neq; /* total # of egress queues */ 742 743 struct sge_iq fwq; /* Firmware event queue */ 744 struct sge_wrq *ctrlq; /* Control queues */ 745 struct sge_txq *txq; /* NIC tx queues */ 746 struct sge_rxq *rxq; /* NIC rx queues */ 747 struct sge_wrq *ofld_txq; /* TOE tx queues */ 748 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 749 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 750 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 751 752 uint16_t iq_start; /* first cntxt_id */ 753 uint16_t iq_base; /* first abs_id */ 754 int eq_start; /* first cntxt_id */ 755 int eq_base; /* first abs_id */ 756 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 757 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 758 759 int8_t safe_hwidx1; /* may not have room for metadata */ 760 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 761 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 762 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 763 }; 764 765 struct devnames { 766 const char *nexus_name; 767 const char *ifnet_name; 768 const char *vi_ifnet_name; 769 const char *pf03_drv_name; 770 const char *vf_nexus_name; 771 const char *vf_ifnet_name; 772 }; 773 774 struct clip_entry; 775 776 struct adapter { 777 SLIST_ENTRY(adapter) link; 778 device_t dev; 779 struct cdev *cdev; 780 const struct devnames *names; 781 782 /* PCIe register resources */ 783 int regs_rid; 784 struct resource *regs_res; 785 int msix_rid; 786 struct resource *msix_res; 787 bus_space_handle_t bh; 788 bus_space_tag_t bt; 789 bus_size_t mmio_len; 790 int udbs_rid; 791 struct resource *udbs_res; 792 volatile uint8_t *udbs_base; 793 794 unsigned int pf; 795 unsigned int mbox; 796 unsigned int vpd_busy; 797 unsigned int vpd_flag; 798 799 /* Interrupt information */ 800 int intr_type; 801 int intr_count; 802 struct irq { 803 struct resource *res; 804 int rid; 805 void *tag; 806 struct sge_rxq *rxq; 807 struct sge_nm_rxq *nm_rxq; 808 } __aligned(CACHE_LINE_SIZE) *irq; 809 int sge_gts_reg; 810 int sge_kdoorbell_reg; 811 812 bus_dma_tag_t dmat; /* Parent DMA tag */ 813 814 struct sge sge; 815 int lro_timeout; 816 int sc_do_rxcopy; 817 818 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 819 struct port_info *port[MAX_NPORTS]; 820 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 821 822 struct mtx clip_table_lock; 823 TAILQ_HEAD(, clip_entry) clip_table; 824 int clip_gen; 825 826 void *tom_softc; /* (struct tom_data *) */ 827 struct tom_tunables tt; 828 struct t4_offload_policy *policy; 829 struct rwlock policy_lock; 830 831 void *iwarp_softc; /* (struct c4iw_dev *) */ 832 struct iw_tunables iwt; 833 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 834 void *ccr_softc; /* (struct ccr_softc *) */ 835 struct l2t_data *l2t; /* L2 table */ 836 struct smt_data *smt; /* Source MAC Table */ 837 struct tid_info tids; 838 vmem_t *key_map; 839 840 uint8_t doorbells; 841 int offload_map; /* ports with IFCAP_TOE enabled */ 842 int active_ulds; /* ULDs activated on this adapter */ 843 int flags; 844 int debug_flags; 845 846 char ifp_lockname[16]; 847 struct mtx ifp_lock; 848 struct ifnet *ifp; /* tracer ifp */ 849 struct ifmedia media; 850 int traceq; /* iq used by all tracers, -1 if none */ 851 int tracer_valid; /* bitmap of valid tracers */ 852 int tracer_enabled; /* bitmap of enabled tracers */ 853 854 char fw_version[16]; 855 char tp_version[16]; 856 char er_version[16]; 857 char bs_version[16]; 858 char cfg_file[32]; 859 u_int cfcsum; 860 struct adapter_params params; 861 const struct chip_params *chip_params; 862 struct t4_virt_res vres; 863 864 uint16_t nbmcaps; 865 uint16_t linkcaps; 866 uint16_t switchcaps; 867 uint16_t niccaps; 868 uint16_t toecaps; 869 uint16_t rdmacaps; 870 uint16_t cryptocaps; 871 uint16_t iscsicaps; 872 uint16_t fcoecaps; 873 874 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 875 876 struct mtx sc_lock; 877 char lockname[16]; 878 879 /* Starving free lists */ 880 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 881 TAILQ_HEAD(, sge_fl) sfl; 882 struct callout sfl_callout; 883 884 struct mtx reg_lock; /* for indirect register access */ 885 886 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 887 888 struct mtx tc_lock; 889 struct task tc_task; 890 891 const char *last_op; 892 const void *last_op_thr; 893 int last_op_flags; 894 }; 895 896 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 897 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 898 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 899 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 900 901 #define ASSERT_SYNCHRONIZED_OP(sc) \ 902 KASSERT(IS_BUSY(sc) && \ 903 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 904 ("%s: operation not synchronized.", __func__)) 905 906 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 907 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 908 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 909 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 910 911 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 912 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 913 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 914 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 915 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 916 917 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 918 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 919 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 920 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 921 922 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 923 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 924 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 925 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 926 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 927 928 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 929 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 930 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 931 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 932 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 933 934 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 935 do { \ 936 if (sc->debug_flags & DF_DUMP_MBOX) { \ 937 log(LOG_NOTICE, \ 938 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 939 "%016llx %016llx %016llx %016llx\n", \ 940 device_get_nameunit(sc->dev), mbox, \ 941 (unsigned long long)t4_read_reg64(sc, data_reg), \ 942 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 943 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 944 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 945 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 946 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 947 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 948 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 949 } \ 950 } while (0) 951 952 #define for_each_txq(vi, iter, q) \ 953 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 954 iter < vi->ntxq; ++iter, ++q) 955 #define for_each_rxq(vi, iter, q) \ 956 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 957 iter < vi->nrxq; ++iter, ++q) 958 #define for_each_ofld_txq(vi, iter, q) \ 959 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 960 iter < vi->nofldtxq; ++iter, ++q) 961 #define for_each_ofld_rxq(vi, iter, q) \ 962 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 963 iter < vi->nofldrxq; ++iter, ++q) 964 #define for_each_nm_txq(vi, iter, q) \ 965 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 966 iter < vi->nnmtxq; ++iter, ++q) 967 #define for_each_nm_rxq(vi, iter, q) \ 968 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 969 iter < vi->nnmrxq; ++iter, ++q) 970 #define for_each_vi(_pi, _iter, _vi) \ 971 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 972 ++(_iter), ++(_vi)) 973 974 #define IDXINCR(idx, incr, wrap) do { \ 975 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 976 } while (0) 977 #define IDXDIFF(head, tail, wrap) \ 978 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 979 980 /* One for errors, one for firmware events */ 981 #define T4_EXTRA_INTR 2 982 983 /* One for firmware events */ 984 #define T4VF_EXTRA_INTR 1 985 986 static inline int 987 forwarding_intr_to_fwq(struct adapter *sc) 988 { 989 990 return (sc->intr_count == 1); 991 } 992 993 static inline uint32_t 994 t4_read_reg(struct adapter *sc, uint32_t reg) 995 { 996 997 return bus_space_read_4(sc->bt, sc->bh, reg); 998 } 999 1000 static inline void 1001 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1002 { 1003 1004 bus_space_write_4(sc->bt, sc->bh, reg, val); 1005 } 1006 1007 static inline uint64_t 1008 t4_read_reg64(struct adapter *sc, uint32_t reg) 1009 { 1010 1011 #ifdef __LP64__ 1012 return bus_space_read_8(sc->bt, sc->bh, reg); 1013 #else 1014 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1015 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1016 1017 #endif 1018 } 1019 1020 static inline void 1021 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1022 { 1023 1024 #ifdef __LP64__ 1025 bus_space_write_8(sc->bt, sc->bh, reg, val); 1026 #else 1027 bus_space_write_4(sc->bt, sc->bh, reg, val); 1028 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1029 #endif 1030 } 1031 1032 static inline void 1033 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1034 { 1035 1036 *val = pci_read_config(sc->dev, reg, 1); 1037 } 1038 1039 static inline void 1040 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1041 { 1042 1043 pci_write_config(sc->dev, reg, val, 1); 1044 } 1045 1046 static inline void 1047 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1048 { 1049 1050 *val = pci_read_config(sc->dev, reg, 2); 1051 } 1052 1053 static inline void 1054 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1055 { 1056 1057 pci_write_config(sc->dev, reg, val, 2); 1058 } 1059 1060 static inline void 1061 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1062 { 1063 1064 *val = pci_read_config(sc->dev, reg, 4); 1065 } 1066 1067 static inline void 1068 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1069 { 1070 1071 pci_write_config(sc->dev, reg, val, 4); 1072 } 1073 1074 static inline struct port_info * 1075 adap2pinfo(struct adapter *sc, int idx) 1076 { 1077 1078 return (sc->port[idx]); 1079 } 1080 1081 static inline void 1082 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1083 { 1084 1085 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1086 } 1087 1088 static inline int 1089 tx_resume_threshold(struct sge_eq *eq) 1090 { 1091 1092 /* not quite the same as qsize / 4, but this will do. */ 1093 return (eq->sidx / 4); 1094 } 1095 1096 static inline int 1097 t4_use_ldst(struct adapter *sc) 1098 { 1099 1100 #ifdef notyet 1101 return (sc->flags & FW_OK || !sc->use_bd); 1102 #else 1103 return (0); 1104 #endif 1105 } 1106 1107 /* t4_main.c */ 1108 extern int t4_ntxq; 1109 extern int t4_nrxq; 1110 extern int t4_intr_types; 1111 extern int t4_tmr_idx; 1112 extern int t4_pktc_idx; 1113 extern unsigned int t4_qsize_rxq; 1114 extern unsigned int t4_qsize_txq; 1115 extern device_method_t cxgbe_methods[]; 1116 1117 int t4_os_find_pci_capability(struct adapter *, int); 1118 int t4_os_pci_save_state(struct adapter *); 1119 int t4_os_pci_restore_state(struct adapter *); 1120 void t4_os_portmod_changed(struct port_info *); 1121 void t4_os_link_changed(struct port_info *); 1122 void t4_iterate(void (*)(struct adapter *, void *), void *); 1123 void t4_init_devnames(struct adapter *); 1124 void t4_add_adapter(struct adapter *); 1125 void t4_aes_getdeckey(void *, const void *, unsigned int); 1126 int t4_detach_common(device_t); 1127 int t4_map_bars_0_and_4(struct adapter *); 1128 int t4_map_bar_2(struct adapter *); 1129 int t4_setup_intr_handlers(struct adapter *); 1130 void t4_sysctls(struct adapter *); 1131 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1132 void doom_vi(struct adapter *, struct vi_info *); 1133 void end_synchronized_op(struct adapter *, int); 1134 int update_mac_settings(struct ifnet *, int); 1135 int adapter_full_init(struct adapter *); 1136 int adapter_full_uninit(struct adapter *); 1137 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1138 int vi_full_init(struct vi_info *); 1139 int vi_full_uninit(struct vi_info *); 1140 void vi_sysctls(struct vi_info *); 1141 void vi_tick(void *); 1142 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1143 int alloc_atid_tab(struct tid_info *, int); 1144 void free_atid_tab(struct tid_info *); 1145 int alloc_atid(struct adapter *, void *); 1146 void *lookup_atid(struct adapter *, int); 1147 void free_atid(struct adapter *, int); 1148 void release_tid(struct adapter *, int, struct sge_wrq *); 1149 int cxgbe_media_change(struct ifnet *); 1150 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1151 1152 #ifdef DEV_NETMAP 1153 /* t4_netmap.c */ 1154 struct sge_nm_rxq; 1155 void cxgbe_nm_attach(struct vi_info *); 1156 void cxgbe_nm_detach(struct vi_info *); 1157 void service_nm_rxq(struct sge_nm_rxq *); 1158 #endif 1159 1160 /* t4_sge.c */ 1161 void t4_sge_modload(void); 1162 void t4_sge_modunload(void); 1163 uint64_t t4_sge_extfree_refs(void); 1164 void t4_tweak_chip_settings(struct adapter *); 1165 int t4_read_chip_settings(struct adapter *); 1166 int t4_create_dma_tag(struct adapter *); 1167 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1168 struct sysctl_oid_list *); 1169 int t4_destroy_dma_tag(struct adapter *); 1170 int t4_setup_adapter_queues(struct adapter *); 1171 int t4_teardown_adapter_queues(struct adapter *); 1172 int t4_setup_vi_queues(struct vi_info *); 1173 int t4_teardown_vi_queues(struct vi_info *); 1174 void t4_intr_all(void *); 1175 void t4_intr(void *); 1176 #ifdef DEV_NETMAP 1177 void t4_nm_intr(void *); 1178 void t4_vi_intr(void *); 1179 #endif 1180 void t4_intr_err(void *); 1181 void t4_intr_evt(void *); 1182 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1183 void t4_update_fl_bufsize(struct ifnet *); 1184 struct mbuf *alloc_wr_mbuf(int, int); 1185 int parse_pkt(struct adapter *, struct mbuf **); 1186 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1187 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1188 int tnl_cong(struct port_info *, int); 1189 void t4_register_an_handler(an_handler_t); 1190 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1191 void t4_register_cpl_handler(int, cpl_handler_t); 1192 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1193 #ifdef RATELIMIT 1194 int ethofld_transmit(struct ifnet *, struct mbuf *); 1195 void send_etid_flush_wr(struct cxgbe_snd_tag *); 1196 #endif 1197 1198 /* t4_tracer.c */ 1199 struct t4_tracer; 1200 void t4_tracer_modload(void); 1201 void t4_tracer_modunload(void); 1202 void t4_tracer_port_detach(struct adapter *); 1203 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1204 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1205 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1206 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1207 1208 /* t4_sched.c */ 1209 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1210 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1211 int t4_init_tx_sched(struct adapter *); 1212 int t4_free_tx_sched(struct adapter *); 1213 void t4_update_tx_sched(struct adapter *); 1214 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1215 void t4_release_cl_rl(struct adapter *, int, int); 1216 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1217 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1218 #ifdef RATELIMIT 1219 void t4_init_etid_table(struct adapter *); 1220 void t4_free_etid_table(struct adapter *); 1221 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int); 1222 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1223 struct m_snd_tag **); 1224 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1225 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1226 void cxgbe_snd_tag_free(struct m_snd_tag *); 1227 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *); 1228 #endif 1229 1230 /* t4_filter.c */ 1231 int get_filter_mode(struct adapter *, uint32_t *); 1232 int set_filter_mode(struct adapter *, uint32_t); 1233 int get_filter(struct adapter *, struct t4_filter *); 1234 int set_filter(struct adapter *, struct t4_filter *); 1235 int del_filter(struct adapter *, struct t4_filter *); 1236 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1237 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1238 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1239 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1240 void free_hftid_hash(struct tid_info *); 1241 1242 static inline struct wrqe * 1243 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1244 { 1245 int len = offsetof(struct wrqe, wr) + wr_len; 1246 struct wrqe *wr; 1247 1248 wr = malloc(len, M_CXGBE, M_NOWAIT); 1249 if (__predict_false(wr == NULL)) 1250 return (NULL); 1251 wr->wr_len = wr_len; 1252 wr->wrq = wrq; 1253 return (wr); 1254 } 1255 1256 static inline void * 1257 wrtod(struct wrqe *wr) 1258 { 1259 return (&wr->wr[0]); 1260 } 1261 1262 static inline void 1263 free_wrqe(struct wrqe *wr) 1264 { 1265 free(wr, M_CXGBE); 1266 } 1267 1268 static inline void 1269 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1270 { 1271 struct sge_wrq *wrq = wr->wrq; 1272 1273 TXQ_LOCK(wrq); 1274 t4_wrq_tx_locked(sc, wrq, wr); 1275 TXQ_UNLOCK(wrq); 1276 } 1277 1278 static inline int 1279 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1280 int len) 1281 { 1282 1283 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1284 } 1285 1286 static inline int 1287 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1288 const uint32_t *val, int len) 1289 { 1290 1291 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1292 } 1293 #endif 1294