1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/in.h> 48 #include <netinet/tcp_lro.h> 49 50 #include "offload.h" 51 #include "firmware/t4fw_interface.h" 52 53 #define T4_CFGNAME "t4fw_cfg" 54 #define T4_FWNAME "t4fw" 55 56 MALLOC_DECLARE(M_CXGBE); 57 #define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60 #if defined(__i386__) || defined(__amd64__) 61 static __inline void 62 prefetch(void *x) 63 { 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65 } 66 #else 67 #define prefetch(x) 68 #endif 69 70 #ifndef SYSCTL_ADD_UQUAD 71 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72 #define sysctl_handle_64 sysctl_handle_quad 73 #define CTLTYPE_U64 CTLTYPE_QUAD 74 #endif 75 76 #if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78 #define SBUF_DRAIN 1 79 #endif 80 81 #ifdef __amd64__ 82 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 83 static __inline uint64_t 84 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 85 bus_size_t offset) 86 { 87 KASSERT(tag == X86_BUS_SPACE_MEM, 88 ("%s: can only handle mem space", __func__)); 89 90 return (*(volatile uint64_t *)(handle + offset)); 91 } 92 93 static __inline void 94 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 95 bus_size_t offset, uint64_t value) 96 { 97 KASSERT(tag == X86_BUS_SPACE_MEM, 98 ("%s: can only handle mem space", __func__)); 99 100 *(volatile uint64_t *)(bsh + offset) = value; 101 } 102 #else 103 static __inline uint64_t 104 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 105 bus_size_t offset) 106 { 107 return (uint64_t)bus_space_read_4(tag, handle, offset) + 108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 109 } 110 111 static __inline void 112 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 113 bus_size_t offset, uint64_t value) 114 { 115 bus_space_write_4(tag, bsh, offset, value); 116 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 117 } 118 #endif 119 120 struct adapter; 121 typedef struct adapter adapter_t; 122 123 enum { 124 FW_IQ_QSIZE = 256, 125 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 126 127 RX_IQ_QSIZE = 1024, 128 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 129 130 EQ_ESIZE = 64, /* All egress queues use this entry size */ 131 132 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 133 #if MJUMPAGESIZE != MCLBYTES 134 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 135 #else 136 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 137 #endif 138 OFLD_BUF_SIZE = MJUM16BYTES, /* size of fl buffer for TOE rxq */ 139 140 CTRL_EQ_QSIZE = 128, 141 142 TX_EQ_QSIZE = 1024, 143 TX_SGL_SEGS = 36, 144 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 145 }; 146 147 #ifdef T4_PKT_TIMESTAMP 148 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 149 #else 150 #define RX_COPY_THRESHOLD MINCLSIZE 151 #endif 152 153 enum { 154 /* adapter intr_type */ 155 INTR_INTX = (1 << 0), 156 INTR_MSI = (1 << 1), 157 INTR_MSIX = (1 << 2) 158 }; 159 160 enum { 161 /* adapter flags */ 162 FULL_INIT_DONE = (1 << 0), 163 FW_OK = (1 << 1), 164 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 165 MASTER_PF = (1 << 3), 166 ADAP_SYSCTL_CTX = (1 << 4), 167 TOM_INIT_DONE = (1 << 5), 168 169 CXGBE_BUSY = (1 << 9), 170 171 /* port flags */ 172 DOOMED = (1 << 0), 173 PORT_INIT_DONE = (1 << 1), 174 PORT_SYSCTL_CTX = (1 << 2), 175 }; 176 177 #define IS_DOOMED(pi) (pi->flags & DOOMED) 178 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 179 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 180 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 181 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 182 183 struct port_info { 184 device_t dev; 185 struct adapter *adapter; 186 187 struct ifnet *ifp; 188 struct ifmedia media; 189 190 struct mtx pi_lock; 191 char lockname[16]; 192 unsigned long flags; 193 int if_flags; 194 195 uint16_t viid; 196 int16_t xact_addr_filt;/* index of exact MAC address filter */ 197 uint16_t rss_size; /* size of VI's RSS table slice */ 198 uint8_t lport; /* associated offload logical port */ 199 int8_t mdio_addr; 200 uint8_t port_type; 201 uint8_t mod_type; 202 uint8_t port_id; 203 uint8_t tx_chan; 204 205 /* These need to be int as they are used in sysctl */ 206 int ntxq; /* # of tx queues */ 207 int first_txq; /* index of first tx queue */ 208 int nrxq; /* # of rx queues */ 209 int first_rxq; /* index of first rx queue */ 210 #ifdef TCP_OFFLOAD 211 int nofldtxq; /* # of offload tx queues */ 212 int first_ofld_txq; /* index of first offload tx queue */ 213 int nofldrxq; /* # of offload rx queues */ 214 int first_ofld_rxq; /* index of first offload rx queue */ 215 #endif 216 int tmr_idx; 217 int pktc_idx; 218 int qsize_rxq; 219 int qsize_txq; 220 221 struct link_config link_cfg; 222 struct port_stats stats; 223 224 eventhandler_tag vlan_c; 225 226 struct callout tick; 227 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 228 229 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 230 }; 231 232 struct fl_sdesc { 233 struct mbuf *m; 234 bus_dmamap_t map; 235 caddr_t cl; 236 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 237 #ifdef INVARIANTS 238 __be64 ba_tag; 239 #endif 240 }; 241 242 struct tx_desc { 243 __be64 flit[8]; 244 }; 245 246 struct tx_map { 247 struct mbuf *m; 248 bus_dmamap_t map; 249 }; 250 251 /* DMA maps used for tx */ 252 struct tx_maps { 253 struct tx_map *maps; 254 uint32_t map_total; /* # of DMA maps */ 255 uint32_t map_pidx; /* next map to be used */ 256 uint32_t map_cidx; /* reclaimed up to this index */ 257 uint32_t map_avail; /* # of available maps */ 258 }; 259 260 struct tx_sdesc { 261 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 262 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 263 }; 264 265 enum { 266 /* iq flags */ 267 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 268 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 269 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 270 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 271 272 /* iq state */ 273 IQS_DISABLED = 0, 274 IQS_BUSY = 1, 275 IQS_IDLE = 2, 276 }; 277 278 /* 279 * Ingress Queue: T4 is producer, driver is consumer. 280 */ 281 struct sge_iq { 282 bus_dma_tag_t desc_tag; 283 bus_dmamap_t desc_map; 284 bus_addr_t ba; /* bus address of descriptor ring */ 285 char lockname[16]; 286 uint32_t flags; 287 uint16_t abs_id; /* absolute SGE id for the iq */ 288 int8_t intr_pktc_idx; /* packet count threshold index */ 289 int8_t pad0; 290 __be64 *desc; /* KVA of descriptor ring */ 291 292 volatile int state; 293 struct adapter *adapter; 294 const __be64 *cdesc; /* current descriptor */ 295 uint8_t gen; /* generation bit */ 296 uint8_t intr_params; /* interrupt holdoff parameters */ 297 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 298 uint8_t esize; /* size (bytes) of each entry in the queue */ 299 uint16_t qsize; /* size (# of entries) of the queue */ 300 uint16_t cidx; /* consumer index */ 301 uint16_t cntxt_id; /* SGE context id for the iq */ 302 303 STAILQ_ENTRY(sge_iq) link; 304 }; 305 306 enum { 307 EQ_CTRL = 1, 308 EQ_ETH = 2, 309 #ifdef TCP_OFFLOAD 310 EQ_OFLD = 3, 311 #endif 312 313 /* eq flags */ 314 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 315 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 316 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 317 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 318 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 319 }; 320 321 /* 322 * Egress Queue: driver is producer, T4 is consumer. 323 * 324 * Note: A free list is an egress queue (driver produces the buffers and T4 325 * consumes them) but it's special enough to have its own struct (see sge_fl). 326 */ 327 struct sge_eq { 328 unsigned int flags; /* MUST be first */ 329 unsigned int cntxt_id; /* SGE context id for the eq */ 330 bus_dma_tag_t desc_tag; 331 bus_dmamap_t desc_map; 332 char lockname[16]; 333 struct mtx eq_lock; 334 335 struct tx_desc *desc; /* KVA of descriptor ring */ 336 bus_addr_t ba; /* bus address of descriptor ring */ 337 struct sge_qstat *spg; /* status page, for convenience */ 338 uint16_t cap; /* max # of desc, for convenience */ 339 uint16_t avail; /* available descriptors, for convenience */ 340 uint16_t qsize; /* size (# of entries) of the queue */ 341 uint16_t cidx; /* consumer idx (desc idx) */ 342 uint16_t pidx; /* producer idx (desc idx) */ 343 uint16_t pending; /* # of descriptors used since last doorbell */ 344 uint16_t iqid; /* iq that gets egr_update for the eq */ 345 uint8_t tx_chan; /* tx channel used by the eq */ 346 struct task tx_task; 347 struct callout tx_callout; 348 349 /* stats */ 350 351 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 352 uint32_t unstalled; /* recovered from stall */ 353 }; 354 355 enum { 356 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 357 FL_DOOMED = (1 << 1), /* about to be destroyed */ 358 }; 359 360 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 361 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 362 363 struct sge_fl { 364 bus_dma_tag_t desc_tag; 365 bus_dmamap_t desc_map; 366 bus_dma_tag_t tag[FL_BUF_SIZES]; 367 uint8_t tag_idx; 368 struct mtx fl_lock; 369 char lockname[16]; 370 int flags; 371 372 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 373 bus_addr_t ba; /* bus address of descriptor ring */ 374 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 375 uint32_t cap; /* max # of buffers, for convenience */ 376 uint16_t qsize; /* size (# of entries) of the queue */ 377 uint16_t cntxt_id; /* SGE context id for the freelist */ 378 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 379 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 380 uint32_t needed; /* # of buffers needed to fill up fl. */ 381 uint32_t lowat; /* # of buffers <= this means fl needs help */ 382 uint32_t pending; /* # of bufs allocated since last doorbell */ 383 unsigned int dmamap_failed; 384 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 385 }; 386 387 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 388 struct sge_txq { 389 struct sge_eq eq; /* MUST be first */ 390 391 struct ifnet *ifp; /* the interface this txq belongs to */ 392 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 393 struct buf_ring *br; /* tx buffer ring */ 394 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 395 struct mbuf *m; /* held up due to temporary resource shortage */ 396 397 struct tx_maps txmaps; 398 399 /* stats for common events first */ 400 401 uint64_t txcsum; /* # of times hardware assisted with checksum */ 402 uint64_t tso_wrs; /* # of TSO work requests */ 403 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 404 uint64_t imm_wrs; /* # of work requests with immediate data */ 405 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 406 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 407 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 408 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 409 410 /* stats for not-that-common events */ 411 412 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 413 uint32_t no_desc; /* out of hardware descriptors */ 414 } __aligned(CACHE_LINE_SIZE); 415 416 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 417 struct sge_rxq { 418 struct sge_iq iq; /* MUST be first */ 419 struct sge_fl fl; /* MUST follow iq */ 420 421 struct ifnet *ifp; /* the interface this rxq belongs to */ 422 #if defined(INET) || defined(INET6) 423 struct lro_ctrl lro; /* LRO state */ 424 #endif 425 426 /* stats for common events first */ 427 428 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 429 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 430 431 /* stats for not-that-common events */ 432 433 } __aligned(CACHE_LINE_SIZE); 434 435 static inline struct sge_rxq * 436 iq_to_rxq(struct sge_iq *iq) 437 { 438 439 return (member2struct(sge_rxq, iq, iq)); 440 } 441 442 443 #ifdef TCP_OFFLOAD 444 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 445 struct sge_ofld_rxq { 446 struct sge_iq iq; /* MUST be first */ 447 struct sge_fl fl; /* MUST follow iq */ 448 } __aligned(CACHE_LINE_SIZE); 449 450 static inline struct sge_ofld_rxq * 451 iq_to_ofld_rxq(struct sge_iq *iq) 452 { 453 454 return (member2struct(sge_ofld_rxq, iq, iq)); 455 } 456 #endif 457 458 struct wrqe { 459 STAILQ_ENTRY(wrqe) link; 460 struct sge_wrq *wrq; 461 int wr_len; 462 uint64_t wr[] __aligned(16); 463 }; 464 465 /* 466 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 467 * and offload tx queues are of this type. 468 */ 469 struct sge_wrq { 470 struct sge_eq eq; /* MUST be first */ 471 472 struct adapter *adapter; 473 474 /* List of WRs held up due to lack of tx descriptors */ 475 STAILQ_HEAD(, wrqe) wr_list; 476 477 /* stats for common events first */ 478 479 uint64_t tx_wrs; /* # of tx work requests */ 480 481 /* stats for not-that-common events */ 482 483 uint32_t no_desc; /* out of hardware descriptors */ 484 } __aligned(CACHE_LINE_SIZE); 485 486 struct sge { 487 int timer_val[SGE_NTIMERS]; 488 int counter_val[SGE_NCOUNTERS]; 489 int fl_starve_threshold; 490 491 int nrxq; /* total # of Ethernet rx queues */ 492 int ntxq; /* total # of Ethernet tx tx queues */ 493 #ifdef TCP_OFFLOAD 494 int nofldrxq; /* total # of TOE rx queues */ 495 int nofldtxq; /* total # of TOE tx queues */ 496 #endif 497 int niq; /* total # of ingress queues */ 498 int neq; /* total # of egress queues */ 499 500 struct sge_iq fwq; /* Firmware event queue */ 501 struct sge_wrq mgmtq; /* Management queue (control queue) */ 502 struct sge_wrq *ctrlq; /* Control queues */ 503 struct sge_txq *txq; /* NIC tx queues */ 504 struct sge_rxq *rxq; /* NIC rx queues */ 505 #ifdef TCP_OFFLOAD 506 struct sge_wrq *ofld_txq; /* TOE tx queues */ 507 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 508 #endif 509 510 uint16_t iq_start; 511 int eq_start; 512 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 513 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 514 }; 515 516 struct rss_header; 517 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 518 struct mbuf *); 519 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 520 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 521 522 struct adapter { 523 SLIST_ENTRY(adapter) link; 524 device_t dev; 525 struct cdev *cdev; 526 527 /* PCIe register resources */ 528 int regs_rid; 529 struct resource *regs_res; 530 int msix_rid; 531 struct resource *msix_res; 532 bus_space_handle_t bh; 533 bus_space_tag_t bt; 534 bus_size_t mmio_len; 535 536 unsigned int pf; 537 unsigned int mbox; 538 539 /* Interrupt information */ 540 int intr_type; 541 int intr_count; 542 struct irq { 543 struct resource *res; 544 int rid; 545 void *tag; 546 } *irq; 547 548 bus_dma_tag_t dmat; /* Parent DMA tag */ 549 550 struct sge sge; 551 552 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 553 struct port_info *port[MAX_NPORTS]; 554 uint8_t chan_map[NCHAN]; 555 uint32_t filter_mode; 556 557 #ifdef TCP_OFFLOAD 558 void *tom_softc; /* (struct tom_data *) */ 559 struct tom_tunables tt; 560 #endif 561 struct l2t_data *l2t; /* L2 table */ 562 struct tid_info tids; 563 564 int open_device_map; 565 #ifdef TCP_OFFLOAD 566 int offload_map; 567 #endif 568 int flags; 569 570 char fw_version[32]; 571 unsigned int cfcsum; 572 struct adapter_params params; 573 struct t4_virt_res vres; 574 575 uint16_t linkcaps; 576 uint16_t niccaps; 577 uint16_t toecaps; 578 uint16_t rdmacaps; 579 uint16_t iscsicaps; 580 uint16_t fcoecaps; 581 582 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 583 584 struct mtx sc_lock; 585 char lockname[16]; 586 587 /* Starving free lists */ 588 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 589 TAILQ_HEAD(, sge_fl) sfl; 590 struct callout sfl_callout; 591 592 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 593 fw_msg_handler_t fw_msg_handler[4]; /* NUM_FW6_TYPES */ 594 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 595 }; 596 597 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 598 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 599 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 600 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 601 602 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 603 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 604 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 605 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 606 607 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 608 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 609 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 610 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 611 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 612 613 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 614 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 615 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 616 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 617 618 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 619 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 620 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 621 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 622 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 623 624 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 625 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 626 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 627 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 628 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 629 630 #define for_each_txq(pi, iter, txq) \ 631 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 632 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 633 #define for_each_rxq(pi, iter, rxq) \ 634 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 635 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 636 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 637 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 638 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 639 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 640 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 641 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 642 643 /* One for errors, one for firmware events */ 644 #define T4_EXTRA_INTR 2 645 646 static inline uint32_t 647 t4_read_reg(struct adapter *sc, uint32_t reg) 648 { 649 650 return bus_space_read_4(sc->bt, sc->bh, reg); 651 } 652 653 static inline void 654 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 655 { 656 657 bus_space_write_4(sc->bt, sc->bh, reg, val); 658 } 659 660 static inline uint64_t 661 t4_read_reg64(struct adapter *sc, uint32_t reg) 662 { 663 664 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 665 } 666 667 static inline void 668 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 669 { 670 671 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 672 } 673 674 static inline void 675 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 676 { 677 678 *val = pci_read_config(sc->dev, reg, 1); 679 } 680 681 static inline void 682 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 683 { 684 685 pci_write_config(sc->dev, reg, val, 1); 686 } 687 688 static inline void 689 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 690 { 691 692 *val = pci_read_config(sc->dev, reg, 2); 693 } 694 695 static inline void 696 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 697 { 698 699 pci_write_config(sc->dev, reg, val, 2); 700 } 701 702 static inline void 703 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 704 { 705 706 *val = pci_read_config(sc->dev, reg, 4); 707 } 708 709 static inline void 710 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 711 { 712 713 pci_write_config(sc->dev, reg, val, 4); 714 } 715 716 static inline struct port_info * 717 adap2pinfo(struct adapter *sc, int idx) 718 { 719 720 return (sc->port[idx]); 721 } 722 723 static inline void 724 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 725 { 726 727 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 728 } 729 730 static inline bool is_10G_port(const struct port_info *pi) 731 { 732 733 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 734 } 735 736 static inline int tx_resume_threshold(struct sge_eq *eq) 737 { 738 739 return (eq->qsize / 4); 740 } 741 742 /* t4_main.c */ 743 void t4_tx_task(void *, int); 744 void t4_tx_callout(void *); 745 int t4_os_find_pci_capability(struct adapter *, int); 746 int t4_os_pci_save_state(struct adapter *); 747 int t4_os_pci_restore_state(struct adapter *); 748 void t4_os_portmod_changed(const struct adapter *, int); 749 void t4_os_link_changed(struct adapter *, int, int); 750 void t4_iterate(void (*)(struct adapter *, void *), void *); 751 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 752 int t4_register_an_handler(struct adapter *, an_handler_t); 753 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 754 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 755 756 /* t4_sge.c */ 757 void t4_sge_modload(void); 758 int t4_sge_init(struct adapter *); 759 int t4_create_dma_tag(struct adapter *); 760 int t4_destroy_dma_tag(struct adapter *); 761 int t4_setup_adapter_queues(struct adapter *); 762 int t4_teardown_adapter_queues(struct adapter *); 763 int t4_setup_port_queues(struct port_info *); 764 int t4_teardown_port_queues(struct port_info *); 765 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 766 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 767 void t4_intr_all(void *); 768 void t4_intr(void *); 769 void t4_intr_err(void *); 770 void t4_intr_evt(void *); 771 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 772 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 773 void t4_update_fl_bufsize(struct ifnet *); 774 int can_resume_tx(struct sge_eq *); 775 776 static inline struct wrqe * 777 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 778 { 779 int len = offsetof(struct wrqe, wr) + wr_len; 780 struct wrqe *wr; 781 782 wr = malloc(len, M_CXGBE, M_NOWAIT); 783 if (__predict_false(wr == NULL)) 784 return (NULL); 785 wr->wr_len = wr_len; 786 wr->wrq = wrq; 787 return (wr); 788 } 789 790 static inline void * 791 wrtod(struct wrqe *wr) 792 { 793 return (&wr->wr[0]); 794 } 795 796 static inline void 797 free_wrqe(struct wrqe *wr) 798 { 799 free(wr, M_CXGBE); 800 } 801 802 static inline void 803 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 804 { 805 struct sge_wrq *wrq = wr->wrq; 806 807 TXQ_LOCK(wrq); 808 t4_wrq_tx_locked(sc, wrq, wr); 809 TXQ_UNLOCK(wrq); 810 } 811 812 #endif 813