xref: /freebsd/sys/dev/cxgbe/adapter.h (revision a0e793cbf1951d07fc47a0d9ea389d7dacba5213)
1 /*-
2  * Copyright (c) 2011 Chelsio Communications, Inc.
3  * All rights reserved.
4  * Written by: Navdeep Parhar <np@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  *
29  */
30 
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33 
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
41 #include <sys/sx.h>
42 #include <vm/uma.h>
43 
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
55 
56 #include "offload.h"
57 #include "common/t4_msg.h"
58 #include "firmware/t4fw_interface.h"
59 
60 MALLOC_DECLARE(M_CXGBE);
61 #define CXGBE_UNIMPLEMENTED(s) \
62     panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
63 
64 #if defined(__i386__) || defined(__amd64__)
65 static __inline void
66 prefetch(void *x)
67 {
68 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
69 }
70 #else
71 #define prefetch(x)
72 #endif
73 
74 #ifndef SYSCTL_ADD_UQUAD
75 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
76 #define sysctl_handle_64 sysctl_handle_quad
77 #define CTLTYPE_U64 CTLTYPE_QUAD
78 #endif
79 
80 #if (__FreeBSD_version >= 900030) || \
81     ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
82 #define SBUF_DRAIN 1
83 #endif
84 
85 #ifdef __amd64__
86 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
87 static __inline uint64_t
88 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
89     bus_size_t offset)
90 {
91 	KASSERT(tag == X86_BUS_SPACE_MEM,
92 	    ("%s: can only handle mem space", __func__));
93 
94 	return (*(volatile uint64_t *)(handle + offset));
95 }
96 
97 static __inline void
98 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
99     bus_size_t offset, uint64_t value)
100 {
101 	KASSERT(tag == X86_BUS_SPACE_MEM,
102 	    ("%s: can only handle mem space", __func__));
103 
104 	*(volatile uint64_t *)(bsh + offset) = value;
105 }
106 #else
107 static __inline uint64_t
108 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
109     bus_size_t offset)
110 {
111 	return (uint64_t)bus_space_read_4(tag, handle, offset) +
112 	    ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
113 }
114 
115 static __inline void
116 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
117     bus_size_t offset, uint64_t value)
118 {
119 	bus_space_write_4(tag, bsh, offset, value);
120 	bus_space_write_4(tag, bsh, offset + 4, value >> 32);
121 }
122 #endif
123 
124 struct adapter;
125 typedef struct adapter adapter_t;
126 
127 enum {
128 	/*
129 	 * All ingress queues use this entry size.  Note that the firmware event
130 	 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
131 	 * be at least 64.
132 	 */
133 	IQ_ESIZE = 64,
134 
135 	/* Default queue sizes for all kinds of ingress queues */
136 	FW_IQ_QSIZE = 256,
137 	RX_IQ_QSIZE = 1024,
138 
139 	/* All egress queues use this entry size */
140 	EQ_ESIZE = 64,
141 
142 	/* Default queue sizes for all kinds of egress queues */
143 	CTRL_EQ_QSIZE = 128,
144 	TX_EQ_QSIZE = 1024,
145 
146 #if MJUMPAGESIZE != MCLBYTES
147 	SW_ZONE_SIZES = 4,	/* cluster, jumbop, jumbo9k, jumbo16k */
148 #else
149 	SW_ZONE_SIZES = 3,	/* cluster, jumbo9k, jumbo16k */
150 #endif
151 	CL_METADATA_SIZE = CACHE_LINE_SIZE,
152 
153 	SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
154 	TX_SGL_SEGS = 36,
155 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
156 };
157 
158 enum {
159 	/* adapter intr_type */
160 	INTR_INTX	= (1 << 0),
161 	INTR_MSI 	= (1 << 1),
162 	INTR_MSIX	= (1 << 2)
163 };
164 
165 enum {
166 	XGMAC_MTU	= (1 << 0),
167 	XGMAC_PROMISC	= (1 << 1),
168 	XGMAC_ALLMULTI	= (1 << 2),
169 	XGMAC_VLANEX	= (1 << 3),
170 	XGMAC_UCADDR	= (1 << 4),
171 	XGMAC_MCADDRS	= (1 << 5),
172 
173 	XGMAC_ALL	= 0xffff
174 };
175 
176 enum {
177 	/* flags understood by begin_synchronized_op */
178 	HOLD_LOCK	= (1 << 0),
179 	SLEEP_OK	= (1 << 1),
180 	INTR_OK		= (1 << 2),
181 
182 	/* flags understood by end_synchronized_op */
183 	LOCK_HELD	= HOLD_LOCK,
184 };
185 
186 enum {
187 	/* adapter flags */
188 	FULL_INIT_DONE	= (1 << 0),
189 	FW_OK		= (1 << 1),
190 	/* INTR_DIRECT	= (1 << 2),	No longer used. */
191 	MASTER_PF	= (1 << 3),
192 	ADAP_SYSCTL_CTX	= (1 << 4),
193 	TOM_INIT_DONE	= (1 << 5),
194 	BUF_PACKING_OK	= (1 << 6),
195 
196 	CXGBE_BUSY	= (1 << 9),
197 
198 	/* port flags */
199 	DOOMED		= (1 << 0),
200 	PORT_INIT_DONE	= (1 << 1),
201 	PORT_SYSCTL_CTX	= (1 << 2),
202 	HAS_TRACEQ	= (1 << 3),
203 	INTR_RXQ	= (1 << 4),	/* All NIC rxq's take interrupts */
204 	INTR_OFLD_RXQ	= (1 << 5),	/* All TOE rxq's take interrupts */
205 	INTR_NM_RXQ	= (1 << 6),	/* All netmap rxq's take interrupts */
206 	INTR_ALL	= (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
207 };
208 
209 #define IS_DOOMED(pi)	((pi)->flags & DOOMED)
210 #define SET_DOOMED(pi)	do {(pi)->flags |= DOOMED;} while (0)
211 #define IS_BUSY(sc)	((sc)->flags & CXGBE_BUSY)
212 #define SET_BUSY(sc)	do {(sc)->flags |= CXGBE_BUSY;} while (0)
213 #define CLR_BUSY(sc)	do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
214 
215 struct port_info {
216 	device_t dev;
217 	struct adapter *adapter;
218 
219 	struct ifnet *ifp;
220 	struct ifmedia media;
221 
222 	struct mtx pi_lock;
223 	char lockname[16];
224 	unsigned long flags;
225 	int if_flags;
226 
227 	uint16_t *rss;
228 	uint16_t viid;
229 	int16_t  xact_addr_filt;/* index of exact MAC address filter */
230 	uint16_t rss_size;	/* size of VI's RSS table slice */
231 	uint8_t  lport;		/* associated offload logical port */
232 	int8_t   mdio_addr;
233 	uint8_t  port_type;
234 	uint8_t  mod_type;
235 	uint8_t  port_id;
236 	uint8_t  tx_chan;
237 	uint8_t  rx_chan_map;	/* rx MPS channel bitmap */
238 
239 	/* These need to be int as they are used in sysctl */
240 	int ntxq;	/* # of tx queues */
241 	int first_txq;	/* index of first tx queue */
242 	int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
243 	int nrxq;	/* # of rx queues */
244 	int first_rxq;	/* index of first rx queue */
245 #ifdef TCP_OFFLOAD
246 	int nofldtxq;		/* # of offload tx queues */
247 	int first_ofld_txq;	/* index of first offload tx queue */
248 	int nofldrxq;		/* # of offload rx queues */
249 	int first_ofld_rxq;	/* index of first offload rx queue */
250 #endif
251 #ifdef DEV_NETMAP
252 	int nnmtxq;		/* # of netmap tx queues */
253 	int first_nm_txq;	/* index of first netmap tx queue */
254 	int nnmrxq;		/* # of netmap rx queues */
255 	int first_nm_rxq;	/* index of first netmap rx queue */
256 
257 	struct ifnet *nm_ifp;
258 	struct ifmedia nm_media;
259 	int nmif_flags;
260 	uint16_t nm_viid;
261 	int16_t nm_xact_addr_filt;
262 	uint16_t nm_rss_size;	/* size of netmap VI's RSS table slice */
263 #endif
264 	int tmr_idx;
265 	int pktc_idx;
266 	int qsize_rxq;
267 	int qsize_txq;
268 
269 	int linkdnrc;
270 	struct link_config link_cfg;
271 	struct port_stats stats;
272 
273 	eventhandler_tag vlan_c;
274 
275 	struct callout tick;
276 	struct sysctl_ctx_list ctx;	/* from ifconfig up to driver detach */
277 
278 	uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
279 };
280 
281 /* Where the cluster came from, how it has been carved up. */
282 struct cluster_layout {
283 	int8_t zidx;
284 	int8_t hwidx;
285 	uint16_t region1;	/* mbufs laid out within this region */
286 				/* region2 is the DMA region */
287 	uint16_t region3;	/* cluster_metadata within this region */
288 };
289 
290 struct cluster_metadata {
291 	u_int refcount;
292 #ifdef INVARIANTS
293 	struct fl_sdesc *sd;	/* For debug only.  Could easily be stale */
294 #endif
295 };
296 
297 struct fl_sdesc {
298 	caddr_t cl;
299 	uint16_t nmbuf;	/* # of driver originated mbufs with ref on cluster */
300 	struct cluster_layout cll;
301 };
302 
303 struct tx_desc {
304 	__be64 flit[8];
305 };
306 
307 struct tx_map {
308 	struct mbuf *m;
309 	bus_dmamap_t map;
310 };
311 
312 /* DMA maps used for tx */
313 struct tx_maps {
314 	struct tx_map *maps;
315 	uint32_t map_total;	/* # of DMA maps */
316 	uint32_t map_pidx;	/* next map to be used */
317 	uint32_t map_cidx;	/* reclaimed up to this index */
318 	uint32_t map_avail;	/* # of available maps */
319 };
320 
321 struct tx_sdesc {
322 	uint8_t desc_used;	/* # of hardware descriptors used by the WR */
323 	uint8_t credits;	/* NIC txq: # of frames sent out in the WR */
324 };
325 
326 
327 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
328 struct iq_desc {
329 	struct rss_header rss;
330 	uint8_t cpl[IQ_PAD];
331 	struct rsp_ctrl rsp;
332 };
333 #undef IQ_PAD
334 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
335 
336 enum {
337 	/* iq flags */
338 	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
339 	IQ_HAS_FL	= (1 << 1),	/* iq associated with a freelist */
340 	IQ_INTR		= (1 << 2),	/* iq takes direct interrupt */
341 	IQ_LRO_ENABLED	= (1 << 3),	/* iq is an eth rxq with LRO enabled */
342 
343 	/* iq state */
344 	IQS_DISABLED	= 0,
345 	IQS_BUSY	= 1,
346 	IQS_IDLE	= 2,
347 };
348 
349 /*
350  * Ingress Queue: T4 is producer, driver is consumer.
351  */
352 struct sge_iq {
353 	uint32_t flags;
354 	volatile int state;
355 	struct adapter *adapter;
356 	struct iq_desc  *desc;	/* KVA of descriptor ring */
357 	int8_t   intr_pktc_idx;	/* packet count threshold index */
358 	uint8_t  gen;		/* generation bit */
359 	uint8_t  intr_params;	/* interrupt holdoff parameters */
360 	uint8_t  intr_next;	/* XXX: holdoff for next interrupt */
361 	uint16_t qsize;		/* size (# of entries) of the queue */
362 	uint16_t sidx;		/* index of the entry with the status page */
363 	uint16_t cidx;		/* consumer index */
364 	uint16_t cntxt_id;	/* SGE context id for the iq */
365 	uint16_t abs_id;	/* absolute SGE id for the iq */
366 
367 	STAILQ_ENTRY(sge_iq) link;
368 
369 	bus_dma_tag_t desc_tag;
370 	bus_dmamap_t desc_map;
371 	bus_addr_t ba;		/* bus address of descriptor ring */
372 };
373 
374 enum {
375 	EQ_CTRL		= 1,
376 	EQ_ETH		= 2,
377 #ifdef TCP_OFFLOAD
378 	EQ_OFLD		= 3,
379 #endif
380 
381 	/* eq flags */
382 	EQ_TYPEMASK	= 7,		/* 3 lsbits hold the type */
383 	EQ_ALLOCATED	= (1 << 3),	/* firmware resources allocated */
384 	EQ_DOOMED	= (1 << 4),	/* about to be destroyed */
385 	EQ_CRFLUSHED	= (1 << 5),	/* expecting an update from SGE */
386 	EQ_STALLED	= (1 << 6),	/* out of hw descriptors or dmamaps */
387 };
388 
389 /* Listed in order of preference.  Update t4_sysctls too if you change these */
390 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
391 
392 /*
393  * Egress Queue: driver is producer, T4 is consumer.
394  *
395  * Note: A free list is an egress queue (driver produces the buffers and T4
396  * consumes them) but it's special enough to have its own struct (see sge_fl).
397  */
398 struct sge_eq {
399 	unsigned int flags;	/* MUST be first */
400 	unsigned int cntxt_id;	/* SGE context id for the eq */
401 	bus_dma_tag_t desc_tag;
402 	bus_dmamap_t desc_map;
403 	char lockname[16];
404 	struct mtx eq_lock;
405 
406 	struct tx_desc *desc;	/* KVA of descriptor ring */
407 	bus_addr_t ba;		/* bus address of descriptor ring */
408 	struct sge_qstat *spg;	/* status page, for convenience */
409 	uint16_t doorbells;
410 	volatile uint32_t *udb;	/* KVA of doorbell (lies within BAR2) */
411 	u_int udb_qid;		/* relative qid within the doorbell page */
412 	uint16_t cap;		/* max # of desc, for convenience */
413 	uint16_t avail;		/* available descriptors, for convenience */
414 	uint16_t qsize;		/* size (# of entries) of the queue */
415 	uint16_t cidx;		/* consumer idx (desc idx) */
416 	uint16_t pidx;		/* producer idx (desc idx) */
417 	uint16_t pending;	/* # of descriptors used since last doorbell */
418 	uint16_t iqid;		/* iq that gets egr_update for the eq */
419 	uint8_t tx_chan;	/* tx channel used by the eq */
420 	struct task tx_task;
421 	struct callout tx_callout;
422 
423 	/* stats */
424 
425 	uint32_t egr_update;	/* # of SGE_EGR_UPDATE notifications for eq */
426 	uint32_t unstalled;	/* recovered from stall */
427 };
428 
429 struct sw_zone_info {
430 	uma_zone_t zone;	/* zone that this cluster comes from */
431 	int size;		/* size of cluster: 2K, 4K, 9K, 16K, etc. */
432 	int type;		/* EXT_xxx type of the cluster */
433 	int8_t head_hwidx;
434 	int8_t tail_hwidx;
435 };
436 
437 struct hw_buf_info {
438 	int8_t zidx;		/* backpointer to zone; -ve means unused */
439 	int8_t next;		/* next hwidx for this zone; -1 means no more */
440 	int size;
441 };
442 
443 enum {
444 	FL_STARVING	= (1 << 0), /* on the adapter's list of starving fl's */
445 	FL_DOOMED	= (1 << 1), /* about to be destroyed */
446 	FL_BUF_PACKING	= (1 << 2), /* buffer packing enabled */
447 	FL_BUF_RESUME	= (1 << 3), /* resume from the middle of the frame */
448 };
449 
450 #define FL_RUNNING_LOW(fl) \
451     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
452 #define FL_NOT_RUNNING_LOW(fl) \
453     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
454 
455 struct sge_fl {
456 	struct mtx fl_lock;
457 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
458 	struct fl_sdesc *sdesc;	/* KVA of software descriptor ring */
459 	struct cluster_layout cll_def;	/* default refill zone, layout */
460 	uint16_t lowat;		/* # of buffers <= this means fl needs help */
461 	int flags;
462 	uint16_t buf_boundary;
463 
464 	/* The 16b idx all deal with hw descriptors */
465 	uint16_t dbidx;		/* hw pidx after last doorbell */
466 	uint16_t sidx;		/* index of status page */
467 	volatile uint16_t hw_cidx;
468 
469 	/* The 32b idx are all buffer idx, not hardware descriptor idx */
470 	uint32_t cidx;		/* consumer index */
471 	uint32_t pidx;		/* producer index */
472 
473 	uint32_t dbval;
474 	u_int rx_offset;	/* offset in fl buf (when buffer packing) */
475 	volatile uint32_t *udb;
476 
477 	uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
478 	uint64_t mbuf_inlined;	/* # of mbuf created within clusters */
479 	uint64_t cl_allocated;	/* # of clusters allocated */
480 	uint64_t cl_recycled;	/* # of clusters recycled */
481 	uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
482 
483 	/* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
484 	struct mbuf *m0;
485 	struct mbuf **pnext;
486 	u_int remaining;
487 
488 	uint16_t qsize;		/* # of hw descriptors (status page included) */
489 	uint16_t cntxt_id;	/* SGE context id for the freelist */
490 	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
491 	bus_dma_tag_t desc_tag;
492 	bus_dmamap_t desc_map;
493 	char lockname[16];
494 	bus_addr_t ba;		/* bus address of descriptor ring */
495 	struct cluster_layout cll_alt;	/* alternate refill zone, layout */
496 };
497 
498 /* txq: SGE egress queue + what's needed for Ethernet NIC */
499 struct sge_txq {
500 	struct sge_eq eq;	/* MUST be first */
501 
502 	struct ifnet *ifp;	/* the interface this txq belongs to */
503 	bus_dma_tag_t tx_tag;	/* tag for transmit buffers */
504 	struct buf_ring *br;	/* tx buffer ring */
505 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
506 	struct mbuf *m;		/* held up due to temporary resource shortage */
507 
508 	struct tx_maps txmaps;
509 
510 	/* stats for common events first */
511 
512 	uint64_t txcsum;	/* # of times hardware assisted with checksum */
513 	uint64_t tso_wrs;	/* # of TSO work requests */
514 	uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
515 	uint64_t imm_wrs;	/* # of work requests with immediate data */
516 	uint64_t sgl_wrs;	/* # of work requests with direct SGL */
517 	uint64_t txpkt_wrs;	/* # of txpkt work requests (not coalesced) */
518 	uint64_t txpkts_wrs;	/* # of coalesced tx work requests */
519 	uint64_t txpkts_pkts;	/* # of frames in coalesced tx work requests */
520 
521 	/* stats for not-that-common events */
522 
523 	uint32_t no_dmamap;	/* no DMA map to load the mbuf */
524 	uint32_t no_desc;	/* out of hardware descriptors */
525 } __aligned(CACHE_LINE_SIZE);
526 
527 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
528 struct sge_rxq {
529 	struct sge_iq iq;	/* MUST be first */
530 	struct sge_fl fl;	/* MUST follow iq */
531 
532 	struct ifnet *ifp;	/* the interface this rxq belongs to */
533 #if defined(INET) || defined(INET6)
534 	struct lro_ctrl lro;	/* LRO state */
535 #endif
536 
537 	/* stats for common events first */
538 
539 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
540 	uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
541 
542 	/* stats for not-that-common events */
543 
544 } __aligned(CACHE_LINE_SIZE);
545 
546 static inline struct sge_rxq *
547 iq_to_rxq(struct sge_iq *iq)
548 {
549 
550 	return (__containerof(iq, struct sge_rxq, iq));
551 }
552 
553 
554 #ifdef TCP_OFFLOAD
555 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
556 struct sge_ofld_rxq {
557 	struct sge_iq iq;	/* MUST be first */
558 	struct sge_fl fl;	/* MUST follow iq */
559 } __aligned(CACHE_LINE_SIZE);
560 
561 static inline struct sge_ofld_rxq *
562 iq_to_ofld_rxq(struct sge_iq *iq)
563 {
564 
565 	return (__containerof(iq, struct sge_ofld_rxq, iq));
566 }
567 #endif
568 
569 struct wrqe {
570 	STAILQ_ENTRY(wrqe) link;
571 	struct sge_wrq *wrq;
572 	int wr_len;
573 	uint64_t wr[] __aligned(16);
574 };
575 
576 /*
577  * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
578  * and offload tx queues are of this type.
579  */
580 struct sge_wrq {
581 	struct sge_eq eq;	/* MUST be first */
582 
583 	struct adapter *adapter;
584 
585 	/* List of WRs held up due to lack of tx descriptors */
586 	STAILQ_HEAD(, wrqe) wr_list;
587 
588 	/* stats for common events first */
589 
590 	uint64_t tx_wrs;	/* # of tx work requests */
591 
592 	/* stats for not-that-common events */
593 
594 	uint32_t no_desc;	/* out of hardware descriptors */
595 } __aligned(CACHE_LINE_SIZE);
596 
597 
598 #ifdef DEV_NETMAP
599 struct sge_nm_rxq {
600 	struct port_info *pi;
601 
602 	struct iq_desc *iq_desc;
603 	uint16_t iq_abs_id;
604 	uint16_t iq_cntxt_id;
605 	uint16_t iq_cidx;
606 	uint16_t iq_sidx;
607 	uint8_t iq_gen;
608 
609 	__be64  *fl_desc;
610 	uint16_t fl_cntxt_id;
611 	uint32_t fl_cidx;
612 	uint32_t fl_pidx;
613 	uint32_t fl_sidx;
614 	uint32_t fl_db_val;
615 	u_int fl_hwidx:4;
616 
617 	u_int nid;		/* netmap ring # for this queue */
618 
619 	/* infrequently used items after this */
620 
621 	bus_dma_tag_t iq_desc_tag;
622 	bus_dmamap_t iq_desc_map;
623 	bus_addr_t iq_ba;
624 	int intr_idx;
625 
626 	bus_dma_tag_t fl_desc_tag;
627 	bus_dmamap_t fl_desc_map;
628 	bus_addr_t fl_ba;
629 } __aligned(CACHE_LINE_SIZE);
630 
631 struct sge_nm_txq {
632 	struct tx_desc *desc;
633 	uint16_t cidx;
634 	uint16_t pidx;
635 	uint16_t sidx;
636 	uint16_t equiqidx;	/* EQUIQ last requested at this pidx */
637 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
638 	uint16_t dbidx;		/* pidx of the most recent doorbell */
639 	uint16_t doorbells;
640 	volatile uint32_t *udb;
641 	u_int udb_qid;
642 	u_int cntxt_id;
643 	__be32 cpl_ctrl0;	/* for convenience */
644 	u_int nid;		/* netmap ring # for this queue */
645 
646 	/* infrequently used items after this */
647 
648 	bus_dma_tag_t desc_tag;
649 	bus_dmamap_t desc_map;
650 	bus_addr_t ba;
651 	int iqidx;
652 } __aligned(CACHE_LINE_SIZE);
653 #endif
654 
655 struct sge {
656 	int timer_val[SGE_NTIMERS];
657 	int counter_val[SGE_NCOUNTERS];
658 	int fl_starve_threshold;
659 	int fl_starve_threshold2;
660 	int eq_s_qpp;
661 	int iq_s_qpp;
662 
663 	int nrxq;	/* total # of Ethernet rx queues */
664 	int ntxq;	/* total # of Ethernet tx tx queues */
665 #ifdef TCP_OFFLOAD
666 	int nofldrxq;	/* total # of TOE rx queues */
667 	int nofldtxq;	/* total # of TOE tx queues */
668 #endif
669 #ifdef DEV_NETMAP
670 	int nnmrxq;	/* total # of netmap rx queues */
671 	int nnmtxq;	/* total # of netmap tx queues */
672 #endif
673 	int niq;	/* total # of ingress queues */
674 	int neq;	/* total # of egress queues */
675 
676 	struct sge_iq fwq;	/* Firmware event queue */
677 	struct sge_wrq mgmtq;	/* Management queue (control queue) */
678 	struct sge_wrq *ctrlq;	/* Control queues */
679 	struct sge_txq *txq;	/* NIC tx queues */
680 	struct sge_rxq *rxq;	/* NIC rx queues */
681 #ifdef TCP_OFFLOAD
682 	struct sge_wrq *ofld_txq;	/* TOE tx queues */
683 	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
684 #endif
685 #ifdef DEV_NETMAP
686 	struct sge_nm_txq *nm_txq;	/* netmap tx queues */
687 	struct sge_nm_rxq *nm_rxq;	/* netmap rx queues */
688 #endif
689 
690 	uint16_t iq_start;
691 	int eq_start;
692 	struct sge_iq **iqmap;	/* iq->cntxt_id to iq mapping */
693 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
694 
695 	int pack_boundary;
696 	int8_t safe_hwidx1;	/* may not have room for metadata */
697 	int8_t safe_hwidx2;	/* with room for metadata and maybe more */
698 	struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
699 	struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
700 };
701 
702 struct rss_header;
703 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
704     struct mbuf *);
705 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
706 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
707 
708 struct adapter {
709 	SLIST_ENTRY(adapter) link;
710 	device_t dev;
711 	struct cdev *cdev;
712 
713 	/* PCIe register resources */
714 	int regs_rid;
715 	struct resource *regs_res;
716 	int msix_rid;
717 	struct resource *msix_res;
718 	bus_space_handle_t bh;
719 	bus_space_tag_t bt;
720 	bus_size_t mmio_len;
721 	int udbs_rid;
722 	struct resource *udbs_res;
723 	volatile uint8_t *udbs_base;
724 
725 	unsigned int pf;
726 	unsigned int mbox;
727 
728 	/* Interrupt information */
729 	int intr_type;
730 	int intr_count;
731 	struct irq {
732 		struct resource *res;
733 		int rid;
734 		void *tag;
735 	} *irq;
736 
737 	bus_dma_tag_t dmat;	/* Parent DMA tag */
738 
739 	struct sge sge;
740 	int lro_timeout;
741 
742 	struct taskqueue *tq[NCHAN];	/* taskqueues that flush data out */
743 	struct port_info *port[MAX_NPORTS];
744 	uint8_t chan_map[NCHAN];
745 
746 #ifdef TCP_OFFLOAD
747 	void *tom_softc;	/* (struct tom_data *) */
748 	struct tom_tunables tt;
749 	void *iwarp_softc;	/* (struct c4iw_dev *) */
750 	void *iscsi_softc;
751 #endif
752 	struct l2t_data *l2t;	/* L2 table */
753 	struct tid_info tids;
754 
755 	uint16_t doorbells;
756 	int open_device_map;
757 #ifdef TCP_OFFLOAD
758 	int offload_map;
759 #endif
760 	int flags;
761 
762 	char ifp_lockname[16];
763 	struct mtx ifp_lock;
764 	struct ifnet *ifp;	/* tracer ifp */
765 	struct ifmedia media;
766 	int traceq;		/* iq used by all tracers, -1 if none */
767 	int tracer_valid;	/* bitmap of valid tracers */
768 	int tracer_enabled;	/* bitmap of enabled tracers */
769 
770 	char fw_version[32];
771 	char cfg_file[32];
772 	u_int cfcsum;
773 	struct adapter_params params;
774 	struct t4_virt_res vres;
775 
776 	uint16_t linkcaps;
777 	uint16_t niccaps;
778 	uint16_t toecaps;
779 	uint16_t rdmacaps;
780 	uint16_t iscsicaps;
781 	uint16_t fcoecaps;
782 
783 	struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
784 
785 	struct mtx sc_lock;
786 	char lockname[16];
787 
788 	/* Starving free lists */
789 	struct mtx sfl_lock;	/* same cache-line as sc_lock? but that's ok */
790 	TAILQ_HEAD(, sge_fl) sfl;
791 	struct callout sfl_callout;
792 
793 	an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
794 	fw_msg_handler_t fw_msg_handler[5];	/* NUM_FW6_TYPES */
795 	cpl_handler_t cpl_handler[0xef];	/* NUM_CPL_CMDS */
796 
797 #ifdef INVARIANTS
798 	const char *last_op;
799 	const void *last_op_thr;
800 #endif
801 
802 	int sc_do_rxcopy;
803 };
804 
805 #define ADAPTER_LOCK(sc)		mtx_lock(&(sc)->sc_lock)
806 #define ADAPTER_UNLOCK(sc)		mtx_unlock(&(sc)->sc_lock)
807 #define ADAPTER_LOCK_ASSERT_OWNED(sc)	mtx_assert(&(sc)->sc_lock, MA_OWNED)
808 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
809 
810 /* XXX: not bulletproof, but much better than nothing */
811 #define ASSERT_SYNCHRONIZED_OP(sc)	\
812     KASSERT(IS_BUSY(sc) && \
813 	(mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
814 	("%s: operation not synchronized.", __func__))
815 
816 #define PORT_LOCK(pi)			mtx_lock(&(pi)->pi_lock)
817 #define PORT_UNLOCK(pi)			mtx_unlock(&(pi)->pi_lock)
818 #define PORT_LOCK_ASSERT_OWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_OWNED)
819 #define PORT_LOCK_ASSERT_NOTOWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
820 
821 #define FL_LOCK(fl)			mtx_lock(&(fl)->fl_lock)
822 #define FL_TRYLOCK(fl)			mtx_trylock(&(fl)->fl_lock)
823 #define FL_UNLOCK(fl)			mtx_unlock(&(fl)->fl_lock)
824 #define FL_LOCK_ASSERT_OWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_OWNED)
825 #define FL_LOCK_ASSERT_NOTOWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
826 
827 #define RXQ_FL_LOCK(rxq)		FL_LOCK(&(rxq)->fl)
828 #define RXQ_FL_UNLOCK(rxq)		FL_UNLOCK(&(rxq)->fl)
829 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq)	FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
830 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
831 
832 #define EQ_LOCK(eq)			mtx_lock(&(eq)->eq_lock)
833 #define EQ_TRYLOCK(eq)			mtx_trylock(&(eq)->eq_lock)
834 #define EQ_UNLOCK(eq)			mtx_unlock(&(eq)->eq_lock)
835 #define EQ_LOCK_ASSERT_OWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_OWNED)
836 #define EQ_LOCK_ASSERT_NOTOWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
837 
838 #define TXQ_LOCK(txq)			EQ_LOCK(&(txq)->eq)
839 #define TXQ_TRYLOCK(txq)		EQ_TRYLOCK(&(txq)->eq)
840 #define TXQ_UNLOCK(txq)			EQ_UNLOCK(&(txq)->eq)
841 #define TXQ_LOCK_ASSERT_OWNED(txq)	EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
842 #define TXQ_LOCK_ASSERT_NOTOWNED(txq)	EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
843 
844 #define for_each_txq(pi, iter, q) \
845 	for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
846 	    iter < pi->ntxq; ++iter, ++q)
847 #define for_each_rxq(pi, iter, q) \
848 	for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
849 	    iter < pi->nrxq; ++iter, ++q)
850 #define for_each_ofld_txq(pi, iter, q) \
851 	for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
852 	    iter < pi->nofldtxq; ++iter, ++q)
853 #define for_each_ofld_rxq(pi, iter, q) \
854 	for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
855 	    iter < pi->nofldrxq; ++iter, ++q)
856 #define for_each_nm_txq(pi, iter, q) \
857 	for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
858 	    iter < pi->nnmtxq; ++iter, ++q)
859 #define for_each_nm_rxq(pi, iter, q) \
860 	for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
861 	    iter < pi->nnmrxq; ++iter, ++q)
862 
863 #define IDXINCR(idx, incr, wrap) do { \
864 	idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
865 } while (0)
866 #define IDXDIFF(head, tail, wrap) \
867 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
868 
869 /* One for errors, one for firmware events */
870 #define T4_EXTRA_INTR 2
871 
872 static inline uint32_t
873 t4_read_reg(struct adapter *sc, uint32_t reg)
874 {
875 
876 	return bus_space_read_4(sc->bt, sc->bh, reg);
877 }
878 
879 static inline void
880 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
881 {
882 
883 	bus_space_write_4(sc->bt, sc->bh, reg, val);
884 }
885 
886 static inline uint64_t
887 t4_read_reg64(struct adapter *sc, uint32_t reg)
888 {
889 
890 	return t4_bus_space_read_8(sc->bt, sc->bh, reg);
891 }
892 
893 static inline void
894 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
895 {
896 
897 	t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
898 }
899 
900 static inline void
901 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
902 {
903 
904 	*val = pci_read_config(sc->dev, reg, 1);
905 }
906 
907 static inline void
908 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
909 {
910 
911 	pci_write_config(sc->dev, reg, val, 1);
912 }
913 
914 static inline void
915 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
916 {
917 
918 	*val = pci_read_config(sc->dev, reg, 2);
919 }
920 
921 static inline void
922 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
923 {
924 
925 	pci_write_config(sc->dev, reg, val, 2);
926 }
927 
928 static inline void
929 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
930 {
931 
932 	*val = pci_read_config(sc->dev, reg, 4);
933 }
934 
935 static inline void
936 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
937 {
938 
939 	pci_write_config(sc->dev, reg, val, 4);
940 }
941 
942 static inline struct port_info *
943 adap2pinfo(struct adapter *sc, int idx)
944 {
945 
946 	return (sc->port[idx]);
947 }
948 
949 static inline void
950 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
951 {
952 
953 	bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
954 }
955 
956 static inline bool
957 is_10G_port(const struct port_info *pi)
958 {
959 
960 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
961 }
962 
963 static inline bool
964 is_40G_port(const struct port_info *pi)
965 {
966 
967 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
968 }
969 
970 static inline int
971 tx_resume_threshold(struct sge_eq *eq)
972 {
973 
974 	return (eq->qsize / 4);
975 }
976 
977 /* t4_main.c */
978 void t4_tx_task(void *, int);
979 void t4_tx_callout(void *);
980 int t4_os_find_pci_capability(struct adapter *, int);
981 int t4_os_pci_save_state(struct adapter *);
982 int t4_os_pci_restore_state(struct adapter *);
983 void t4_os_portmod_changed(const struct adapter *, int);
984 void t4_os_link_changed(struct adapter *, int, int, int);
985 void t4_iterate(void (*)(struct adapter *, void *), void *);
986 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
987 int t4_register_an_handler(struct adapter *, an_handler_t);
988 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
989 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
990 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
991 void end_synchronized_op(struct adapter *, int);
992 int update_mac_settings(struct ifnet *, int);
993 int adapter_full_init(struct adapter *);
994 int adapter_full_uninit(struct adapter *);
995 int port_full_init(struct port_info *);
996 int port_full_uninit(struct port_info *);
997 
998 #ifdef DEV_NETMAP
999 /* t4_netmap.c */
1000 int create_netmap_ifnet(struct port_info *);
1001 int destroy_netmap_ifnet(struct port_info *);
1002 void t4_nm_intr(void *);
1003 #endif
1004 
1005 /* t4_sge.c */
1006 void t4_sge_modload(void);
1007 void t4_sge_modunload(void);
1008 uint64_t t4_sge_extfree_refs(void);
1009 void t4_init_sge_cpl_handlers(struct adapter *);
1010 void t4_tweak_chip_settings(struct adapter *);
1011 int t4_read_chip_settings(struct adapter *);
1012 int t4_create_dma_tag(struct adapter *);
1013 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1014     struct sysctl_oid_list *);
1015 int t4_destroy_dma_tag(struct adapter *);
1016 int t4_setup_adapter_queues(struct adapter *);
1017 int t4_teardown_adapter_queues(struct adapter *);
1018 int t4_setup_port_queues(struct port_info *);
1019 int t4_teardown_port_queues(struct port_info *);
1020 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
1021 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
1022 void t4_intr_all(void *);
1023 void t4_intr(void *);
1024 void t4_intr_err(void *);
1025 void t4_intr_evt(void *);
1026 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1027 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
1028 void t4_update_fl_bufsize(struct ifnet *);
1029 int can_resume_tx(struct sge_eq *);
1030 
1031 /* t4_tracer.c */
1032 struct t4_tracer;
1033 void t4_tracer_modload(void);
1034 void t4_tracer_modunload(void);
1035 void t4_tracer_port_detach(struct adapter *);
1036 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1037 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1038 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1039 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1040 
1041 static inline struct wrqe *
1042 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1043 {
1044 	int len = offsetof(struct wrqe, wr) + wr_len;
1045 	struct wrqe *wr;
1046 
1047 	wr = malloc(len, M_CXGBE, M_NOWAIT);
1048 	if (__predict_false(wr == NULL))
1049 		return (NULL);
1050 	wr->wr_len = wr_len;
1051 	wr->wrq = wrq;
1052 	return (wr);
1053 }
1054 
1055 static inline void *
1056 wrtod(struct wrqe *wr)
1057 {
1058 	return (&wr->wr[0]);
1059 }
1060 
1061 static inline void
1062 free_wrqe(struct wrqe *wr)
1063 {
1064 	free(wr, M_CXGBE);
1065 }
1066 
1067 static inline void
1068 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1069 {
1070 	struct sge_wrq *wrq = wr->wrq;
1071 
1072 	TXQ_LOCK(wrq);
1073 	t4_wrq_tx_locked(sc, wrq, wr);
1074 	TXQ_UNLOCK(wrq);
1075 }
1076 
1077 #endif
1078