1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2025 Chelsio Communications. 5 * Written by: Navdeep Parhar <np@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __T4_ADAPTER_H__ 31 #define __T4_ADAPTER_H__ 32 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/counter.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/seqc.h> 42 #include <sys/sx.h> 43 #include <sys/vmem.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/taskqueue.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <net/pfil.h> 57 #include <netinet/in.h> 58 #include <netinet/tcp_lro.h> 59 60 #include "offload.h" 61 #include "t4_ioctl.h" 62 #include "common/t4_msg.h" 63 #include "firmware/t4fw_interface.h" 64 65 #define KTR_CXGBE KTR_SPARE3 66 MALLOC_DECLARE(M_CXGBE); 67 #define CXGBE_UNIMPLEMENTED(s) \ 68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 69 70 /* 71 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 72 * LIST_HEAD when building iw_cxgbe. 73 */ 74 #define CXGBE_LIST_HEAD(name, type) \ 75 struct name { \ 76 struct type *lh_first; /* first element */ \ 77 } 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 SYSCTL_DECL(_hw_cxgbe); 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 1024, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_SGL_SEGS_VM = 38, 120 TX_SGL_SEGS_VM_TSO = 37, 121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 122 TX_SGL_SEGS_VXLAN_TSO = 37, 123 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 124 }; 125 126 enum { 127 /* adapter intr_type */ 128 INTR_INTX = (1 << 0), 129 INTR_MSI = (1 << 1), 130 INTR_MSIX = (1 << 2) 131 }; 132 133 enum { 134 XGMAC_MTU = (1 << 0), 135 XGMAC_PROMISC = (1 << 1), 136 XGMAC_ALLMULTI = (1 << 2), 137 XGMAC_VLANEX = (1 << 3), 138 XGMAC_UCADDR = (1 << 4), 139 XGMAC_MCADDRS = (1 << 5), 140 141 XGMAC_ALL = 0xffff 142 }; 143 144 enum { 145 /* flags understood by begin_synchronized_op */ 146 HOLD_LOCK = (1 << 0), 147 SLEEP_OK = (1 << 1), 148 INTR_OK = (1 << 2), 149 150 /* flags understood by end_synchronized_op */ 151 LOCK_HELD = HOLD_LOCK, 152 }; 153 154 enum { 155 /* adapter flags. synch_op or adapter_lock. */ 156 FULL_INIT_DONE = (1 << 0), 157 FW_OK = (1 << 1), 158 CHK_MBOX_ACCESS = (1 << 2), 159 MASTER_PF = (1 << 3), 160 BUF_PACKING_OK = (1 << 6), 161 IS_VF = (1 << 7), 162 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 163 CXGBE_BUSY = (1 << 9), 164 165 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 166 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 167 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 168 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 169 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 170 171 /* port flags */ 172 HAS_TRACEQ = (1 << 3), 173 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 174 175 /* VI flags */ 176 VI_DETACHING = (1 << 0), 177 VI_INIT_DONE = (1 << 1), 178 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 179 TX_USES_VM_WR = (1 << 3), 180 VI_SKIP_STATS = (1 << 4), 181 182 /* adapter debug_flags */ 183 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 184 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 185 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 186 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 187 188 /* adapter intr handler flags */ 189 IHF_INTR_CLEAR_ON_INIT = (1 << 0), /* Driver calls t4_intr_clear */ 190 IHF_NO_SHOW = (1 << 1), /* Do not display intr info */ 191 IHF_VERBOSE = (1 << 2), /* Display extra intr info */ 192 IHF_FATAL_IFF_ENABLED = (1 << 3), /* Fatal only if enabled */ 193 IHF_IGNORE_IF_DISABLED = (1 << 4), /* Ignore if disabled */ 194 IHF_CLR_ALL_SET = (1 << 5), /* Clear all set bits */ 195 IHF_CLR_ALL_UNIGNORED = (1 << 6), /* Clear all unignored bits */ 196 IHF_RUN_ALL_ACTIONS = (1 << 7), /* As if all cause are set */ 197 }; 198 199 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING) 200 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0) 201 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0) 202 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 203 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 204 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 205 206 struct vi_info { 207 device_t dev; 208 struct port_info *pi; 209 struct adapter *adapter; 210 211 if_t ifp; 212 struct pfil_head *pfil; 213 214 unsigned long flags; 215 int if_flags; 216 217 uint16_t *rss, *nm_rss; 218 uint16_t viid; /* opaque VI identifier */ 219 uint16_t smt_idx; 220 uint16_t vin; 221 uint8_t vfvld; 222 int16_t xact_addr_filt;/* index of exact MAC address filter */ 223 uint16_t rss_size; /* size of VI's RSS table slice */ 224 uint16_t rss_base; /* start of VI's RSS table slice */ 225 int hashen; 226 227 int nintr; 228 int first_intr; 229 230 /* These need to be int as they are used in sysctl */ 231 int ntxq; /* # of tx queues */ 232 int first_txq; /* index of first tx queue */ 233 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 234 int nrxq; /* # of rx queues */ 235 int first_rxq; /* index of first rx queue */ 236 int nofldtxq; /* # of offload tx queues */ 237 int first_ofld_txq; /* index of first offload tx queue */ 238 int nofldrxq; /* # of offload rx queues */ 239 int first_ofld_rxq; /* index of first offload rx queue */ 240 int nnmtxq; 241 int first_nm_txq; 242 int nnmrxq; 243 int first_nm_rxq; 244 int tmr_idx; 245 int ofld_tmr_idx; 246 int pktc_idx; 247 int ofld_pktc_idx; 248 int qsize_rxq; 249 int qsize_txq; 250 251 struct timeval last_refreshed; 252 struct fw_vi_stats_vf stats; 253 struct mtx tick_mtx; 254 struct callout tick; 255 256 struct sysctl_ctx_list ctx; 257 struct sysctl_oid *rxq_oid; 258 struct sysctl_oid *txq_oid; 259 struct sysctl_oid *nm_rxq_oid; 260 struct sysctl_oid *nm_txq_oid; 261 struct sysctl_oid *ofld_rxq_oid; 262 struct sysctl_oid *ofld_txq_oid; 263 264 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 265 u_int txq_rr; 266 u_int rxq_rr; 267 }; 268 269 struct tx_ch_rl_params { 270 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 271 uint32_t maxrate; 272 }; 273 274 /* CLRL state */ 275 enum clrl_state { 276 CS_UNINITIALIZED = 0, 277 CS_PARAMS_SET, /* sw parameters have been set. */ 278 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 279 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 280 CS_HW_CONFIGURED /* configured in the hardware. */ 281 }; 282 283 /* CLRL flags */ 284 enum { 285 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 286 }; 287 288 struct tx_cl_rl_params { 289 enum clrl_state state; 290 int refcount; 291 uint8_t flags; 292 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 293 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 294 enum fw_sched_params_mode mode; /* aggr or per-flow */ 295 uint32_t maxrate; 296 uint16_t pktsize; 297 uint16_t burstsize; 298 }; 299 300 /* Tx scheduler parameters for a channel/port */ 301 struct tx_sched_params { 302 /* Channel Rate Limiter */ 303 struct tx_ch_rl_params ch_rl; 304 305 /* Class WRR */ 306 /* XXX */ 307 308 /* Class Rate Limiter (including the default pktsize and burstsize). */ 309 int pktsize; 310 int burstsize; 311 struct tx_cl_rl_params cl_rl[]; 312 }; 313 314 struct port_info { 315 device_t dev; 316 struct adapter *adapter; 317 318 struct vi_info *vi; 319 int nvi; 320 int up_vis; 321 int uld_vis; 322 bool vxlan_tcam_entry; 323 324 struct tx_sched_params *sched_params; 325 326 struct mtx pi_lock; 327 char lockname[16]; 328 unsigned long flags; 329 330 uint8_t hw_port; /* associated hardware port idx */ 331 int8_t mdio_addr; 332 uint8_t port_type; 333 uint8_t mod_type; 334 uint8_t port_id; 335 uint8_t tx_chan; /* tx TP c-channel */ 336 uint8_t rx_chan; /* rx TP c-channel */ 337 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 338 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 339 340 struct link_config link_cfg; 341 struct ifmedia media; 342 343 struct port_stats stats; 344 u_int tnl_cong_drops; 345 u_int tx_parse_error; 346 int fcs_reg; 347 uint64_t fcs_base; 348 349 struct sysctl_ctx_list ctx; 350 }; 351 352 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 353 354 struct cluster_metadata { 355 uma_zone_t zone; 356 caddr_t cl; 357 u_int refcount; 358 }; 359 360 struct fl_sdesc { 361 caddr_t cl; 362 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 363 int16_t moff; /* offset of metadata from cl */ 364 uint8_t zidx; 365 }; 366 367 struct tx_desc { 368 __be64 flit[8]; 369 }; 370 371 struct tx_sdesc { 372 struct mbuf *m; /* m_nextpkt linked chain of frames */ 373 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 374 }; 375 376 377 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 378 struct iq_desc { 379 struct rss_header rss; 380 uint8_t cpl[IQ_PAD]; 381 struct rsp_ctrl rsp; 382 }; 383 #undef IQ_PAD 384 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 385 386 enum { 387 /* iq type */ 388 IQ_OTHER = FW_IQ_IQTYPE_OTHER, 389 IQ_ETH = FW_IQ_IQTYPE_NIC, 390 IQ_OFLD = FW_IQ_IQTYPE_OFLD, 391 392 /* iq flags */ 393 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 394 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 395 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 396 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 397 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 398 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 399 400 /* iq state */ 401 IQS_DISABLED = 0, 402 IQS_BUSY = 1, 403 IQS_IDLE = 2, 404 405 /* netmap related flags */ 406 NM_OFF = 0, 407 NM_ON = 1, 408 NM_BUSY = 2, 409 }; 410 411 enum { 412 CPL_COOKIE_RESERVED = 0, 413 CPL_COOKIE_FILTER, 414 CPL_COOKIE_DDP0, 415 CPL_COOKIE_DDP1, 416 CPL_COOKIE_TOM, 417 CPL_COOKIE_HASHFILTER, 418 CPL_COOKIE_ETHOFLD, 419 CPL_COOKIE_KERN_TLS, 420 421 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 422 }; 423 424 /* 425 * Crypto replies use the low bit in the 64-bit cookie of CPL_FW6_PLD as a 426 * CPL cookie to identify the sender/receiver. 427 */ 428 enum { 429 CPL_FW6_COOKIE_CCR = 0, 430 CPL_FW6_COOKIE_KTLS, 431 432 NUM_CPL_FW6_COOKIES = 2 /* Low bits of cookie value. */ 433 }; 434 435 _Static_assert(powerof2(NUM_CPL_FW6_COOKIES), 436 "NUM_CPL_FW6_COOKIES must be a power of 2"); 437 438 #define CPL_FW6_COOKIE_MASK (NUM_CPL_FW6_COOKIES - 1) 439 440 #define CPL_FW6_PLD_COOKIE(cpl) (be64toh((cpl)->data[1]) & ~CPL_FW6_COOKIE_MASK) 441 442 struct sge_iq; 443 struct rss_header; 444 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 445 struct mbuf *); 446 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 447 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 448 449 /* 450 * Ingress Queue: T4 is producer, driver is consumer. 451 */ 452 struct sge_iq { 453 uint16_t flags; 454 uint8_t qtype; 455 volatile int state; 456 struct adapter *adapter; 457 struct iq_desc *desc; /* KVA of descriptor ring */ 458 int8_t intr_pktc_idx; /* packet count threshold index */ 459 uint8_t gen; /* generation bit */ 460 uint8_t intr_params; /* interrupt holdoff parameters */ 461 int8_t cong_drop; /* congestion drop settings for the queue */ 462 uint16_t qsize; /* size (# of entries) of the queue */ 463 uint16_t sidx; /* index of the entry with the status page */ 464 uint16_t cidx; /* consumer index */ 465 uint16_t cntxt_id; /* SGE context id for the iq */ 466 uint16_t abs_id; /* absolute SGE id for the iq */ 467 int16_t intr_idx; /* interrupt used by the queue */ 468 469 STAILQ_ENTRY(sge_iq) link; 470 471 bus_dma_tag_t desc_tag; 472 bus_dmamap_t desc_map; 473 bus_addr_t ba; /* bus address of descriptor ring */ 474 }; 475 476 enum { 477 /* eq type */ 478 EQ_CTRL = 1, 479 EQ_ETH = 2, 480 EQ_OFLD = 3, 481 482 /* eq flags */ 483 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 484 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 485 EQ_ENABLED = (1 << 3), /* open for business */ 486 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 487 }; 488 489 /* Listed in order of preference. Update t4_sysctls too if you change these */ 490 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 491 492 /* 493 * Egress Queue: driver is producer, T4 is consumer. 494 * 495 * Note: A free list is an egress queue (driver produces the buffers and T4 496 * consumes them) but it's special enough to have its own struct (see sge_fl). 497 */ 498 struct sge_eq { 499 unsigned int flags; /* MUST be first */ 500 unsigned int cntxt_id; /* SGE context id for the eq */ 501 unsigned int abs_id; /* absolute SGE id for the eq */ 502 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 503 uint8_t doorbells; 504 uint8_t port_id; /* port_id of the port associated with the eq */ 505 uint8_t tx_chan; /* tx channel used by the eq */ 506 uint8_t hw_port; /* hw port used by the eq */ 507 struct mtx eq_lock; 508 509 struct tx_desc *desc; /* KVA of descriptor ring */ 510 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 511 u_int udb_qid; /* relative qid within the doorbell page */ 512 uint16_t sidx; /* index of the entry with the status page */ 513 uint16_t cidx; /* consumer idx (desc idx) */ 514 uint16_t pidx; /* producer idx (desc idx) */ 515 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 516 uint16_t dbidx; /* pidx of the most recent doorbell */ 517 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 518 volatile u_int equiq; /* EQUIQ outstanding */ 519 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 520 521 bus_dma_tag_t desc_tag; 522 bus_dmamap_t desc_map; 523 bus_addr_t ba; /* bus address of descriptor ring */ 524 char lockname[16]; 525 }; 526 527 struct rx_buf_info { 528 uma_zone_t zone; /* zone that this cluster comes from */ 529 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 530 * hwsize[hwidx1] = size1. No spare. */ 531 uint16_t size2; /* hwsize[hwidx2] = size2. 532 * spare in cluster = size1 - size2. */ 533 int8_t hwidx1; /* SGE bufsize idx for size1 */ 534 int8_t hwidx2; /* SGE bufsize idx for size2 */ 535 uint8_t type; /* EXT_xxx type of the cluster */ 536 }; 537 538 enum { 539 NUM_MEMWIN = 3, 540 541 MEMWIN0_APERTURE = 2048, 542 MEMWIN0_BASE = 0x1b800, 543 544 MEMWIN1_APERTURE = 32768, 545 MEMWIN1_BASE = 0x28000, 546 547 MEMWIN2_APERTURE_T4 = 65536, 548 MEMWIN2_BASE_T4 = 0x30000, 549 550 MEMWIN2_APERTURE_T5 = 128 * 1024, 551 MEMWIN2_BASE_T5 = 0x60000, 552 }; 553 554 struct memwin { 555 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 556 uint32_t mw_base; /* constant after setup_memwin */ 557 uint32_t mw_aperture; /* ditto */ 558 uint32_t mw_curpos; /* protected by mw_lock */ 559 }; 560 561 enum { 562 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 563 FL_DOOMED = (1 << 1), /* about to be destroyed */ 564 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 565 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 566 }; 567 568 #define FL_RUNNING_LOW(fl) \ 569 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 570 #define FL_NOT_RUNNING_LOW(fl) \ 571 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 572 573 struct sge_fl { 574 struct mtx fl_lock; 575 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 576 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 577 uint16_t zidx; /* refill zone idx */ 578 uint16_t safe_zidx; 579 uint16_t lowat; /* # of buffers <= this means fl needs help */ 580 int flags; 581 uint16_t buf_boundary; 582 583 /* The 16b idx all deal with hw descriptors */ 584 uint16_t dbidx; /* hw pidx after last doorbell */ 585 uint16_t sidx; /* index of status page */ 586 volatile uint16_t hw_cidx; 587 588 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 589 uint32_t cidx; /* consumer index */ 590 uint32_t pidx; /* producer index */ 591 592 uint32_t dbval; 593 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 594 volatile uint32_t *udb; 595 596 uint64_t cl_allocated; /* # of clusters allocated */ 597 uint64_t cl_recycled; /* # of clusters recycled */ 598 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 599 600 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 601 struct mbuf *m0; 602 struct mbuf **pnext; 603 u_int remaining; 604 605 uint16_t qsize; /* # of hw descriptors (status page included) */ 606 uint16_t cntxt_id; /* SGE context id for the freelist */ 607 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 608 bus_dma_tag_t desc_tag; 609 bus_dmamap_t desc_map; 610 char lockname[16]; 611 bus_addr_t ba; /* bus address of descriptor ring */ 612 }; 613 614 struct mp_ring; 615 616 struct txpkts { 617 uint8_t wr_type; /* type 0 or type 1 */ 618 uint8_t npkt; /* # of packets in this work request */ 619 uint8_t len16; /* # of 16B pieces used by this work request */ 620 uint8_t score; 621 uint8_t max_npkt; /* maximum number of packets allowed */ 622 uint16_t plen; /* total payload (sum of all packets) */ 623 624 /* straight from fw_eth_tx_pkts_vm_wr. */ 625 __u8 ethmacdst[6]; 626 __u8 ethmacsrc[6]; 627 __be16 ethtype; 628 __be16 vlantci; 629 630 struct mbuf *mb[15]; 631 }; 632 633 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 634 struct sge_txq { 635 struct sge_eq eq; /* MUST be first */ 636 637 if_t ifp; /* the interface this txq belongs to */ 638 struct mp_ring *r; /* tx software ring */ 639 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 640 struct sglist *gl; 641 __be32 cpl_ctrl0; /* for convenience */ 642 int tc_idx; /* traffic class */ 643 uint64_t last_tx; /* cycle count when eth_tx was last called */ 644 struct txpkts txp; 645 646 struct task tx_reclaim_task; 647 /* stats for common events first */ 648 649 uint64_t txcsum; /* # of times hardware assisted with checksum */ 650 uint64_t tso_wrs; /* # of TSO work requests */ 651 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 652 uint64_t imm_wrs; /* # of work requests with immediate data */ 653 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 654 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 655 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 656 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 657 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 658 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 659 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 660 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 661 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 662 uint64_t vxlan_txcsum; 663 664 uint64_t kern_tls_records; 665 uint64_t kern_tls_short; 666 uint64_t kern_tls_partial; 667 uint64_t kern_tls_full; 668 uint64_t kern_tls_octets; 669 uint64_t kern_tls_waste; 670 uint64_t kern_tls_header; 671 uint64_t kern_tls_fin_short; 672 uint64_t kern_tls_cbc; 673 uint64_t kern_tls_gcm; 674 union { 675 struct { 676 /* T6 only. */ 677 uint64_t kern_tls_options; 678 uint64_t kern_tls_fin; 679 }; 680 struct { 681 /* T7 only. */ 682 uint64_t kern_tls_ghash_received; 683 uint64_t kern_tls_ghash_requested; 684 uint64_t kern_tls_lso; 685 uint64_t kern_tls_partial_ghash; 686 uint64_t kern_tls_splitmode; 687 uint64_t kern_tls_trailer; 688 }; 689 }; 690 691 /* stats for not-that-common events */ 692 693 /* Optional scratch space for constructing work requests. */ 694 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 695 } __aligned(CACHE_LINE_SIZE); 696 697 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 698 struct sge_rxq { 699 struct sge_iq iq; /* MUST be first */ 700 struct sge_fl fl; /* MUST follow iq */ 701 702 if_t ifp; /* the interface this rxq belongs to */ 703 struct lro_ctrl lro; /* LRO state */ 704 705 /* stats for common events first */ 706 707 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 708 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 709 uint64_t vxlan_rxcsum; 710 711 /* stats for not-that-common events */ 712 713 } __aligned(CACHE_LINE_SIZE); 714 715 static inline struct sge_rxq * 716 iq_to_rxq(struct sge_iq *iq) 717 { 718 719 return (__containerof(iq, struct sge_rxq, iq)); 720 } 721 722 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 723 struct sge_ofld_rxq { 724 struct sge_iq iq; /* MUST be first */ 725 struct sge_fl fl; /* MUST follow iq */ 726 counter_u64_t rx_iscsi_ddp_setup_ok; 727 counter_u64_t rx_iscsi_ddp_setup_error; 728 uint64_t rx_iscsi_ddp_pdus; 729 uint64_t rx_iscsi_ddp_octets; 730 uint64_t rx_iscsi_fl_pdus; 731 uint64_t rx_iscsi_fl_octets; 732 uint64_t rx_iscsi_padding_errors; 733 uint64_t rx_iscsi_header_digest_errors; 734 uint64_t rx_iscsi_data_digest_errors; 735 counter_u64_t rx_nvme_ddp_setup_ok; 736 counter_u64_t rx_nvme_ddp_setup_no_stag; 737 counter_u64_t rx_nvme_ddp_setup_error; 738 counter_u64_t rx_nvme_ddp_pdus; 739 counter_u64_t rx_nvme_ddp_octets; 740 counter_u64_t rx_nvme_fl_pdus; 741 counter_u64_t rx_nvme_fl_octets; 742 counter_u64_t rx_nvme_invalid_headers; 743 counter_u64_t rx_nvme_header_digest_errors; 744 counter_u64_t rx_nvme_data_digest_errors; 745 uint64_t rx_aio_ddp_jobs; 746 uint64_t rx_aio_ddp_octets; 747 u_long rx_toe_tls_records; 748 u_long rx_toe_tls_octets; 749 u_long rx_toe_ddp_octets; 750 counter_u64_t ddp_buffer_alloc; 751 counter_u64_t ddp_buffer_reuse; 752 counter_u64_t ddp_buffer_free; 753 } __aligned(CACHE_LINE_SIZE); 754 755 static inline struct sge_ofld_rxq * 756 iq_to_ofld_rxq(struct sge_iq *iq) 757 { 758 759 return (__containerof(iq, struct sge_ofld_rxq, iq)); 760 } 761 762 struct wrqe { 763 STAILQ_ENTRY(wrqe) link; 764 struct sge_wrq *wrq; 765 int wr_len; 766 char wr[] __aligned(16); 767 }; 768 769 struct wrq_cookie { 770 TAILQ_ENTRY(wrq_cookie) link; 771 int ndesc; 772 int pidx; 773 }; 774 775 /* 776 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 777 * are of this type. 778 */ 779 struct sge_wrq { 780 struct sge_eq eq; /* MUST be first */ 781 782 struct adapter *adapter; 783 struct task wrq_tx_task; 784 785 /* Tx desc reserved but WR not "committed" yet. */ 786 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 787 788 /* List of WRs ready to go out as soon as descriptors are available. */ 789 STAILQ_HEAD(, wrqe) wr_list; 790 u_int nwr_pending; 791 u_int ndesc_needed; 792 793 /* stats for common events first */ 794 795 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 796 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 797 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 798 799 /* stats for not-that-common events */ 800 801 /* 802 * Scratch space for work requests that wrap around after reaching the 803 * status page, and some information about the last WR that used it. 804 */ 805 uint16_t ss_pidx; 806 uint16_t ss_len; 807 uint8_t ss[SGE_MAX_WR_LEN]; 808 809 } __aligned(CACHE_LINE_SIZE); 810 811 /* ofld_txq: SGE egress queue + miscellaneous items */ 812 struct sge_ofld_txq { 813 struct sge_wrq wrq; 814 counter_u64_t tx_iscsi_pdus; 815 counter_u64_t tx_iscsi_octets; 816 counter_u64_t tx_iscsi_iso_wrs; 817 counter_u64_t tx_nvme_pdus; 818 counter_u64_t tx_nvme_octets; 819 counter_u64_t tx_nvme_iso_wrs; 820 counter_u64_t tx_aio_jobs; 821 counter_u64_t tx_aio_octets; 822 counter_u64_t tx_toe_tls_records; 823 counter_u64_t tx_toe_tls_octets; 824 } __aligned(CACHE_LINE_SIZE); 825 826 static inline int 827 ofld_txq_group(int val, int mask) 828 { 829 const uint32_t ngroup = 1 << bitcount32(mask); 830 const int mshift = ffs(mask) - 1; 831 const uint32_t gmask = ngroup - 1; 832 833 return (val >> mshift & gmask); 834 } 835 836 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 837 struct sge_nm_rxq { 838 /* Items used by the driver rx ithread are in this cacheline. */ 839 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 840 u_int nid; /* netmap ring # for this queue */ 841 struct vi_info *vi; 842 843 struct iq_desc *iq_desc; 844 uint16_t iq_abs_id; 845 uint16_t iq_cntxt_id; 846 uint16_t iq_cidx; 847 uint16_t iq_sidx; 848 uint8_t iq_gen; 849 uint32_t fl_sidx; 850 851 /* Items used by netmap rxsync are in this cacheline. */ 852 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 853 uint16_t fl_cntxt_id; 854 uint32_t fl_pidx; 855 uint32_t fl_sidx2; /* copy of fl_sidx */ 856 uint32_t fl_db_val; 857 u_int fl_db_saved; 858 u_int fl_db_threshold; /* in descriptors */ 859 u_int fl_hwidx:4; 860 861 /* 862 * fl_cidx is used by both the ithread and rxsync, the rest are not used 863 * in the rx fast path. 864 */ 865 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 866 867 bus_dma_tag_t iq_desc_tag; 868 bus_dmamap_t iq_desc_map; 869 bus_addr_t iq_ba; 870 int intr_idx; 871 872 bus_dma_tag_t fl_desc_tag; 873 bus_dmamap_t fl_desc_map; 874 bus_addr_t fl_ba; 875 }; 876 877 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 878 struct sge_nm_txq { 879 struct tx_desc *desc; 880 uint16_t cidx; 881 uint16_t pidx; 882 uint16_t sidx; 883 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 884 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 885 uint16_t dbidx; /* pidx of the most recent doorbell */ 886 uint8_t doorbells; 887 volatile uint32_t *udb; 888 u_int udb_qid; 889 u_int cntxt_id; 890 __be32 cpl_ctrl0; /* for convenience */ 891 __be32 op_pkd; /* ditto */ 892 u_int nid; /* netmap ring # for this queue */ 893 894 /* infrequently used items after this */ 895 896 bus_dma_tag_t desc_tag; 897 bus_dmamap_t desc_map; 898 bus_addr_t ba; 899 int iqidx; 900 } __aligned(CACHE_LINE_SIZE); 901 902 struct sge { 903 int nctrlq; /* total # of control queues */ 904 int nrxq; /* total # of Ethernet rx queues */ 905 int ntxq; /* total # of Ethernet tx queues */ 906 int nofldrxq; /* total # of TOE rx queues */ 907 int nofldtxq; /* total # of TOE tx queues */ 908 int nnmrxq; /* total # of netmap rx queues */ 909 int nnmtxq; /* total # of netmap tx queues */ 910 int niq; /* total # of ingress queues */ 911 int neq; /* total # of egress queues */ 912 913 struct sge_iq fwq; /* Firmware event queue */ 914 struct sge_wrq *ctrlq; /* Control queues */ 915 struct sge_txq *txq; /* NIC tx queues */ 916 struct sge_rxq *rxq; /* NIC rx queues */ 917 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 918 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 919 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 920 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 921 922 uint16_t iq_start; /* first cntxt_id */ 923 uint16_t iq_base; /* first abs_id */ 924 int eq_start; /* first cntxt_id */ 925 int eq_base; /* first abs_id */ 926 int iqmap_sz; 927 int eqmap_sz; 928 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 929 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 930 931 int8_t safe_zidx; 932 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 933 }; 934 935 struct devnames { 936 const char *nexus_name; 937 const char *ifnet_name; 938 const char *vi_ifnet_name; 939 const char *pf03_drv_name; 940 const char *vf_nexus_name; 941 const char *vf_ifnet_name; 942 }; 943 944 struct clip_entry; 945 946 #define CNT_CAL_INFO 3 947 struct clock_sync { 948 uint64_t hw_cur; 949 uint64_t hw_prev; 950 sbintime_t sbt_cur; 951 sbintime_t sbt_prev; 952 seqc_t gen; 953 }; 954 955 struct adapter { 956 SLIST_ENTRY(adapter) link; 957 device_t dev; 958 struct cdev *cdev; 959 const struct devnames *names; 960 961 /* PCIe register resources */ 962 int regs_rid; 963 struct resource *regs_res; 964 int msix_rid; 965 struct resource *msix_res; 966 bus_space_handle_t bh; 967 bus_space_tag_t bt; 968 bus_size_t mmio_len; 969 int udbs_rid; 970 struct resource *udbs_res; 971 volatile uint8_t *udbs_base; 972 973 unsigned int pf; 974 unsigned int mbox; 975 unsigned int vpd_busy; 976 unsigned int vpd_flag; 977 978 /* Interrupt information */ 979 int intr_type; 980 int intr_count; 981 struct irq { 982 struct resource *res; 983 int rid; 984 void *tag; 985 struct sge_rxq *rxq; 986 struct sge_nm_rxq *nm_rxq; 987 } __aligned(CACHE_LINE_SIZE) *irq; 988 int sge_gts_reg; 989 int sge_kdoorbell_reg; 990 991 bus_dma_tag_t dmat; /* Parent DMA tag */ 992 993 struct sge sge; 994 int lro_timeout; 995 int sc_do_rxcopy; 996 997 int vxlan_port; 998 u_int vxlan_refcount; 999 int rawf_base; 1000 int nrawf; 1001 u_int vlan_id; 1002 1003 struct taskqueue *tq[MAX_NPORTS]; /* General purpose taskqueues */ 1004 struct port_info *port[MAX_NPORTS]; 1005 uint8_t chan_map[MAX_NCHAN]; /* tx_chan -> port_id */ 1006 uint8_t port_map[MAX_NPORTS]; /* hw_port -> port_id */ 1007 1008 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 1009 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 1010 u_long clip_mask; 1011 int clip_gen; 1012 struct timeout_task clip_task; 1013 1014 void *tom_softc; /* (struct tom_data *) */ 1015 struct tom_tunables tt; 1016 struct t4_offload_policy *policy; 1017 struct rwlock policy_lock; 1018 1019 void *iwarp_softc; /* (struct c4iw_dev *) */ 1020 struct iw_tunables iwt; 1021 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 1022 void *nvme_ulp_softc; /* (struct nvmf_che_adapter *) */ 1023 struct l2t_data *l2t; /* L2 table */ 1024 struct smt_data *smt; /* Source MAC Table */ 1025 struct tid_info tids; 1026 vmem_t *key_map; 1027 struct tls_tunables tlst; 1028 1029 vmem_t *pbl_arena; 1030 vmem_t *stag_arena; 1031 1032 uint8_t doorbells; 1033 int offload_map; /* port_id's with IFCAP_TOE enabled */ 1034 int bt_map; /* hw_port's that are BASE-T */ 1035 int active_ulds; /* ULDs activated on this adapter */ 1036 int flags; 1037 int debug_flags; 1038 int error_flags; /* Used by error handler and live reset. */ 1039 int intr_flags; /* Used by interrupt setup/handlers. */ 1040 1041 char ifp_lockname[16]; 1042 struct mtx ifp_lock; 1043 if_t ifp; /* tracer ifp */ 1044 struct ifmedia media; 1045 int traceq; /* iq used by all tracers, -1 if none */ 1046 int tracer_valid; /* bitmap of valid tracers */ 1047 int tracer_enabled; /* bitmap of enabled tracers */ 1048 1049 char fw_version[16]; 1050 char tp_version[16]; 1051 char er_version[16]; 1052 char bs_version[16]; 1053 char cfg_file[32]; 1054 u_int cfcsum; 1055 struct adapter_params params; 1056 const struct chip_params *chip_params; 1057 struct t4_virt_res vres; 1058 1059 uint16_t nbmcaps; 1060 uint16_t linkcaps; 1061 uint16_t switchcaps; 1062 uint16_t nvmecaps; 1063 uint16_t niccaps; 1064 uint16_t toecaps; 1065 uint16_t rdmacaps; 1066 uint16_t cryptocaps; 1067 uint16_t iscsicaps; 1068 uint16_t fcoecaps; 1069 1070 struct sysctl_ctx_list ctx; 1071 struct sysctl_oid *ctrlq_oid; 1072 struct sysctl_oid *fwq_oid; 1073 1074 struct mtx sc_lock; 1075 char lockname[16]; 1076 1077 /* Starving free lists */ 1078 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 1079 TAILQ_HEAD(, sge_fl) sfl; 1080 struct callout sfl_callout; 1081 struct callout cal_callout; 1082 struct clock_sync cal_info[CNT_CAL_INFO]; 1083 int cal_current; 1084 int cal_count; 1085 uint32_t cal_gen; 1086 1087 /* 1088 * Driver code that can run when the adapter is suspended must use this 1089 * lock or a synchronized_op and check for HW_OFF_LIMITS before 1090 * accessing hardware. 1091 * 1092 * XXX: could be changed to rwlock. wlock in suspend/resume and for 1093 * indirect register access, rlock everywhere else. 1094 */ 1095 struct mtx reg_lock; 1096 1097 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 1098 1099 struct mtx tc_lock; 1100 struct task tc_task; 1101 1102 struct task fatal_error_task; 1103 struct task reset_task; 1104 const void *reset_thread; 1105 int num_resets; 1106 int incarnation; 1107 1108 const char *last_op; 1109 const void *last_op_thr; 1110 int last_op_flags; 1111 1112 int swintr; 1113 int sensor_resets; 1114 1115 struct callout ktls_tick; 1116 }; 1117 1118 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1119 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1120 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1121 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1122 1123 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1124 KASSERT(IS_BUSY(sc) && \ 1125 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1126 ("%s: operation not synchronized.", __func__)) 1127 1128 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1129 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1130 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1131 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1132 1133 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1134 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1135 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1136 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1137 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1138 1139 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1140 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1141 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1142 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1143 1144 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1145 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1146 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1147 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1148 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1149 1150 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1151 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1152 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1153 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1154 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1155 1156 #define for_each_txq(vi, iter, q) \ 1157 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1158 iter < vi->ntxq; ++iter, ++q) 1159 #define for_each_rxq(vi, iter, q) \ 1160 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1161 iter < vi->nrxq; ++iter, ++q) 1162 #define for_each_ofld_txq(vi, iter, q) \ 1163 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1164 iter < vi->nofldtxq; ++iter, ++q) 1165 #define for_each_ofld_rxq(vi, iter, q) \ 1166 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1167 iter < vi->nofldrxq; ++iter, ++q) 1168 #define for_each_nm_txq(vi, iter, q) \ 1169 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1170 iter < vi->nnmtxq; ++iter, ++q) 1171 #define for_each_nm_rxq(vi, iter, q) \ 1172 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1173 iter < vi->nnmrxq; ++iter, ++q) 1174 #define for_each_vi(_pi, _iter, _vi) \ 1175 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1176 ++(_iter), ++(_vi)) 1177 1178 #define IDXINCR(idx, incr, wrap) do { \ 1179 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1180 } while (0) 1181 #define IDXDIFF(head, tail, wrap) \ 1182 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1183 1184 /* One for errors, one for firmware events */ 1185 #define T4_EXTRA_INTR 2 1186 1187 /* One for firmware events */ 1188 #define T4VF_EXTRA_INTR 1 1189 1190 static inline int 1191 forwarding_intr_to_fwq(struct adapter *sc) 1192 { 1193 1194 return (sc->intr_count == 1); 1195 } 1196 1197 /* Works reliably inside a synch_op or with reg_lock held. */ 1198 static inline bool 1199 hw_off_limits(struct adapter *sc) 1200 { 1201 const int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1202 1203 return (__predict_false(off_limits != 0)); 1204 } 1205 1206 /* Works reliably inside a synch_op or with reg_lock held. */ 1207 static inline bool 1208 hw_all_ok(struct adapter *sc) 1209 { 1210 const int not_ok = atomic_load_int(&sc->error_flags) & 1211 (ADAP_STOPPED | HW_OFF_LIMITS); 1212 1213 return (__predict_true(not_ok == 0)); 1214 } 1215 1216 static inline int 1217 mbuf_nsegs(struct mbuf *m) 1218 { 1219 M_ASSERTPKTHDR(m); 1220 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 1221 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1222 1223 return (m->m_pkthdr.inner_l5hlen); 1224 } 1225 1226 static inline void 1227 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1228 { 1229 M_ASSERTPKTHDR(m); 1230 m->m_pkthdr.inner_l5hlen = nsegs; 1231 } 1232 1233 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 1234 #define MC_NOMAP 0x01 1235 #define MC_RAW_WR 0x02 1236 #define MC_TLS 0x04 1237 1238 static inline int 1239 mbuf_cflags(struct mbuf *m) 1240 { 1241 M_ASSERTPKTHDR(m); 1242 return (m->m_pkthdr.PH_loc.eight[4]); 1243 } 1244 1245 static inline void 1246 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 1247 { 1248 M_ASSERTPKTHDR(m); 1249 m->m_pkthdr.PH_loc.eight[4] = flags; 1250 } 1251 1252 static inline int 1253 mbuf_len16(struct mbuf *m) 1254 { 1255 int n; 1256 1257 M_ASSERTPKTHDR(m); 1258 n = m->m_pkthdr.PH_loc.eight[0]; 1259 if (!(mbuf_cflags(m) & MC_TLS)) 1260 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1261 1262 return (n); 1263 } 1264 1265 static inline void 1266 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1267 { 1268 M_ASSERTPKTHDR(m); 1269 if (!(mbuf_cflags(m) & MC_TLS)) 1270 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 1271 m->m_pkthdr.PH_loc.eight[0] = len16; 1272 } 1273 1274 static inline uint32_t 1275 t4_read_reg(struct adapter *sc, uint32_t reg) 1276 { 1277 if (hw_off_limits(sc)) 1278 MPASS(curthread == sc->reset_thread); 1279 return bus_space_read_4(sc->bt, sc->bh, reg); 1280 } 1281 1282 static inline void 1283 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1284 { 1285 if (hw_off_limits(sc)) 1286 MPASS(curthread == sc->reset_thread); 1287 bus_space_write_4(sc->bt, sc->bh, reg, val); 1288 } 1289 1290 static inline uint64_t 1291 t4_read_reg64(struct adapter *sc, uint32_t reg) 1292 { 1293 if (hw_off_limits(sc)) 1294 MPASS(curthread == sc->reset_thread); 1295 #ifdef __LP64__ 1296 return bus_space_read_8(sc->bt, sc->bh, reg); 1297 #else 1298 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1299 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1300 1301 #endif 1302 } 1303 1304 static inline void 1305 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1306 { 1307 if (hw_off_limits(sc)) 1308 MPASS(curthread == sc->reset_thread); 1309 #ifdef __LP64__ 1310 bus_space_write_8(sc->bt, sc->bh, reg, val); 1311 #else 1312 bus_space_write_4(sc->bt, sc->bh, reg, val); 1313 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1314 #endif 1315 } 1316 1317 static inline void 1318 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1319 { 1320 if (hw_off_limits(sc)) 1321 MPASS(curthread == sc->reset_thread); 1322 *val = pci_read_config(sc->dev, reg, 1); 1323 } 1324 1325 static inline void 1326 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1327 { 1328 if (hw_off_limits(sc)) 1329 MPASS(curthread == sc->reset_thread); 1330 pci_write_config(sc->dev, reg, val, 1); 1331 } 1332 1333 static inline void 1334 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1335 { 1336 1337 if (hw_off_limits(sc)) 1338 MPASS(curthread == sc->reset_thread); 1339 *val = pci_read_config(sc->dev, reg, 2); 1340 } 1341 1342 static inline void 1343 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1344 { 1345 if (hw_off_limits(sc)) 1346 MPASS(curthread == sc->reset_thread); 1347 pci_write_config(sc->dev, reg, val, 2); 1348 } 1349 1350 static inline void 1351 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1352 { 1353 if (hw_off_limits(sc)) 1354 MPASS(curthread == sc->reset_thread); 1355 *val = pci_read_config(sc->dev, reg, 4); 1356 } 1357 1358 static inline void 1359 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1360 { 1361 if (hw_off_limits(sc)) 1362 MPASS(curthread == sc->reset_thread); 1363 pci_write_config(sc->dev, reg, val, 4); 1364 } 1365 1366 static inline struct port_info * 1367 adap2pinfo(struct adapter *sc, int idx) 1368 { 1369 1370 return (sc->port[idx]); 1371 } 1372 1373 static inline void 1374 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1375 { 1376 1377 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1378 } 1379 1380 static inline int 1381 tx_resume_threshold(struct sge_eq *eq) 1382 { 1383 1384 /* not quite the same as qsize / 4, but this will do. */ 1385 return (eq->sidx / 4); 1386 } 1387 1388 static inline int 1389 t4_use_ldst(struct adapter *sc) 1390 { 1391 1392 #ifdef notyet 1393 return (sc->flags & FW_OK || !sc->use_bd); 1394 #else 1395 return (0); 1396 #endif 1397 } 1398 1399 static inline void 1400 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1401 const char *msg, const __be64 *const p, const bool err) 1402 { 1403 1404 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1405 return; 1406 if (p != NULL) { 1407 log(err ? LOG_ERR : LOG_DEBUG, 1408 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1409 "%016llx %016llx %016llx %016llx\n", 1410 device_get_nameunit(sc->dev), mbox, msg, 1411 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1412 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1413 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1414 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1415 } else { 1416 log(err ? LOG_ERR : LOG_DEBUG, 1417 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1418 "%016llx %016llx %016llx %016llx\n", 1419 device_get_nameunit(sc->dev), mbox, msg, 1420 (long long)t4_read_reg64(sc, reg), 1421 (long long)t4_read_reg64(sc, reg + 8), 1422 (long long)t4_read_reg64(sc, reg + 16), 1423 (long long)t4_read_reg64(sc, reg + 24), 1424 (long long)t4_read_reg64(sc, reg + 32), 1425 (long long)t4_read_reg64(sc, reg + 40), 1426 (long long)t4_read_reg64(sc, reg + 48), 1427 (long long)t4_read_reg64(sc, reg + 56)); 1428 } 1429 } 1430 1431 /* t4_main.c */ 1432 extern int t4_ntxq; 1433 extern int t4_nrxq; 1434 extern int t4_intr_types; 1435 extern int t4_tmr_idx; 1436 extern int t4_pktc_idx; 1437 extern unsigned int t4_qsize_rxq; 1438 extern unsigned int t4_qsize_txq; 1439 extern int t4_ddp_rcvbuf_len; 1440 extern unsigned int t4_ddp_rcvbuf_cache; 1441 extern device_method_t cxgbe_methods[]; 1442 1443 int t4_os_find_pci_capability(struct adapter *, int); 1444 void t4_os_portmod_changed(struct port_info *); 1445 void t4_os_link_changed(struct port_info *); 1446 void t4_iterate(void (*)(struct adapter *, void *), void *); 1447 void t4_init_devnames(struct adapter *); 1448 void t4_add_adapter(struct adapter *); 1449 int t4_detach_common(device_t); 1450 int t4_map_bars_0_and_4(struct adapter *); 1451 int t4_map_bar_2(struct adapter *); 1452 int t4_adj_doorbells(struct adapter *); 1453 int t4_setup_intr_handlers(struct adapter *); 1454 void t4_sysctls(struct adapter *); 1455 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1456 void end_synchronized_op(struct adapter *, int); 1457 void begin_vi_detach(struct adapter *, struct vi_info *); 1458 void end_vi_detach(struct adapter *, struct vi_info *); 1459 int update_mac_settings(if_t, int); 1460 int adapter_init(struct adapter *); 1461 int vi_init(struct vi_info *); 1462 void vi_sysctls(struct vi_info *); 1463 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1464 int alloc_atid(struct adapter *, void *); 1465 void *lookup_atid(struct adapter *, int); 1466 void free_atid(struct adapter *, int); 1467 void release_tid(struct adapter *, int, struct sge_wrq *); 1468 int cxgbe_media_change(if_t); 1469 void cxgbe_media_status(if_t, struct ifmediareq *); 1470 void t4_os_cim_err(struct adapter *); 1471 int suspend_adapter(struct adapter *); 1472 int resume_adapter(struct adapter *); 1473 int toe_capability(struct vi_info *, bool); 1474 1475 #ifdef KERN_TLS 1476 /* t6_kern_tls.c */ 1477 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1478 struct m_snd_tag **); 1479 void t6_ktls_modload(void); 1480 void t6_ktls_modunload(void); 1481 int t6_ktls_try(if_t, struct socket *, struct ktls_session *); 1482 int t6_ktls_parse_pkt(struct mbuf *); 1483 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1484 1485 /* t7_kern_tls.c */ 1486 int t7_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1487 struct m_snd_tag **); 1488 void t7_ktls_modload(void); 1489 void t7_ktls_modunload(void); 1490 int t7_ktls_parse_pkt(struct mbuf *); 1491 int t7_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1492 #endif 1493 1494 /* t4_keyctx.c */ 1495 struct auth_hash; 1496 union authctx; 1497 #ifdef KERN_TLS 1498 struct ktls_session; 1499 struct tls_key_req; 1500 struct tls_keyctx; 1501 #endif 1502 1503 void t4_aes_getdeckey(void *, const void *, unsigned int); 1504 void t4_copy_partial_hash(int, union authctx *, void *); 1505 void t4_init_gmac_hash(const char *, int, char *); 1506 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1507 char *); 1508 #ifdef KERN_TLS 1509 u_int t4_tls_key_info_size(const struct ktls_session *); 1510 int t4_tls_proto_ver(const struct ktls_session *); 1511 int t4_tls_cipher_mode(const struct ktls_session *); 1512 int t4_tls_auth_mode(const struct ktls_session *); 1513 int t4_tls_hmac_ctrl(const struct ktls_session *); 1514 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1515 int t4_alloc_tls_keyid(struct adapter *); 1516 void t4_free_tls_keyid(struct adapter *, int); 1517 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1518 struct tls_key_req *); 1519 #endif 1520 1521 #ifdef DEV_NETMAP 1522 /* t4_netmap.c */ 1523 struct sge_nm_rxq; 1524 void cxgbe_nm_attach(struct vi_info *); 1525 void cxgbe_nm_detach(struct vi_info *); 1526 void service_nm_rxq(struct sge_nm_rxq *); 1527 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1528 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1529 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1530 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1531 #endif 1532 1533 /* t4_sge.c */ 1534 void t4_sge_modload(void); 1535 void t4_sge_modunload(void); 1536 uint64_t t4_sge_extfree_refs(void); 1537 void t4_tweak_chip_settings(struct adapter *); 1538 int t4_verify_chip_settings(struct adapter *); 1539 void t4_init_rx_buf_info(struct adapter *); 1540 int t4_create_dma_tag(struct adapter *); 1541 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1542 struct sysctl_oid_list *); 1543 int t4_destroy_dma_tag(struct adapter *); 1544 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1545 bus_addr_t *, void **); 1546 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1547 void *); 1548 void free_fl_buffers(struct adapter *, struct sge_fl *); 1549 int t4_setup_adapter_queues(struct adapter *); 1550 int t4_teardown_adapter_queues(struct adapter *); 1551 int t4_setup_vi_queues(struct vi_info *); 1552 int t4_teardown_vi_queues(struct vi_info *); 1553 void t4_intr_all(void *); 1554 void t4_intr(void *); 1555 #ifdef DEV_NETMAP 1556 void t4_nm_intr(void *); 1557 void t4_vi_intr(void *); 1558 #endif 1559 void t4_intr_err(void *); 1560 void t4_intr_evt(void *); 1561 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1562 void t4_update_fl_bufsize(if_t); 1563 struct mbuf *alloc_wr_mbuf(int, int); 1564 int parse_pkt(struct mbuf **, bool); 1565 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1566 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1567 int t4_sge_set_conm_context(struct adapter *, int, int, int); 1568 void t4_register_an_handler(an_handler_t); 1569 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1570 void t4_register_cpl_handler(int, cpl_handler_t); 1571 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1572 #ifdef RATELIMIT 1573 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1574 #endif 1575 1576 /* t4_tracer.c */ 1577 struct t4_tracer; 1578 void t4_tracer_modload(void); 1579 void t4_tracer_modunload(void); 1580 void t4_tracer_port_detach(struct adapter *); 1581 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1582 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1583 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1584 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1585 1586 /* t4_sched.c */ 1587 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1588 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1589 int t4_init_tx_sched(struct adapter *); 1590 int t4_free_tx_sched(struct adapter *); 1591 void t4_update_tx_sched(struct adapter *); 1592 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1593 void t4_release_cl_rl(struct adapter *, int, int); 1594 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1595 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1596 #ifdef RATELIMIT 1597 void t4_init_etid_table(struct adapter *); 1598 void t4_free_etid_table(struct adapter *); 1599 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1600 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1601 struct m_snd_tag **); 1602 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1603 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *); 1604 #endif 1605 1606 /* t4_filter.c */ 1607 int get_filter_mode(struct adapter *, uint32_t *); 1608 int set_filter_mode(struct adapter *, uint32_t); 1609 int set_filter_mask(struct adapter *, uint32_t); 1610 int get_filter(struct adapter *, struct t4_filter *); 1611 int set_filter(struct adapter *, struct t4_filter *); 1612 int del_filter(struct adapter *, struct t4_filter *); 1613 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1614 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1615 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1616 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1617 void free_hftid_hash(struct tid_info *); 1618 1619 /* t4_tpt.c */ 1620 #define T4_STAG_UNSET 0xffffffff 1621 #define T4_WRITE_MEM_DMA_LEN \ 1622 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_sgl), 16) 1623 #define T4_ULPTX_MIN_IO 32 1624 #define T4_MAX_INLINE_SIZE 96 1625 #define T4_WRITE_MEM_INLINE_LEN(len) \ 1626 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_idata) + \ 1627 roundup((len), T4_ULPTX_MIN_IO), 16) 1628 1629 uint32_t t4_pblpool_alloc(struct adapter *, int); 1630 void t4_pblpool_free(struct adapter *, uint32_t, int); 1631 uint32_t t4_stag_alloc(struct adapter *, int); 1632 void t4_stag_free(struct adapter *, uint32_t, int); 1633 void t4_init_tpt(struct adapter *); 1634 void t4_free_tpt(struct adapter *); 1635 void t4_write_mem_dma_wr(struct adapter *, void *, int, int, uint32_t, 1636 uint32_t, vm_paddr_t, uint64_t); 1637 void t4_write_mem_inline_wr(struct adapter *, void *, int, int, uint32_t, 1638 uint32_t, void *, uint64_t); 1639 1640 static inline struct wrqe * 1641 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1642 { 1643 int len = offsetof(struct wrqe, wr) + wr_len; 1644 struct wrqe *wr; 1645 1646 wr = malloc(len, M_CXGBE, M_NOWAIT); 1647 if (__predict_false(wr == NULL)) 1648 return (NULL); 1649 wr->wr_len = wr_len; 1650 wr->wrq = wrq; 1651 return (wr); 1652 } 1653 1654 static inline void * 1655 wrtod(struct wrqe *wr) 1656 { 1657 return (&wr->wr[0]); 1658 } 1659 1660 static inline void 1661 free_wrqe(struct wrqe *wr) 1662 { 1663 free(wr, M_CXGBE); 1664 } 1665 1666 static inline void 1667 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1668 { 1669 struct sge_wrq *wrq = wr->wrq; 1670 1671 TXQ_LOCK(wrq); 1672 if (__predict_true(wrq->eq.flags & EQ_HW_ALLOCATED)) 1673 t4_wrq_tx_locked(sc, wrq, wr); 1674 else 1675 free(wr, M_CXGBE); 1676 TXQ_UNLOCK(wrq); 1677 } 1678 1679 static inline int 1680 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1681 int len) 1682 { 1683 1684 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1685 } 1686 1687 static inline int 1688 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1689 const uint32_t *val, int len) 1690 { 1691 1692 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1693 } 1694 1695 /* Number of len16 -> number of descriptors */ 1696 static inline int 1697 tx_len16_to_desc(int len16) 1698 { 1699 1700 return (howmany(len16, EQ_ESIZE / 16)); 1701 } 1702 #endif 1703