1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_media.h> 58 #include <net/pfil.h> 59 #include <netinet/in.h> 60 #include <netinet/tcp_lro.h> 61 62 #include "offload.h" 63 #include "t4_ioctl.h" 64 #include "common/t4_msg.h" 65 #include "firmware/t4fw_interface.h" 66 67 #define KTR_CXGBE KTR_SPARE3 68 MALLOC_DECLARE(M_CXGBE); 69 #define CXGBE_UNIMPLEMENTED(s) \ 70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 71 72 /* 73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 74 * LIST_HEAD when building iw_cxgbe. 75 */ 76 #define CXGBE_LIST_HEAD(name, type) \ 77 struct name { \ 78 struct type *lh_first; /* first element */ \ 79 } 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 /* 1 << 4 is unused, was ADAP_SYSCTL_CTX */ 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 167 CXGBE_BUSY = (1 << 9), 168 HW_OFF_LIMITS = (1 << 10), /* off limits to all except reset_thread */ 169 170 /* port flags */ 171 HAS_TRACEQ = (1 << 3), 172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 173 174 /* VI flags */ 175 DOOMED = (1 << 0), 176 VI_INIT_DONE = (1 << 1), 177 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 178 TX_USES_VM_WR = (1 << 3), 179 VI_SKIP_STATS = (1 << 4), 180 181 /* adapter debug_flags */ 182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 187 }; 188 189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 194 195 struct vi_info { 196 device_t dev; 197 struct port_info *pi; 198 struct adapter *adapter; 199 200 struct ifnet *ifp; 201 struct pfil_head *pfil; 202 203 unsigned long flags; 204 int if_flags; 205 206 uint16_t *rss, *nm_rss; 207 uint16_t viid; /* opaque VI identifier */ 208 uint16_t smt_idx; 209 uint16_t vin; 210 uint8_t vfvld; 211 int16_t xact_addr_filt;/* index of exact MAC address filter */ 212 uint16_t rss_size; /* size of VI's RSS table slice */ 213 uint16_t rss_base; /* start of VI's RSS table slice */ 214 int hashen; 215 216 int nintr; 217 int first_intr; 218 219 /* These need to be int as they are used in sysctl */ 220 int ntxq; /* # of tx queues */ 221 int first_txq; /* index of first tx queue */ 222 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 223 int nrxq; /* # of rx queues */ 224 int first_rxq; /* index of first rx queue */ 225 int nofldtxq; /* # of offload tx queues */ 226 int first_ofld_txq; /* index of first offload tx queue */ 227 int nofldrxq; /* # of offload rx queues */ 228 int first_ofld_rxq; /* index of first offload rx queue */ 229 int nnmtxq; 230 int first_nm_txq; 231 int nnmrxq; 232 int first_nm_rxq; 233 int tmr_idx; 234 int ofld_tmr_idx; 235 int pktc_idx; 236 int ofld_pktc_idx; 237 int qsize_rxq; 238 int qsize_txq; 239 240 struct timeval last_refreshed; 241 struct fw_vi_stats_vf stats; 242 struct mtx tick_mtx; 243 struct callout tick; 244 245 struct sysctl_ctx_list ctx; 246 struct sysctl_oid *rxq_oid; 247 struct sysctl_oid *txq_oid; 248 struct sysctl_oid *nm_rxq_oid; 249 struct sysctl_oid *nm_txq_oid; 250 struct sysctl_oid *ofld_rxq_oid; 251 struct sysctl_oid *ofld_txq_oid; 252 253 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 254 }; 255 256 struct tx_ch_rl_params { 257 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 258 uint32_t maxrate; 259 }; 260 261 /* CLRL state */ 262 enum clrl_state { 263 CS_UNINITIALIZED = 0, 264 CS_PARAMS_SET, /* sw parameters have been set. */ 265 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 266 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 267 CS_HW_CONFIGURED /* configured in the hardware. */ 268 }; 269 270 /* CLRL flags */ 271 enum { 272 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 273 }; 274 275 struct tx_cl_rl_params { 276 enum clrl_state state; 277 int refcount; 278 uint8_t flags; 279 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 280 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 281 enum fw_sched_params_mode mode; /* aggr or per-flow */ 282 uint32_t maxrate; 283 uint16_t pktsize; 284 uint16_t burstsize; 285 }; 286 287 /* Tx scheduler parameters for a channel/port */ 288 struct tx_sched_params { 289 /* Channel Rate Limiter */ 290 struct tx_ch_rl_params ch_rl; 291 292 /* Class WRR */ 293 /* XXX */ 294 295 /* Class Rate Limiter (including the default pktsize and burstsize). */ 296 int pktsize; 297 int burstsize; 298 struct tx_cl_rl_params cl_rl[]; 299 }; 300 301 struct port_info { 302 device_t dev; 303 struct adapter *adapter; 304 305 struct vi_info *vi; 306 int nvi; 307 int up_vis; 308 int uld_vis; 309 bool vxlan_tcam_entry; 310 311 struct tx_sched_params *sched_params; 312 313 struct mtx pi_lock; 314 char lockname[16]; 315 unsigned long flags; 316 317 uint8_t lport; /* associated offload logical port */ 318 int8_t mdio_addr; 319 uint8_t port_type; 320 uint8_t mod_type; 321 uint8_t port_id; 322 uint8_t tx_chan; 323 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 324 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 325 uint8_t rx_c_chan; /* rx TP c-channel */ 326 327 struct link_config link_cfg; 328 struct ifmedia media; 329 330 struct port_stats stats; 331 u_int tnl_cong_drops; 332 u_int tx_parse_error; 333 int fcs_reg; 334 uint64_t fcs_base; 335 336 struct sysctl_ctx_list ctx; 337 }; 338 339 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 340 341 struct cluster_metadata { 342 uma_zone_t zone; 343 caddr_t cl; 344 u_int refcount; 345 }; 346 347 struct fl_sdesc { 348 caddr_t cl; 349 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 350 int16_t moff; /* offset of metadata from cl */ 351 uint8_t zidx; 352 }; 353 354 struct tx_desc { 355 __be64 flit[8]; 356 }; 357 358 struct tx_sdesc { 359 struct mbuf *m; /* m_nextpkt linked chain of frames */ 360 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 361 }; 362 363 364 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 365 struct iq_desc { 366 struct rss_header rss; 367 uint8_t cpl[IQ_PAD]; 368 struct rsp_ctrl rsp; 369 }; 370 #undef IQ_PAD 371 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 372 373 enum { 374 /* iq flags */ 375 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 376 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 377 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 378 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 379 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 380 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 381 382 /* iq state */ 383 IQS_DISABLED = 0, 384 IQS_BUSY = 1, 385 IQS_IDLE = 2, 386 387 /* netmap related flags */ 388 NM_OFF = 0, 389 NM_ON = 1, 390 NM_BUSY = 2, 391 }; 392 393 enum { 394 CPL_COOKIE_RESERVED = 0, 395 CPL_COOKIE_FILTER, 396 CPL_COOKIE_DDP0, 397 CPL_COOKIE_DDP1, 398 CPL_COOKIE_TOM, 399 CPL_COOKIE_HASHFILTER, 400 CPL_COOKIE_ETHOFLD, 401 CPL_COOKIE_KERN_TLS, 402 403 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 404 }; 405 406 struct sge_iq; 407 struct rss_header; 408 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 409 struct mbuf *); 410 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 411 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 412 413 /* 414 * Ingress Queue: T4 is producer, driver is consumer. 415 */ 416 struct sge_iq { 417 uint32_t flags; 418 volatile int state; 419 struct adapter *adapter; 420 struct iq_desc *desc; /* KVA of descriptor ring */ 421 int8_t intr_pktc_idx; /* packet count threshold index */ 422 uint8_t gen; /* generation bit */ 423 uint8_t intr_params; /* interrupt holdoff parameters */ 424 int8_t cong; /* congestion settings */ 425 uint16_t qsize; /* size (# of entries) of the queue */ 426 uint16_t sidx; /* index of the entry with the status page */ 427 uint16_t cidx; /* consumer index */ 428 uint16_t cntxt_id; /* SGE context id for the iq */ 429 uint16_t abs_id; /* absolute SGE id for the iq */ 430 int16_t intr_idx; /* interrupt used by the queue */ 431 432 STAILQ_ENTRY(sge_iq) link; 433 434 bus_dma_tag_t desc_tag; 435 bus_dmamap_t desc_map; 436 bus_addr_t ba; /* bus address of descriptor ring */ 437 }; 438 439 enum { 440 /* eq type */ 441 EQ_CTRL = 1, 442 EQ_ETH = 2, 443 EQ_OFLD = 3, 444 445 /* eq flags */ 446 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 447 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 448 EQ_ENABLED = (1 << 3), /* open for business */ 449 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 450 }; 451 452 /* Listed in order of preference. Update t4_sysctls too if you change these */ 453 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 454 455 /* 456 * Egress Queue: driver is producer, T4 is consumer. 457 * 458 * Note: A free list is an egress queue (driver produces the buffers and T4 459 * consumes them) but it's special enough to have its own struct (see sge_fl). 460 */ 461 struct sge_eq { 462 unsigned int flags; /* MUST be first */ 463 unsigned int cntxt_id; /* SGE context id for the eq */ 464 unsigned int abs_id; /* absolute SGE id for the eq */ 465 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 466 uint8_t doorbells; 467 uint8_t tx_chan; /* tx channel used by the eq */ 468 struct mtx eq_lock; 469 470 struct tx_desc *desc; /* KVA of descriptor ring */ 471 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 472 u_int udb_qid; /* relative qid within the doorbell page */ 473 uint16_t sidx; /* index of the entry with the status page */ 474 uint16_t cidx; /* consumer idx (desc idx) */ 475 uint16_t pidx; /* producer idx (desc idx) */ 476 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 477 uint16_t dbidx; /* pidx of the most recent doorbell */ 478 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 479 volatile u_int equiq; /* EQUIQ outstanding */ 480 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 481 482 bus_dma_tag_t desc_tag; 483 bus_dmamap_t desc_map; 484 bus_addr_t ba; /* bus address of descriptor ring */ 485 char lockname[16]; 486 }; 487 488 struct rx_buf_info { 489 uma_zone_t zone; /* zone that this cluster comes from */ 490 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 491 * hwsize[hwidx1] = size1. No spare. */ 492 uint16_t size2; /* hwsize[hwidx2] = size2. 493 * spare in cluster = size1 - size2. */ 494 int8_t hwidx1; /* SGE bufsize idx for size1 */ 495 int8_t hwidx2; /* SGE bufsize idx for size2 */ 496 uint8_t type; /* EXT_xxx type of the cluster */ 497 }; 498 499 enum { 500 NUM_MEMWIN = 3, 501 502 MEMWIN0_APERTURE = 2048, 503 MEMWIN0_BASE = 0x1b800, 504 505 MEMWIN1_APERTURE = 32768, 506 MEMWIN1_BASE = 0x28000, 507 508 MEMWIN2_APERTURE_T4 = 65536, 509 MEMWIN2_BASE_T4 = 0x30000, 510 511 MEMWIN2_APERTURE_T5 = 128 * 1024, 512 MEMWIN2_BASE_T5 = 0x60000, 513 }; 514 515 struct memwin { 516 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 517 uint32_t mw_base; /* constant after setup_memwin */ 518 uint32_t mw_aperture; /* ditto */ 519 uint32_t mw_curpos; /* protected by mw_lock */ 520 }; 521 522 enum { 523 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 524 FL_DOOMED = (1 << 1), /* about to be destroyed */ 525 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 526 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 527 }; 528 529 #define FL_RUNNING_LOW(fl) \ 530 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 531 #define FL_NOT_RUNNING_LOW(fl) \ 532 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 533 534 struct sge_fl { 535 struct mtx fl_lock; 536 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 537 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 538 uint16_t zidx; /* refill zone idx */ 539 uint16_t safe_zidx; 540 uint16_t lowat; /* # of buffers <= this means fl needs help */ 541 int flags; 542 uint16_t buf_boundary; 543 544 /* The 16b idx all deal with hw descriptors */ 545 uint16_t dbidx; /* hw pidx after last doorbell */ 546 uint16_t sidx; /* index of status page */ 547 volatile uint16_t hw_cidx; 548 549 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 550 uint32_t cidx; /* consumer index */ 551 uint32_t pidx; /* producer index */ 552 553 uint32_t dbval; 554 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 555 volatile uint32_t *udb; 556 557 uint64_t cl_allocated; /* # of clusters allocated */ 558 uint64_t cl_recycled; /* # of clusters recycled */ 559 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 560 561 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 562 struct mbuf *m0; 563 struct mbuf **pnext; 564 u_int remaining; 565 566 uint16_t qsize; /* # of hw descriptors (status page included) */ 567 uint16_t cntxt_id; /* SGE context id for the freelist */ 568 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 569 bus_dma_tag_t desc_tag; 570 bus_dmamap_t desc_map; 571 char lockname[16]; 572 bus_addr_t ba; /* bus address of descriptor ring */ 573 }; 574 575 struct mp_ring; 576 577 struct txpkts { 578 uint8_t wr_type; /* type 0 or type 1 */ 579 uint8_t npkt; /* # of packets in this work request */ 580 uint8_t len16; /* # of 16B pieces used by this work request */ 581 uint8_t score; 582 uint8_t max_npkt; /* maximum number of packets allowed */ 583 uint16_t plen; /* total payload (sum of all packets) */ 584 585 /* straight from fw_eth_tx_pkts_vm_wr. */ 586 __u8 ethmacdst[6]; 587 __u8 ethmacsrc[6]; 588 __be16 ethtype; 589 __be16 vlantci; 590 591 struct mbuf *mb[15]; 592 }; 593 594 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 595 struct sge_txq { 596 struct sge_eq eq; /* MUST be first */ 597 598 struct ifnet *ifp; /* the interface this txq belongs to */ 599 struct mp_ring *r; /* tx software ring */ 600 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 601 struct sglist *gl; 602 __be32 cpl_ctrl0; /* for convenience */ 603 int tc_idx; /* traffic class */ 604 uint64_t last_tx; /* cycle count when eth_tx was last called */ 605 struct txpkts txp; 606 607 struct task tx_reclaim_task; 608 /* stats for common events first */ 609 610 uint64_t txcsum; /* # of times hardware assisted with checksum */ 611 uint64_t tso_wrs; /* # of TSO work requests */ 612 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 613 uint64_t imm_wrs; /* # of work requests with immediate data */ 614 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 615 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 616 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 617 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 618 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 619 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 620 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 621 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 622 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 623 uint64_t vxlan_txcsum; 624 625 uint64_t kern_tls_records; 626 uint64_t kern_tls_short; 627 uint64_t kern_tls_partial; 628 uint64_t kern_tls_full; 629 uint64_t kern_tls_octets; 630 uint64_t kern_tls_waste; 631 uint64_t kern_tls_options; 632 uint64_t kern_tls_header; 633 uint64_t kern_tls_fin; 634 uint64_t kern_tls_fin_short; 635 uint64_t kern_tls_cbc; 636 uint64_t kern_tls_gcm; 637 638 /* stats for not-that-common events */ 639 640 /* Optional scratch space for constructing work requests. */ 641 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 642 } __aligned(CACHE_LINE_SIZE); 643 644 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 645 struct sge_rxq { 646 struct sge_iq iq; /* MUST be first */ 647 struct sge_fl fl; /* MUST follow iq */ 648 649 struct ifnet *ifp; /* the interface this rxq belongs to */ 650 struct lro_ctrl lro; /* LRO state */ 651 652 /* stats for common events first */ 653 654 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 655 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 656 uint64_t vxlan_rxcsum; 657 658 /* stats for not-that-common events */ 659 660 } __aligned(CACHE_LINE_SIZE); 661 662 static inline struct sge_rxq * 663 iq_to_rxq(struct sge_iq *iq) 664 { 665 666 return (__containerof(iq, struct sge_rxq, iq)); 667 } 668 669 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 670 struct sge_ofld_rxq { 671 struct sge_iq iq; /* MUST be first */ 672 struct sge_fl fl; /* MUST follow iq */ 673 counter_u64_t rx_iscsi_ddp_setup_ok; 674 counter_u64_t rx_iscsi_ddp_setup_error; 675 uint64_t rx_iscsi_ddp_pdus; 676 uint64_t rx_iscsi_ddp_octets; 677 uint64_t rx_iscsi_fl_pdus; 678 uint64_t rx_iscsi_fl_octets; 679 uint64_t rx_iscsi_padding_errors; 680 uint64_t rx_iscsi_header_digest_errors; 681 uint64_t rx_iscsi_data_digest_errors; 682 u_long rx_toe_tls_records; 683 u_long rx_toe_tls_octets; 684 } __aligned(CACHE_LINE_SIZE); 685 686 static inline struct sge_ofld_rxq * 687 iq_to_ofld_rxq(struct sge_iq *iq) 688 { 689 690 return (__containerof(iq, struct sge_ofld_rxq, iq)); 691 } 692 693 struct wrqe { 694 STAILQ_ENTRY(wrqe) link; 695 struct sge_wrq *wrq; 696 int wr_len; 697 char wr[] __aligned(16); 698 }; 699 700 struct wrq_cookie { 701 TAILQ_ENTRY(wrq_cookie) link; 702 int ndesc; 703 int pidx; 704 }; 705 706 /* 707 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 708 * are of this type. 709 */ 710 struct sge_wrq { 711 struct sge_eq eq; /* MUST be first */ 712 713 struct adapter *adapter; 714 struct task wrq_tx_task; 715 716 /* Tx desc reserved but WR not "committed" yet. */ 717 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 718 719 /* List of WRs ready to go out as soon as descriptors are available. */ 720 STAILQ_HEAD(, wrqe) wr_list; 721 u_int nwr_pending; 722 u_int ndesc_needed; 723 724 /* stats for common events first */ 725 726 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 727 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 728 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 729 730 /* stats for not-that-common events */ 731 732 /* 733 * Scratch space for work requests that wrap around after reaching the 734 * status page, and some information about the last WR that used it. 735 */ 736 uint16_t ss_pidx; 737 uint16_t ss_len; 738 uint8_t ss[SGE_MAX_WR_LEN]; 739 740 } __aligned(CACHE_LINE_SIZE); 741 742 /* ofld_txq: SGE egress queue + miscellaneous items */ 743 struct sge_ofld_txq { 744 struct sge_wrq wrq; 745 counter_u64_t tx_iscsi_pdus; 746 counter_u64_t tx_iscsi_octets; 747 counter_u64_t tx_iscsi_iso_wrs; 748 counter_u64_t tx_toe_tls_records; 749 counter_u64_t tx_toe_tls_octets; 750 } __aligned(CACHE_LINE_SIZE); 751 752 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 753 struct sge_nm_rxq { 754 /* Items used by the driver rx ithread are in this cacheline. */ 755 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 756 u_int nid; /* netmap ring # for this queue */ 757 struct vi_info *vi; 758 759 struct iq_desc *iq_desc; 760 uint16_t iq_abs_id; 761 uint16_t iq_cntxt_id; 762 uint16_t iq_cidx; 763 uint16_t iq_sidx; 764 uint8_t iq_gen; 765 uint32_t fl_sidx; 766 767 /* Items used by netmap rxsync are in this cacheline. */ 768 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 769 uint16_t fl_cntxt_id; 770 uint32_t fl_pidx; 771 uint32_t fl_sidx2; /* copy of fl_sidx */ 772 uint32_t fl_db_val; 773 u_int fl_db_saved; 774 u_int fl_db_threshold; /* in descriptors */ 775 u_int fl_hwidx:4; 776 777 /* 778 * fl_cidx is used by both the ithread and rxsync, the rest are not used 779 * in the rx fast path. 780 */ 781 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 782 783 bus_dma_tag_t iq_desc_tag; 784 bus_dmamap_t iq_desc_map; 785 bus_addr_t iq_ba; 786 int intr_idx; 787 788 bus_dma_tag_t fl_desc_tag; 789 bus_dmamap_t fl_desc_map; 790 bus_addr_t fl_ba; 791 }; 792 793 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 794 struct sge_nm_txq { 795 struct tx_desc *desc; 796 uint16_t cidx; 797 uint16_t pidx; 798 uint16_t sidx; 799 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 800 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 801 uint16_t dbidx; /* pidx of the most recent doorbell */ 802 uint8_t doorbells; 803 volatile uint32_t *udb; 804 u_int udb_qid; 805 u_int cntxt_id; 806 __be32 cpl_ctrl0; /* for convenience */ 807 __be32 op_pkd; /* ditto */ 808 u_int nid; /* netmap ring # for this queue */ 809 810 /* infrequently used items after this */ 811 812 bus_dma_tag_t desc_tag; 813 bus_dmamap_t desc_map; 814 bus_addr_t ba; 815 int iqidx; 816 } __aligned(CACHE_LINE_SIZE); 817 818 struct sge { 819 int nrxq; /* total # of Ethernet rx queues */ 820 int ntxq; /* total # of Ethernet tx queues */ 821 int nofldrxq; /* total # of TOE rx queues */ 822 int nofldtxq; /* total # of TOE tx queues */ 823 int nnmrxq; /* total # of netmap rx queues */ 824 int nnmtxq; /* total # of netmap tx queues */ 825 int niq; /* total # of ingress queues */ 826 int neq; /* total # of egress queues */ 827 828 struct sge_iq fwq; /* Firmware event queue */ 829 struct sge_wrq *ctrlq; /* Control queues */ 830 struct sge_txq *txq; /* NIC tx queues */ 831 struct sge_rxq *rxq; /* NIC rx queues */ 832 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 833 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 834 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 835 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 836 837 uint16_t iq_start; /* first cntxt_id */ 838 uint16_t iq_base; /* first abs_id */ 839 int eq_start; /* first cntxt_id */ 840 int eq_base; /* first abs_id */ 841 int iqmap_sz; 842 int eqmap_sz; 843 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 844 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 845 846 int8_t safe_zidx; 847 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 848 }; 849 850 struct devnames { 851 const char *nexus_name; 852 const char *ifnet_name; 853 const char *vi_ifnet_name; 854 const char *pf03_drv_name; 855 const char *vf_nexus_name; 856 const char *vf_ifnet_name; 857 }; 858 859 struct clip_entry; 860 861 struct adapter { 862 SLIST_ENTRY(adapter) link; 863 device_t dev; 864 struct cdev *cdev; 865 const struct devnames *names; 866 867 /* PCIe register resources */ 868 int regs_rid; 869 struct resource *regs_res; 870 int msix_rid; 871 struct resource *msix_res; 872 bus_space_handle_t bh; 873 bus_space_tag_t bt; 874 bus_size_t mmio_len; 875 int udbs_rid; 876 struct resource *udbs_res; 877 volatile uint8_t *udbs_base; 878 879 unsigned int pf; 880 unsigned int mbox; 881 unsigned int vpd_busy; 882 unsigned int vpd_flag; 883 884 /* Interrupt information */ 885 int intr_type; 886 int intr_count; 887 struct irq { 888 struct resource *res; 889 int rid; 890 void *tag; 891 struct sge_rxq *rxq; 892 struct sge_nm_rxq *nm_rxq; 893 } __aligned(CACHE_LINE_SIZE) *irq; 894 int sge_gts_reg; 895 int sge_kdoorbell_reg; 896 897 bus_dma_tag_t dmat; /* Parent DMA tag */ 898 899 struct sge sge; 900 int lro_timeout; 901 int sc_do_rxcopy; 902 903 int vxlan_port; 904 u_int vxlan_refcount; 905 int rawf_base; 906 int nrawf; 907 908 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 909 struct task async_event_task; 910 struct port_info *port[MAX_NPORTS]; 911 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 912 913 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 914 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 915 u_long clip_mask; 916 int clip_gen; 917 struct timeout_task clip_task; 918 919 void *tom_softc; /* (struct tom_data *) */ 920 struct tom_tunables tt; 921 struct t4_offload_policy *policy; 922 struct rwlock policy_lock; 923 924 void *iwarp_softc; /* (struct c4iw_dev *) */ 925 struct iw_tunables iwt; 926 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 927 void *ccr_softc; /* (struct ccr_softc *) */ 928 struct l2t_data *l2t; /* L2 table */ 929 struct smt_data *smt; /* Source MAC Table */ 930 struct tid_info tids; 931 vmem_t *key_map; 932 struct tls_tunables tlst; 933 934 uint8_t doorbells; 935 int offload_map; /* port_id's with IFCAP_TOE enabled */ 936 int bt_map; /* tx_chan's with BASE-T */ 937 int active_ulds; /* ULDs activated on this adapter */ 938 int flags; 939 int debug_flags; 940 941 char ifp_lockname[16]; 942 struct mtx ifp_lock; 943 struct ifnet *ifp; /* tracer ifp */ 944 struct ifmedia media; 945 int traceq; /* iq used by all tracers, -1 if none */ 946 int tracer_valid; /* bitmap of valid tracers */ 947 int tracer_enabled; /* bitmap of enabled tracers */ 948 949 char fw_version[16]; 950 char tp_version[16]; 951 char er_version[16]; 952 char bs_version[16]; 953 char cfg_file[32]; 954 u_int cfcsum; 955 struct adapter_params params; 956 const struct chip_params *chip_params; 957 struct t4_virt_res vres; 958 959 uint16_t nbmcaps; 960 uint16_t linkcaps; 961 uint16_t switchcaps; 962 uint16_t niccaps; 963 uint16_t toecaps; 964 uint16_t rdmacaps; 965 uint16_t cryptocaps; 966 uint16_t iscsicaps; 967 uint16_t fcoecaps; 968 969 struct sysctl_ctx_list ctx; 970 struct sysctl_oid *ctrlq_oid; 971 struct sysctl_oid *fwq_oid; 972 973 struct mtx sc_lock; 974 char lockname[16]; 975 976 /* Starving free lists */ 977 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 978 TAILQ_HEAD(, sge_fl) sfl; 979 struct callout sfl_callout; 980 981 /* 982 * Driver code that can run when the adapter is suspended must use this 983 * lock or a synchronized_op and check for HW_OFF_LIMITS before 984 * accessing hardware. 985 * 986 * XXX: could be changed to rwlock. wlock in suspend/resume and for 987 * indirect register access, rlock everywhere else. 988 */ 989 struct mtx reg_lock; 990 991 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 992 993 struct mtx tc_lock; 994 struct task tc_task; 995 996 struct task reset_task; 997 const void *reset_thread; 998 int num_resets; 999 int incarnation; 1000 1001 const char *last_op; 1002 const void *last_op_thr; 1003 int last_op_flags; 1004 1005 int swintr; 1006 int sensor_resets; 1007 1008 struct callout ktls_tick; 1009 }; 1010 1011 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1012 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1013 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1014 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1015 1016 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1017 KASSERT(IS_BUSY(sc) && \ 1018 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1019 ("%s: operation not synchronized.", __func__)) 1020 1021 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1022 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1023 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1024 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1025 1026 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1027 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1028 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1029 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1030 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1031 1032 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1033 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1034 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1035 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1036 1037 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1038 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1039 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1040 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1041 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1042 1043 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1044 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1045 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1046 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1047 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1048 1049 #define for_each_txq(vi, iter, q) \ 1050 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1051 iter < vi->ntxq; ++iter, ++q) 1052 #define for_each_rxq(vi, iter, q) \ 1053 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1054 iter < vi->nrxq; ++iter, ++q) 1055 #define for_each_ofld_txq(vi, iter, q) \ 1056 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1057 iter < vi->nofldtxq; ++iter, ++q) 1058 #define for_each_ofld_rxq(vi, iter, q) \ 1059 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1060 iter < vi->nofldrxq; ++iter, ++q) 1061 #define for_each_nm_txq(vi, iter, q) \ 1062 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1063 iter < vi->nnmtxq; ++iter, ++q) 1064 #define for_each_nm_rxq(vi, iter, q) \ 1065 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1066 iter < vi->nnmrxq; ++iter, ++q) 1067 #define for_each_vi(_pi, _iter, _vi) \ 1068 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1069 ++(_iter), ++(_vi)) 1070 1071 #define IDXINCR(idx, incr, wrap) do { \ 1072 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1073 } while (0) 1074 #define IDXDIFF(head, tail, wrap) \ 1075 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1076 1077 /* One for errors, one for firmware events */ 1078 #define T4_EXTRA_INTR 2 1079 1080 /* One for firmware events */ 1081 #define T4VF_EXTRA_INTR 1 1082 1083 static inline int 1084 forwarding_intr_to_fwq(struct adapter *sc) 1085 { 1086 1087 return (sc->intr_count == 1); 1088 } 1089 1090 /* Works reliably inside a sync_op or with reg_lock held. */ 1091 static inline bool 1092 hw_off_limits(struct adapter *sc) 1093 { 1094 return (__predict_false(sc->flags & HW_OFF_LIMITS)); 1095 } 1096 1097 static inline uint32_t 1098 t4_read_reg(struct adapter *sc, uint32_t reg) 1099 { 1100 if (hw_off_limits(sc)) 1101 MPASS(curthread == sc->reset_thread); 1102 return bus_space_read_4(sc->bt, sc->bh, reg); 1103 } 1104 1105 static inline void 1106 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1107 { 1108 if (hw_off_limits(sc)) 1109 MPASS(curthread == sc->reset_thread); 1110 bus_space_write_4(sc->bt, sc->bh, reg, val); 1111 } 1112 1113 static inline uint64_t 1114 t4_read_reg64(struct adapter *sc, uint32_t reg) 1115 { 1116 if (hw_off_limits(sc)) 1117 MPASS(curthread == sc->reset_thread); 1118 #ifdef __LP64__ 1119 return bus_space_read_8(sc->bt, sc->bh, reg); 1120 #else 1121 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1122 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1123 1124 #endif 1125 } 1126 1127 static inline void 1128 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1129 { 1130 if (hw_off_limits(sc)) 1131 MPASS(curthread == sc->reset_thread); 1132 #ifdef __LP64__ 1133 bus_space_write_8(sc->bt, sc->bh, reg, val); 1134 #else 1135 bus_space_write_4(sc->bt, sc->bh, reg, val); 1136 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1137 #endif 1138 } 1139 1140 static inline void 1141 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1142 { 1143 if (hw_off_limits(sc)) 1144 MPASS(curthread == sc->reset_thread); 1145 *val = pci_read_config(sc->dev, reg, 1); 1146 } 1147 1148 static inline void 1149 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1150 { 1151 if (hw_off_limits(sc)) 1152 MPASS(curthread == sc->reset_thread); 1153 pci_write_config(sc->dev, reg, val, 1); 1154 } 1155 1156 static inline void 1157 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1158 { 1159 1160 if (hw_off_limits(sc)) 1161 MPASS(curthread == sc->reset_thread); 1162 *val = pci_read_config(sc->dev, reg, 2); 1163 } 1164 1165 static inline void 1166 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1167 { 1168 if (hw_off_limits(sc)) 1169 MPASS(curthread == sc->reset_thread); 1170 pci_write_config(sc->dev, reg, val, 2); 1171 } 1172 1173 static inline void 1174 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1175 { 1176 if (hw_off_limits(sc)) 1177 MPASS(curthread == sc->reset_thread); 1178 *val = pci_read_config(sc->dev, reg, 4); 1179 } 1180 1181 static inline void 1182 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1183 { 1184 if (hw_off_limits(sc)) 1185 MPASS(curthread == sc->reset_thread); 1186 pci_write_config(sc->dev, reg, val, 4); 1187 } 1188 1189 static inline struct port_info * 1190 adap2pinfo(struct adapter *sc, int idx) 1191 { 1192 1193 return (sc->port[idx]); 1194 } 1195 1196 static inline void 1197 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1198 { 1199 1200 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1201 } 1202 1203 static inline int 1204 tx_resume_threshold(struct sge_eq *eq) 1205 { 1206 1207 /* not quite the same as qsize / 4, but this will do. */ 1208 return (eq->sidx / 4); 1209 } 1210 1211 static inline int 1212 t4_use_ldst(struct adapter *sc) 1213 { 1214 1215 #ifdef notyet 1216 return (sc->flags & FW_OK || !sc->use_bd); 1217 #else 1218 return (0); 1219 #endif 1220 } 1221 1222 static inline void 1223 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1224 const char *msg, const __be64 *const p, const bool err) 1225 { 1226 1227 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1228 return; 1229 if (p != NULL) { 1230 log(err ? LOG_ERR : LOG_DEBUG, 1231 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1232 "%016llx %016llx %016llx %016llx\n", 1233 device_get_nameunit(sc->dev), mbox, msg, 1234 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1235 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1236 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1237 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1238 } else { 1239 log(err ? LOG_ERR : LOG_DEBUG, 1240 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1241 "%016llx %016llx %016llx %016llx\n", 1242 device_get_nameunit(sc->dev), mbox, msg, 1243 (long long)t4_read_reg64(sc, reg), 1244 (long long)t4_read_reg64(sc, reg + 8), 1245 (long long)t4_read_reg64(sc, reg + 16), 1246 (long long)t4_read_reg64(sc, reg + 24), 1247 (long long)t4_read_reg64(sc, reg + 32), 1248 (long long)t4_read_reg64(sc, reg + 40), 1249 (long long)t4_read_reg64(sc, reg + 48), 1250 (long long)t4_read_reg64(sc, reg + 56)); 1251 } 1252 } 1253 1254 /* t4_main.c */ 1255 extern int t4_ntxq; 1256 extern int t4_nrxq; 1257 extern int t4_intr_types; 1258 extern int t4_tmr_idx; 1259 extern int t4_pktc_idx; 1260 extern unsigned int t4_qsize_rxq; 1261 extern unsigned int t4_qsize_txq; 1262 extern device_method_t cxgbe_methods[]; 1263 1264 int t4_os_find_pci_capability(struct adapter *, int); 1265 int t4_os_pci_save_state(struct adapter *); 1266 int t4_os_pci_restore_state(struct adapter *); 1267 void t4_os_portmod_changed(struct port_info *); 1268 void t4_os_link_changed(struct port_info *); 1269 void t4_iterate(void (*)(struct adapter *, void *), void *); 1270 void t4_init_devnames(struct adapter *); 1271 void t4_add_adapter(struct adapter *); 1272 int t4_detach_common(device_t); 1273 int t4_map_bars_0_and_4(struct adapter *); 1274 int t4_map_bar_2(struct adapter *); 1275 int t4_setup_intr_handlers(struct adapter *); 1276 void t4_sysctls(struct adapter *); 1277 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1278 void doom_vi(struct adapter *, struct vi_info *); 1279 void end_synchronized_op(struct adapter *, int); 1280 int update_mac_settings(struct ifnet *, int); 1281 int adapter_init(struct adapter *); 1282 int vi_init(struct vi_info *); 1283 void vi_sysctls(struct vi_info *); 1284 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1285 int alloc_atid(struct adapter *, void *); 1286 void *lookup_atid(struct adapter *, int); 1287 void free_atid(struct adapter *, int); 1288 void release_tid(struct adapter *, int, struct sge_wrq *); 1289 int cxgbe_media_change(struct ifnet *); 1290 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1291 bool t4_os_dump_cimla(struct adapter *, int, bool); 1292 void t4_os_dump_devlog(struct adapter *); 1293 1294 #ifdef KERN_TLS 1295 /* t4_kern_tls.c */ 1296 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1297 struct m_snd_tag **); 1298 void t6_ktls_modload(void); 1299 void t6_ktls_modunload(void); 1300 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1301 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1302 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1303 #endif 1304 1305 /* t4_keyctx.c */ 1306 struct auth_hash; 1307 union authctx; 1308 #ifdef KERN_TLS 1309 struct ktls_session; 1310 struct tls_key_req; 1311 struct tls_keyctx; 1312 #endif 1313 1314 void t4_aes_getdeckey(void *, const void *, unsigned int); 1315 void t4_copy_partial_hash(int, union authctx *, void *); 1316 void t4_init_gmac_hash(const char *, int, char *); 1317 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1318 char *); 1319 #ifdef KERN_TLS 1320 u_int t4_tls_key_info_size(const struct ktls_session *); 1321 int t4_tls_proto_ver(const struct ktls_session *); 1322 int t4_tls_cipher_mode(const struct ktls_session *); 1323 int t4_tls_auth_mode(const struct ktls_session *); 1324 int t4_tls_hmac_ctrl(const struct ktls_session *); 1325 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1326 int t4_alloc_tls_keyid(struct adapter *); 1327 void t4_free_tls_keyid(struct adapter *, int); 1328 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1329 struct tls_key_req *); 1330 #endif 1331 1332 #ifdef DEV_NETMAP 1333 /* t4_netmap.c */ 1334 struct sge_nm_rxq; 1335 void cxgbe_nm_attach(struct vi_info *); 1336 void cxgbe_nm_detach(struct vi_info *); 1337 void service_nm_rxq(struct sge_nm_rxq *); 1338 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1339 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1340 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1341 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1342 #endif 1343 1344 /* t4_sge.c */ 1345 void t4_sge_modload(void); 1346 void t4_sge_modunload(void); 1347 uint64_t t4_sge_extfree_refs(void); 1348 void t4_tweak_chip_settings(struct adapter *); 1349 int t4_verify_chip_settings(struct adapter *); 1350 void t4_init_rx_buf_info(struct adapter *); 1351 int t4_create_dma_tag(struct adapter *); 1352 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1353 struct sysctl_oid_list *); 1354 int t4_destroy_dma_tag(struct adapter *); 1355 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1356 bus_addr_t *, void **); 1357 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1358 void *); 1359 void free_fl_buffers(struct adapter *, struct sge_fl *); 1360 int t4_setup_adapter_queues(struct adapter *); 1361 int t4_teardown_adapter_queues(struct adapter *); 1362 int t4_setup_vi_queues(struct vi_info *); 1363 int t4_teardown_vi_queues(struct vi_info *); 1364 void t4_intr_all(void *); 1365 void t4_intr(void *); 1366 #ifdef DEV_NETMAP 1367 void t4_nm_intr(void *); 1368 void t4_vi_intr(void *); 1369 #endif 1370 void t4_intr_err(void *); 1371 void t4_intr_evt(void *); 1372 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1373 void t4_update_fl_bufsize(struct ifnet *); 1374 struct mbuf *alloc_wr_mbuf(int, int); 1375 int parse_pkt(struct mbuf **, bool); 1376 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1377 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1378 int tnl_cong(struct port_info *, int); 1379 void t4_register_an_handler(an_handler_t); 1380 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1381 void t4_register_cpl_handler(int, cpl_handler_t); 1382 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1383 #ifdef RATELIMIT 1384 int ethofld_transmit(struct ifnet *, struct mbuf *); 1385 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1386 #endif 1387 1388 /* t4_tracer.c */ 1389 struct t4_tracer; 1390 void t4_tracer_modload(void); 1391 void t4_tracer_modunload(void); 1392 void t4_tracer_port_detach(struct adapter *); 1393 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1394 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1395 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1396 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1397 1398 /* t4_sched.c */ 1399 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1400 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1401 int t4_init_tx_sched(struct adapter *); 1402 int t4_free_tx_sched(struct adapter *); 1403 void t4_update_tx_sched(struct adapter *); 1404 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1405 void t4_release_cl_rl(struct adapter *, int, int); 1406 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1407 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1408 #ifdef RATELIMIT 1409 void t4_init_etid_table(struct adapter *); 1410 void t4_free_etid_table(struct adapter *); 1411 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1412 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1413 struct m_snd_tag **); 1414 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1415 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1416 #endif 1417 1418 /* t4_filter.c */ 1419 int get_filter_mode(struct adapter *, uint32_t *); 1420 int set_filter_mode(struct adapter *, uint32_t); 1421 int set_filter_mask(struct adapter *, uint32_t); 1422 int get_filter(struct adapter *, struct t4_filter *); 1423 int set_filter(struct adapter *, struct t4_filter *); 1424 int del_filter(struct adapter *, struct t4_filter *); 1425 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1426 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1427 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1428 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1429 void free_hftid_hash(struct tid_info *); 1430 1431 static inline struct wrqe * 1432 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1433 { 1434 int len = offsetof(struct wrqe, wr) + wr_len; 1435 struct wrqe *wr; 1436 1437 wr = malloc(len, M_CXGBE, M_NOWAIT); 1438 if (__predict_false(wr == NULL)) 1439 return (NULL); 1440 wr->wr_len = wr_len; 1441 wr->wrq = wrq; 1442 return (wr); 1443 } 1444 1445 static inline void * 1446 wrtod(struct wrqe *wr) 1447 { 1448 return (&wr->wr[0]); 1449 } 1450 1451 static inline void 1452 free_wrqe(struct wrqe *wr) 1453 { 1454 free(wr, M_CXGBE); 1455 } 1456 1457 static inline void 1458 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1459 { 1460 struct sge_wrq *wrq = wr->wrq; 1461 1462 TXQ_LOCK(wrq); 1463 t4_wrq_tx_locked(sc, wrq, wr); 1464 TXQ_UNLOCK(wrq); 1465 } 1466 1467 static inline int 1468 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1469 int len) 1470 { 1471 1472 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1473 } 1474 1475 static inline int 1476 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1477 const uint32_t *val, int len) 1478 { 1479 1480 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1481 } 1482 1483 /* Number of len16 -> number of descriptors */ 1484 static inline int 1485 tx_len16_to_desc(int len16) 1486 { 1487 1488 return (howmany(len16, EQ_ESIZE / 16)); 1489 } 1490 #endif 1491