1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 #if defined(__i386__) || defined(__amd64__) 72 static __inline void 73 prefetch(void *x) 74 { 75 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 76 } 77 #else 78 #define prefetch(x) __builtin_prefetch(x) 79 #endif 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 ADAP_SYSCTL_CTX = (1 << 4), 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_OK = (1 << 8), 167 168 CXGBE_BUSY = (1 << 9), 169 170 /* port flags */ 171 HAS_TRACEQ = (1 << 3), 172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 173 174 /* VI flags */ 175 DOOMED = (1 << 0), 176 VI_INIT_DONE = (1 << 1), 177 VI_SYSCTL_CTX = (1 << 2), 178 TX_USES_VM_WR = (1 << 3), 179 180 /* adapter debug_flags */ 181 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 182 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 183 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 184 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 185 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 186 }; 187 188 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 189 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 190 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 191 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 192 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 193 194 struct vi_info { 195 device_t dev; 196 struct port_info *pi; 197 struct adapter *adapter; 198 199 struct ifnet *ifp; 200 struct pfil_head *pfil; 201 202 unsigned long flags; 203 int if_flags; 204 205 uint16_t *rss, *nm_rss; 206 uint16_t viid; /* opaque VI identifier */ 207 uint16_t smt_idx; 208 uint16_t vin; 209 uint8_t vfvld; 210 int16_t xact_addr_filt;/* index of exact MAC address filter */ 211 uint16_t rss_size; /* size of VI's RSS table slice */ 212 uint16_t rss_base; /* start of VI's RSS table slice */ 213 int hashen; 214 215 int nintr; 216 int first_intr; 217 218 /* These need to be int as they are used in sysctl */ 219 int ntxq; /* # of tx queues */ 220 int first_txq; /* index of first tx queue */ 221 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 222 int nrxq; /* # of rx queues */ 223 int first_rxq; /* index of first rx queue */ 224 int nofldtxq; /* # of offload tx queues */ 225 int first_ofld_txq; /* index of first offload tx queue */ 226 int nofldrxq; /* # of offload rx queues */ 227 int first_ofld_rxq; /* index of first offload rx queue */ 228 int nnmtxq; 229 int first_nm_txq; 230 int nnmrxq; 231 int first_nm_rxq; 232 int tmr_idx; 233 int ofld_tmr_idx; 234 int pktc_idx; 235 int ofld_pktc_idx; 236 int qsize_rxq; 237 int qsize_txq; 238 239 struct timeval last_refreshed; 240 struct fw_vi_stats_vf stats; 241 242 struct callout tick; 243 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 244 245 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 246 }; 247 248 struct tx_ch_rl_params { 249 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 250 uint32_t maxrate; 251 }; 252 253 enum { 254 CLRL_USER = (1 << 0), /* allocated manually. */ 255 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 256 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 257 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 258 }; 259 260 struct tx_cl_rl_params { 261 int refcount; 262 uint8_t flags; 263 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 264 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 265 enum fw_sched_params_mode mode; /* aggr or per-flow */ 266 uint32_t maxrate; 267 uint16_t pktsize; 268 uint16_t burstsize; 269 }; 270 271 /* Tx scheduler parameters for a channel/port */ 272 struct tx_sched_params { 273 /* Channel Rate Limiter */ 274 struct tx_ch_rl_params ch_rl; 275 276 /* Class WRR */ 277 /* XXX */ 278 279 /* Class Rate Limiter (including the default pktsize and burstsize). */ 280 int pktsize; 281 int burstsize; 282 struct tx_cl_rl_params cl_rl[]; 283 }; 284 285 struct port_info { 286 device_t dev; 287 struct adapter *adapter; 288 289 struct vi_info *vi; 290 int nvi; 291 int up_vis; 292 int uld_vis; 293 bool vxlan_tcam_entry; 294 295 struct tx_sched_params *sched_params; 296 297 struct mtx pi_lock; 298 char lockname[16]; 299 unsigned long flags; 300 301 uint8_t lport; /* associated offload logical port */ 302 int8_t mdio_addr; 303 uint8_t port_type; 304 uint8_t mod_type; 305 uint8_t port_id; 306 uint8_t tx_chan; 307 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 308 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 309 310 struct link_config link_cfg; 311 struct ifmedia media; 312 313 struct timeval last_refreshed; 314 struct port_stats stats; 315 u_int tnl_cong_drops; 316 u_int tx_parse_error; 317 u_long tx_toe_tls_records; 318 u_long tx_toe_tls_octets; 319 u_long rx_toe_tls_records; 320 u_long rx_toe_tls_octets; 321 322 struct callout tick; 323 }; 324 325 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 326 327 struct cluster_metadata { 328 uma_zone_t zone; 329 caddr_t cl; 330 u_int refcount; 331 }; 332 333 struct fl_sdesc { 334 caddr_t cl; 335 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 336 int16_t moff; /* offset of metadata from cl */ 337 uint8_t zidx; 338 }; 339 340 struct tx_desc { 341 __be64 flit[8]; 342 }; 343 344 struct tx_sdesc { 345 struct mbuf *m; /* m_nextpkt linked chain of frames */ 346 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 347 }; 348 349 350 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 351 struct iq_desc { 352 struct rss_header rss; 353 uint8_t cpl[IQ_PAD]; 354 struct rsp_ctrl rsp; 355 }; 356 #undef IQ_PAD 357 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 358 359 enum { 360 /* iq flags */ 361 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 362 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 363 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 364 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 365 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 366 367 /* iq state */ 368 IQS_DISABLED = 0, 369 IQS_BUSY = 1, 370 IQS_IDLE = 2, 371 372 /* netmap related flags */ 373 NM_OFF = 0, 374 NM_ON = 1, 375 NM_BUSY = 2, 376 }; 377 378 enum { 379 CPL_COOKIE_RESERVED = 0, 380 CPL_COOKIE_FILTER, 381 CPL_COOKIE_DDP0, 382 CPL_COOKIE_DDP1, 383 CPL_COOKIE_TOM, 384 CPL_COOKIE_HASHFILTER, 385 CPL_COOKIE_ETHOFLD, 386 CPL_COOKIE_KERN_TLS, 387 388 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 389 }; 390 391 struct sge_iq; 392 struct rss_header; 393 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 394 struct mbuf *); 395 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 396 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 397 398 /* 399 * Ingress Queue: T4 is producer, driver is consumer. 400 */ 401 struct sge_iq { 402 uint32_t flags; 403 volatile int state; 404 struct adapter *adapter; 405 struct iq_desc *desc; /* KVA of descriptor ring */ 406 int8_t intr_pktc_idx; /* packet count threshold index */ 407 uint8_t gen; /* generation bit */ 408 uint8_t intr_params; /* interrupt holdoff parameters */ 409 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 410 uint16_t qsize; /* size (# of entries) of the queue */ 411 uint16_t sidx; /* index of the entry with the status page */ 412 uint16_t cidx; /* consumer index */ 413 uint16_t cntxt_id; /* SGE context id for the iq */ 414 uint16_t abs_id; /* absolute SGE id for the iq */ 415 416 STAILQ_ENTRY(sge_iq) link; 417 418 bus_dma_tag_t desc_tag; 419 bus_dmamap_t desc_map; 420 bus_addr_t ba; /* bus address of descriptor ring */ 421 }; 422 423 enum { 424 EQ_CTRL = 1, 425 EQ_ETH = 2, 426 EQ_OFLD = 3, 427 428 /* eq flags */ 429 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 430 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 431 EQ_ENABLED = (1 << 3), /* open for business */ 432 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 433 }; 434 435 /* Listed in order of preference. Update t4_sysctls too if you change these */ 436 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 437 438 /* 439 * Egress Queue: driver is producer, T4 is consumer. 440 * 441 * Note: A free list is an egress queue (driver produces the buffers and T4 442 * consumes them) but it's special enough to have its own struct (see sge_fl). 443 */ 444 struct sge_eq { 445 unsigned int flags; /* MUST be first */ 446 unsigned int cntxt_id; /* SGE context id for the eq */ 447 unsigned int abs_id; /* absolute SGE id for the eq */ 448 struct mtx eq_lock; 449 450 struct tx_desc *desc; /* KVA of descriptor ring */ 451 uint8_t doorbells; 452 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 453 u_int udb_qid; /* relative qid within the doorbell page */ 454 uint16_t sidx; /* index of the entry with the status page */ 455 uint16_t cidx; /* consumer idx (desc idx) */ 456 uint16_t pidx; /* producer idx (desc idx) */ 457 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 458 uint16_t dbidx; /* pidx of the most recent doorbell */ 459 uint16_t iqid; /* iq that gets egr_update for the eq */ 460 uint8_t tx_chan; /* tx channel used by the eq */ 461 volatile u_int equiq; /* EQUIQ outstanding */ 462 463 bus_dma_tag_t desc_tag; 464 bus_dmamap_t desc_map; 465 bus_addr_t ba; /* bus address of descriptor ring */ 466 char lockname[16]; 467 }; 468 469 struct rx_buf_info { 470 uma_zone_t zone; /* zone that this cluster comes from */ 471 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 472 * hwsize[hwidx1] = size1. No spare. */ 473 uint16_t size2; /* hwsize[hwidx2] = size2. 474 * spare in cluster = size1 - size2. */ 475 int8_t hwidx1; /* SGE bufsize idx for size1 */ 476 int8_t hwidx2; /* SGE bufsize idx for size2 */ 477 uint8_t type; /* EXT_xxx type of the cluster */ 478 }; 479 480 enum { 481 NUM_MEMWIN = 3, 482 483 MEMWIN0_APERTURE = 2048, 484 MEMWIN0_BASE = 0x1b800, 485 486 MEMWIN1_APERTURE = 32768, 487 MEMWIN1_BASE = 0x28000, 488 489 MEMWIN2_APERTURE_T4 = 65536, 490 MEMWIN2_BASE_T4 = 0x30000, 491 492 MEMWIN2_APERTURE_T5 = 128 * 1024, 493 MEMWIN2_BASE_T5 = 0x60000, 494 }; 495 496 struct memwin { 497 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 498 uint32_t mw_base; /* constant after setup_memwin */ 499 uint32_t mw_aperture; /* ditto */ 500 uint32_t mw_curpos; /* protected by mw_lock */ 501 }; 502 503 enum { 504 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 505 FL_DOOMED = (1 << 1), /* about to be destroyed */ 506 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 507 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 508 }; 509 510 #define FL_RUNNING_LOW(fl) \ 511 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 512 #define FL_NOT_RUNNING_LOW(fl) \ 513 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 514 515 struct sge_fl { 516 struct mtx fl_lock; 517 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 518 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 519 uint16_t zidx; /* refill zone idx */ 520 uint16_t safe_zidx; 521 uint16_t lowat; /* # of buffers <= this means fl needs help */ 522 int flags; 523 uint16_t buf_boundary; 524 525 /* The 16b idx all deal with hw descriptors */ 526 uint16_t dbidx; /* hw pidx after last doorbell */ 527 uint16_t sidx; /* index of status page */ 528 volatile uint16_t hw_cidx; 529 530 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 531 uint32_t cidx; /* consumer index */ 532 uint32_t pidx; /* producer index */ 533 534 uint32_t dbval; 535 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 536 volatile uint32_t *udb; 537 538 uint64_t cl_allocated; /* # of clusters allocated */ 539 uint64_t cl_recycled; /* # of clusters recycled */ 540 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 541 542 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 543 struct mbuf *m0; 544 struct mbuf **pnext; 545 u_int remaining; 546 547 uint16_t qsize; /* # of hw descriptors (status page included) */ 548 uint16_t cntxt_id; /* SGE context id for the freelist */ 549 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 550 bus_dma_tag_t desc_tag; 551 bus_dmamap_t desc_map; 552 char lockname[16]; 553 bus_addr_t ba; /* bus address of descriptor ring */ 554 }; 555 556 struct mp_ring; 557 558 struct txpkts { 559 uint8_t wr_type; /* type 0 or type 1 */ 560 uint8_t npkt; /* # of packets in this work request */ 561 uint8_t len16; /* # of 16B pieces used by this work request */ 562 uint8_t score; /* 1-10. coalescing attempted if score > 3 */ 563 uint8_t max_npkt; /* maximum number of packets allowed */ 564 uint16_t plen; /* total payload (sum of all packets) */ 565 566 /* straight from fw_eth_tx_pkts_vm_wr. */ 567 __u8 ethmacdst[6]; 568 __u8 ethmacsrc[6]; 569 __be16 ethtype; 570 __be16 vlantci; 571 572 struct mbuf *mb[15]; 573 }; 574 575 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 576 struct sge_txq { 577 struct sge_eq eq; /* MUST be first */ 578 579 struct ifnet *ifp; /* the interface this txq belongs to */ 580 struct mp_ring *r; /* tx software ring */ 581 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 582 struct sglist *gl; 583 __be32 cpl_ctrl0; /* for convenience */ 584 int tc_idx; /* traffic class */ 585 struct txpkts txp; 586 587 struct task tx_reclaim_task; 588 /* stats for common events first */ 589 590 uint64_t txcsum; /* # of times hardware assisted with checksum */ 591 uint64_t tso_wrs; /* # of TSO work requests */ 592 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 593 uint64_t imm_wrs; /* # of work requests with immediate data */ 594 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 595 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 596 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 597 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 598 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 599 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 600 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 601 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 602 uint64_t vxlan_txcsum; 603 604 uint64_t kern_tls_records; 605 uint64_t kern_tls_short; 606 uint64_t kern_tls_partial; 607 uint64_t kern_tls_full; 608 uint64_t kern_tls_octets; 609 uint64_t kern_tls_waste; 610 uint64_t kern_tls_options; 611 uint64_t kern_tls_header; 612 uint64_t kern_tls_fin; 613 uint64_t kern_tls_fin_short; 614 uint64_t kern_tls_cbc; 615 uint64_t kern_tls_gcm; 616 617 /* stats for not-that-common events */ 618 619 /* Optional scratch space for constructing work requests. */ 620 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 621 } __aligned(CACHE_LINE_SIZE); 622 623 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 624 struct sge_rxq { 625 struct sge_iq iq; /* MUST be first */ 626 struct sge_fl fl; /* MUST follow iq */ 627 628 struct ifnet *ifp; /* the interface this rxq belongs to */ 629 struct lro_ctrl lro; /* LRO state */ 630 631 /* stats for common events first */ 632 633 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 634 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 635 uint64_t vxlan_rxcsum; 636 637 /* stats for not-that-common events */ 638 639 } __aligned(CACHE_LINE_SIZE); 640 641 static inline struct sge_rxq * 642 iq_to_rxq(struct sge_iq *iq) 643 { 644 645 return (__containerof(iq, struct sge_rxq, iq)); 646 } 647 648 649 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 650 struct sge_ofld_rxq { 651 struct sge_iq iq; /* MUST be first */ 652 struct sge_fl fl; /* MUST follow iq */ 653 } __aligned(CACHE_LINE_SIZE); 654 655 static inline struct sge_ofld_rxq * 656 iq_to_ofld_rxq(struct sge_iq *iq) 657 { 658 659 return (__containerof(iq, struct sge_ofld_rxq, iq)); 660 } 661 662 struct wrqe { 663 STAILQ_ENTRY(wrqe) link; 664 struct sge_wrq *wrq; 665 int wr_len; 666 char wr[] __aligned(16); 667 }; 668 669 struct wrq_cookie { 670 TAILQ_ENTRY(wrq_cookie) link; 671 int ndesc; 672 int pidx; 673 }; 674 675 /* 676 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 677 * and offload tx queues are of this type. 678 */ 679 struct sge_wrq { 680 struct sge_eq eq; /* MUST be first */ 681 682 struct adapter *adapter; 683 struct task wrq_tx_task; 684 685 /* Tx desc reserved but WR not "committed" yet. */ 686 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 687 688 /* List of WRs ready to go out as soon as descriptors are available. */ 689 STAILQ_HEAD(, wrqe) wr_list; 690 u_int nwr_pending; 691 u_int ndesc_needed; 692 693 /* stats for common events first */ 694 695 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 696 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 697 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 698 699 /* stats for not-that-common events */ 700 701 /* 702 * Scratch space for work requests that wrap around after reaching the 703 * status page, and some information about the last WR that used it. 704 */ 705 uint16_t ss_pidx; 706 uint16_t ss_len; 707 uint8_t ss[SGE_MAX_WR_LEN]; 708 709 } __aligned(CACHE_LINE_SIZE); 710 711 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 712 struct sge_nm_rxq { 713 /* Items used by the driver rx ithread are in this cacheline. */ 714 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 715 u_int nid; /* netmap ring # for this queue */ 716 struct vi_info *vi; 717 718 struct iq_desc *iq_desc; 719 uint16_t iq_abs_id; 720 uint16_t iq_cntxt_id; 721 uint16_t iq_cidx; 722 uint16_t iq_sidx; 723 uint8_t iq_gen; 724 uint32_t fl_sidx; 725 726 /* Items used by netmap rxsync are in this cacheline. */ 727 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 728 uint16_t fl_cntxt_id; 729 uint32_t fl_pidx; 730 uint32_t fl_sidx2; /* copy of fl_sidx */ 731 uint32_t fl_db_val; 732 u_int fl_db_saved; 733 u_int fl_db_threshold; /* in descriptors */ 734 u_int fl_hwidx:4; 735 736 /* 737 * fl_cidx is used by both the ithread and rxsync, the rest are not used 738 * in the rx fast path. 739 */ 740 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 741 742 bus_dma_tag_t iq_desc_tag; 743 bus_dmamap_t iq_desc_map; 744 bus_addr_t iq_ba; 745 int intr_idx; 746 747 bus_dma_tag_t fl_desc_tag; 748 bus_dmamap_t fl_desc_map; 749 bus_addr_t fl_ba; 750 }; 751 752 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 753 struct sge_nm_txq { 754 struct tx_desc *desc; 755 uint16_t cidx; 756 uint16_t pidx; 757 uint16_t sidx; 758 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 759 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 760 uint16_t dbidx; /* pidx of the most recent doorbell */ 761 uint8_t doorbells; 762 volatile uint32_t *udb; 763 u_int udb_qid; 764 u_int cntxt_id; 765 __be32 cpl_ctrl0; /* for convenience */ 766 __be32 op_pkd; /* ditto */ 767 u_int nid; /* netmap ring # for this queue */ 768 769 /* infrequently used items after this */ 770 771 bus_dma_tag_t desc_tag; 772 bus_dmamap_t desc_map; 773 bus_addr_t ba; 774 int iqidx; 775 } __aligned(CACHE_LINE_SIZE); 776 777 struct sge { 778 int nrxq; /* total # of Ethernet rx queues */ 779 int ntxq; /* total # of Ethernet tx queues */ 780 int nofldrxq; /* total # of TOE rx queues */ 781 int nofldtxq; /* total # of TOE tx queues */ 782 int nnmrxq; /* total # of netmap rx queues */ 783 int nnmtxq; /* total # of netmap tx queues */ 784 int niq; /* total # of ingress queues */ 785 int neq; /* total # of egress queues */ 786 787 struct sge_iq fwq; /* Firmware event queue */ 788 struct sge_wrq *ctrlq; /* Control queues */ 789 struct sge_txq *txq; /* NIC tx queues */ 790 struct sge_rxq *rxq; /* NIC rx queues */ 791 struct sge_wrq *ofld_txq; /* TOE tx queues */ 792 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 793 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 794 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 795 796 uint16_t iq_start; /* first cntxt_id */ 797 uint16_t iq_base; /* first abs_id */ 798 int eq_start; /* first cntxt_id */ 799 int eq_base; /* first abs_id */ 800 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 801 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 802 803 int8_t safe_zidx; 804 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 805 }; 806 807 struct devnames { 808 const char *nexus_name; 809 const char *ifnet_name; 810 const char *vi_ifnet_name; 811 const char *pf03_drv_name; 812 const char *vf_nexus_name; 813 const char *vf_ifnet_name; 814 }; 815 816 struct clip_entry; 817 818 struct adapter { 819 SLIST_ENTRY(adapter) link; 820 device_t dev; 821 struct cdev *cdev; 822 const struct devnames *names; 823 824 /* PCIe register resources */ 825 int regs_rid; 826 struct resource *regs_res; 827 int msix_rid; 828 struct resource *msix_res; 829 bus_space_handle_t bh; 830 bus_space_tag_t bt; 831 bus_size_t mmio_len; 832 int udbs_rid; 833 struct resource *udbs_res; 834 volatile uint8_t *udbs_base; 835 836 unsigned int pf; 837 unsigned int mbox; 838 unsigned int vpd_busy; 839 unsigned int vpd_flag; 840 841 /* Interrupt information */ 842 int intr_type; 843 int intr_count; 844 struct irq { 845 struct resource *res; 846 int rid; 847 void *tag; 848 struct sge_rxq *rxq; 849 struct sge_nm_rxq *nm_rxq; 850 } __aligned(CACHE_LINE_SIZE) *irq; 851 int sge_gts_reg; 852 int sge_kdoorbell_reg; 853 854 bus_dma_tag_t dmat; /* Parent DMA tag */ 855 856 struct sge sge; 857 int lro_timeout; 858 int sc_do_rxcopy; 859 860 int vxlan_port; 861 u_int vxlan_refcount; 862 int rawf_base; 863 int nrawf; 864 865 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 866 struct task async_event_task; 867 struct port_info *port[MAX_NPORTS]; 868 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 869 870 struct mtx clip_table_lock; 871 TAILQ_HEAD(, clip_entry) clip_table; 872 int clip_gen; 873 874 void *tom_softc; /* (struct tom_data *) */ 875 struct tom_tunables tt; 876 struct t4_offload_policy *policy; 877 struct rwlock policy_lock; 878 879 void *iwarp_softc; /* (struct c4iw_dev *) */ 880 struct iw_tunables iwt; 881 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 882 void *ccr_softc; /* (struct ccr_softc *) */ 883 struct l2t_data *l2t; /* L2 table */ 884 struct smt_data *smt; /* Source MAC Table */ 885 struct tid_info tids; 886 vmem_t *key_map; 887 struct tls_tunables tlst; 888 889 uint8_t doorbells; 890 int offload_map; /* ports with IFCAP_TOE enabled */ 891 int active_ulds; /* ULDs activated on this adapter */ 892 int flags; 893 int debug_flags; 894 895 char ifp_lockname[16]; 896 struct mtx ifp_lock; 897 struct ifnet *ifp; /* tracer ifp */ 898 struct ifmedia media; 899 int traceq; /* iq used by all tracers, -1 if none */ 900 int tracer_valid; /* bitmap of valid tracers */ 901 int tracer_enabled; /* bitmap of enabled tracers */ 902 903 char fw_version[16]; 904 char tp_version[16]; 905 char er_version[16]; 906 char bs_version[16]; 907 char cfg_file[32]; 908 u_int cfcsum; 909 struct adapter_params params; 910 const struct chip_params *chip_params; 911 struct t4_virt_res vres; 912 913 uint16_t nbmcaps; 914 uint16_t linkcaps; 915 uint16_t switchcaps; 916 uint16_t niccaps; 917 uint16_t toecaps; 918 uint16_t rdmacaps; 919 uint16_t cryptocaps; 920 uint16_t iscsicaps; 921 uint16_t fcoecaps; 922 923 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 924 925 struct mtx sc_lock; 926 char lockname[16]; 927 928 /* Starving free lists */ 929 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 930 TAILQ_HEAD(, sge_fl) sfl; 931 struct callout sfl_callout; 932 933 struct mtx reg_lock; /* for indirect register access */ 934 935 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 936 937 struct mtx tc_lock; 938 struct task tc_task; 939 940 const char *last_op; 941 const void *last_op_thr; 942 int last_op_flags; 943 944 int swintr; 945 int sensor_resets; 946 947 struct callout ktls_tick; 948 }; 949 950 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 951 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 952 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 953 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 954 955 #define ASSERT_SYNCHRONIZED_OP(sc) \ 956 KASSERT(IS_BUSY(sc) && \ 957 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 958 ("%s: operation not synchronized.", __func__)) 959 960 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 961 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 962 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 963 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 964 965 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 966 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 967 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 968 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 969 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 970 971 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 972 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 973 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 974 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 975 976 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 977 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 978 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 979 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 980 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 981 982 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 983 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 984 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 985 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 986 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 987 988 #define for_each_txq(vi, iter, q) \ 989 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 990 iter < vi->ntxq; ++iter, ++q) 991 #define for_each_rxq(vi, iter, q) \ 992 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 993 iter < vi->nrxq; ++iter, ++q) 994 #define for_each_ofld_txq(vi, iter, q) \ 995 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 996 iter < vi->nofldtxq; ++iter, ++q) 997 #define for_each_ofld_rxq(vi, iter, q) \ 998 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 999 iter < vi->nofldrxq; ++iter, ++q) 1000 #define for_each_nm_txq(vi, iter, q) \ 1001 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1002 iter < vi->nnmtxq; ++iter, ++q) 1003 #define for_each_nm_rxq(vi, iter, q) \ 1004 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1005 iter < vi->nnmrxq; ++iter, ++q) 1006 #define for_each_vi(_pi, _iter, _vi) \ 1007 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1008 ++(_iter), ++(_vi)) 1009 1010 #define IDXINCR(idx, incr, wrap) do { \ 1011 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1012 } while (0) 1013 #define IDXDIFF(head, tail, wrap) \ 1014 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1015 1016 /* One for errors, one for firmware events */ 1017 #define T4_EXTRA_INTR 2 1018 1019 /* One for firmware events */ 1020 #define T4VF_EXTRA_INTR 1 1021 1022 static inline int 1023 forwarding_intr_to_fwq(struct adapter *sc) 1024 { 1025 1026 return (sc->intr_count == 1); 1027 } 1028 1029 static inline uint32_t 1030 t4_read_reg(struct adapter *sc, uint32_t reg) 1031 { 1032 1033 return bus_space_read_4(sc->bt, sc->bh, reg); 1034 } 1035 1036 static inline void 1037 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1038 { 1039 1040 bus_space_write_4(sc->bt, sc->bh, reg, val); 1041 } 1042 1043 static inline uint64_t 1044 t4_read_reg64(struct adapter *sc, uint32_t reg) 1045 { 1046 1047 #ifdef __LP64__ 1048 return bus_space_read_8(sc->bt, sc->bh, reg); 1049 #else 1050 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1051 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1052 1053 #endif 1054 } 1055 1056 static inline void 1057 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1058 { 1059 1060 #ifdef __LP64__ 1061 bus_space_write_8(sc->bt, sc->bh, reg, val); 1062 #else 1063 bus_space_write_4(sc->bt, sc->bh, reg, val); 1064 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1065 #endif 1066 } 1067 1068 static inline void 1069 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1070 { 1071 1072 *val = pci_read_config(sc->dev, reg, 1); 1073 } 1074 1075 static inline void 1076 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1077 { 1078 1079 pci_write_config(sc->dev, reg, val, 1); 1080 } 1081 1082 static inline void 1083 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1084 { 1085 1086 *val = pci_read_config(sc->dev, reg, 2); 1087 } 1088 1089 static inline void 1090 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1091 { 1092 1093 pci_write_config(sc->dev, reg, val, 2); 1094 } 1095 1096 static inline void 1097 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1098 { 1099 1100 *val = pci_read_config(sc->dev, reg, 4); 1101 } 1102 1103 static inline void 1104 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1105 { 1106 1107 pci_write_config(sc->dev, reg, val, 4); 1108 } 1109 1110 static inline struct port_info * 1111 adap2pinfo(struct adapter *sc, int idx) 1112 { 1113 1114 return (sc->port[idx]); 1115 } 1116 1117 static inline void 1118 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1119 { 1120 1121 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1122 } 1123 1124 static inline int 1125 tx_resume_threshold(struct sge_eq *eq) 1126 { 1127 1128 /* not quite the same as qsize / 4, but this will do. */ 1129 return (eq->sidx / 4); 1130 } 1131 1132 static inline int 1133 t4_use_ldst(struct adapter *sc) 1134 { 1135 1136 #ifdef notyet 1137 return (sc->flags & FW_OK || !sc->use_bd); 1138 #else 1139 return (0); 1140 #endif 1141 } 1142 1143 static inline void 1144 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1145 const char *msg, const __be64 *const p, const bool err) 1146 { 1147 1148 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1149 return; 1150 if (p != NULL) { 1151 log(err ? LOG_ERR : LOG_DEBUG, 1152 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1153 "%016llx %016llx %016llx %016llx\n", 1154 device_get_nameunit(sc->dev), mbox, msg, 1155 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1156 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1157 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1158 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1159 } else { 1160 log(err ? LOG_ERR : LOG_DEBUG, 1161 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1162 "%016llx %016llx %016llx %016llx\n", 1163 device_get_nameunit(sc->dev), mbox, msg, 1164 (long long)t4_read_reg64(sc, reg), 1165 (long long)t4_read_reg64(sc, reg + 8), 1166 (long long)t4_read_reg64(sc, reg + 16), 1167 (long long)t4_read_reg64(sc, reg + 24), 1168 (long long)t4_read_reg64(sc, reg + 32), 1169 (long long)t4_read_reg64(sc, reg + 40), 1170 (long long)t4_read_reg64(sc, reg + 48), 1171 (long long)t4_read_reg64(sc, reg + 56)); 1172 } 1173 } 1174 1175 /* t4_main.c */ 1176 extern int t4_ntxq; 1177 extern int t4_nrxq; 1178 extern int t4_intr_types; 1179 extern int t4_tmr_idx; 1180 extern int t4_pktc_idx; 1181 extern unsigned int t4_qsize_rxq; 1182 extern unsigned int t4_qsize_txq; 1183 extern device_method_t cxgbe_methods[]; 1184 1185 int t4_os_find_pci_capability(struct adapter *, int); 1186 int t4_os_pci_save_state(struct adapter *); 1187 int t4_os_pci_restore_state(struct adapter *); 1188 void t4_os_portmod_changed(struct port_info *); 1189 void t4_os_link_changed(struct port_info *); 1190 void t4_iterate(void (*)(struct adapter *, void *), void *); 1191 void t4_init_devnames(struct adapter *); 1192 void t4_add_adapter(struct adapter *); 1193 int t4_detach_common(device_t); 1194 int t4_map_bars_0_and_4(struct adapter *); 1195 int t4_map_bar_2(struct adapter *); 1196 int t4_setup_intr_handlers(struct adapter *); 1197 void t4_sysctls(struct adapter *); 1198 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1199 void doom_vi(struct adapter *, struct vi_info *); 1200 void end_synchronized_op(struct adapter *, int); 1201 int update_mac_settings(struct ifnet *, int); 1202 int adapter_full_init(struct adapter *); 1203 int adapter_full_uninit(struct adapter *); 1204 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1205 void cxgbe_snd_tag_init(struct cxgbe_snd_tag *, struct ifnet *, int); 1206 int vi_full_init(struct vi_info *); 1207 int vi_full_uninit(struct vi_info *); 1208 void vi_sysctls(struct vi_info *); 1209 void vi_tick(void *); 1210 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1211 int alloc_atid(struct adapter *, void *); 1212 void *lookup_atid(struct adapter *, int); 1213 void free_atid(struct adapter *, int); 1214 void release_tid(struct adapter *, int, struct sge_wrq *); 1215 int cxgbe_media_change(struct ifnet *); 1216 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1217 bool t4_os_dump_cimla(struct adapter *, int, bool); 1218 void t4_os_dump_devlog(struct adapter *); 1219 1220 #ifdef KERN_TLS 1221 /* t4_kern_tls.c */ 1222 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1223 struct m_snd_tag **); 1224 void cxgbe_tls_tag_free(struct m_snd_tag *); 1225 void t6_ktls_modload(void); 1226 void t6_ktls_modunload(void); 1227 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1228 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1229 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1230 #endif 1231 1232 /* t4_keyctx.c */ 1233 struct auth_hash; 1234 union authctx; 1235 1236 void t4_aes_getdeckey(void *, const void *, unsigned int); 1237 void t4_copy_partial_hash(int, union authctx *, void *); 1238 void t4_init_gmac_hash(const char *, int, char *); 1239 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *); 1240 1241 #ifdef DEV_NETMAP 1242 /* t4_netmap.c */ 1243 struct sge_nm_rxq; 1244 void cxgbe_nm_attach(struct vi_info *); 1245 void cxgbe_nm_detach(struct vi_info *); 1246 void service_nm_rxq(struct sge_nm_rxq *); 1247 #endif 1248 1249 /* t4_sge.c */ 1250 void t4_sge_modload(void); 1251 void t4_sge_modunload(void); 1252 uint64_t t4_sge_extfree_refs(void); 1253 void t4_tweak_chip_settings(struct adapter *); 1254 int t4_read_chip_settings(struct adapter *); 1255 int t4_create_dma_tag(struct adapter *); 1256 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1257 struct sysctl_oid_list *); 1258 int t4_destroy_dma_tag(struct adapter *); 1259 int t4_setup_adapter_queues(struct adapter *); 1260 int t4_teardown_adapter_queues(struct adapter *); 1261 int t4_setup_vi_queues(struct vi_info *); 1262 int t4_teardown_vi_queues(struct vi_info *); 1263 void t4_intr_all(void *); 1264 void t4_intr(void *); 1265 #ifdef DEV_NETMAP 1266 void t4_nm_intr(void *); 1267 void t4_vi_intr(void *); 1268 #endif 1269 void t4_intr_err(void *); 1270 void t4_intr_evt(void *); 1271 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1272 void t4_update_fl_bufsize(struct ifnet *); 1273 struct mbuf *alloc_wr_mbuf(int, int); 1274 int parse_pkt(struct mbuf **, bool); 1275 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1276 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1277 int tnl_cong(struct port_info *, int); 1278 void t4_register_an_handler(an_handler_t); 1279 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1280 void t4_register_cpl_handler(int, cpl_handler_t); 1281 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1282 #ifdef RATELIMIT 1283 int ethofld_transmit(struct ifnet *, struct mbuf *); 1284 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1285 #endif 1286 1287 /* t4_tracer.c */ 1288 struct t4_tracer; 1289 void t4_tracer_modload(void); 1290 void t4_tracer_modunload(void); 1291 void t4_tracer_port_detach(struct adapter *); 1292 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1293 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1294 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1295 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1296 1297 /* t4_sched.c */ 1298 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1299 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1300 int t4_init_tx_sched(struct adapter *); 1301 int t4_free_tx_sched(struct adapter *); 1302 void t4_update_tx_sched(struct adapter *); 1303 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1304 void t4_release_cl_rl(struct adapter *, int, int); 1305 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1306 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1307 #ifdef RATELIMIT 1308 void t4_init_etid_table(struct adapter *); 1309 void t4_free_etid_table(struct adapter *); 1310 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1311 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1312 struct m_snd_tag **); 1313 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1314 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1315 void cxgbe_rate_tag_free(struct m_snd_tag *); 1316 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1317 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1318 #endif 1319 1320 /* t4_filter.c */ 1321 int get_filter_mode(struct adapter *, uint32_t *); 1322 int set_filter_mode(struct adapter *, uint32_t); 1323 int get_filter(struct adapter *, struct t4_filter *); 1324 int set_filter(struct adapter *, struct t4_filter *); 1325 int del_filter(struct adapter *, struct t4_filter *); 1326 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1327 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1328 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1329 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1330 void free_hftid_hash(struct tid_info *); 1331 1332 static inline struct wrqe * 1333 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1334 { 1335 int len = offsetof(struct wrqe, wr) + wr_len; 1336 struct wrqe *wr; 1337 1338 wr = malloc(len, M_CXGBE, M_NOWAIT); 1339 if (__predict_false(wr == NULL)) 1340 return (NULL); 1341 wr->wr_len = wr_len; 1342 wr->wrq = wrq; 1343 return (wr); 1344 } 1345 1346 static inline void * 1347 wrtod(struct wrqe *wr) 1348 { 1349 return (&wr->wr[0]); 1350 } 1351 1352 static inline void 1353 free_wrqe(struct wrqe *wr) 1354 { 1355 free(wr, M_CXGBE); 1356 } 1357 1358 static inline void 1359 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1360 { 1361 struct sge_wrq *wrq = wr->wrq; 1362 1363 TXQ_LOCK(wrq); 1364 t4_wrq_tx_locked(sc, wrq, wr); 1365 TXQ_UNLOCK(wrq); 1366 } 1367 1368 static inline int 1369 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1370 int len) 1371 { 1372 1373 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1374 } 1375 1376 static inline int 1377 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1378 const uint32_t *val, int len) 1379 { 1380 1381 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1382 } 1383 1384 /* Number of len16 -> number of descriptors */ 1385 static inline int 1386 tx_len16_to_desc(int len16) 1387 { 1388 1389 return (howmany(len16, EQ_ESIZE / 16)); 1390 } 1391 #endif 1392