1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/in.h> 48 #include <netinet/tcp_lro.h> 49 50 #include "offload.h" 51 #include "firmware/t4fw_interface.h" 52 53 #define T4_CFGNAME "t4fw_cfg" 54 #define T4_FWNAME "t4fw" 55 56 MALLOC_DECLARE(M_CXGBE); 57 #define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60 #if defined(__i386__) || defined(__amd64__) 61 static __inline void 62 prefetch(void *x) 63 { 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65 } 66 #else 67 #define prefetch(x) 68 #endif 69 70 #ifndef SYSCTL_ADD_UQUAD 71 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72 #define sysctl_handle_64 sysctl_handle_quad 73 #define CTLTYPE_U64 CTLTYPE_QUAD 74 #endif 75 76 #if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78 #define SBUF_DRAIN 1 79 #endif 80 81 #ifdef __amd64__ 82 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 83 static __inline uint64_t 84 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 85 bus_size_t offset) 86 { 87 KASSERT(tag == X86_BUS_SPACE_MEM, 88 ("%s: can only handle mem space", __func__)); 89 90 return (*(volatile uint64_t *)(handle + offset)); 91 } 92 93 static __inline void 94 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 95 bus_size_t offset, uint64_t value) 96 { 97 KASSERT(tag == X86_BUS_SPACE_MEM, 98 ("%s: can only handle mem space", __func__)); 99 100 *(volatile uint64_t *)(bsh + offset) = value; 101 } 102 #else 103 static __inline uint64_t 104 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 105 bus_size_t offset) 106 { 107 return (uint64_t)bus_space_read_4(tag, handle, offset) + 108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 109 } 110 111 static __inline void 112 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 113 bus_size_t offset, uint64_t value) 114 { 115 bus_space_write_4(tag, bsh, offset, value); 116 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 117 } 118 #endif 119 120 struct adapter; 121 typedef struct adapter adapter_t; 122 123 enum { 124 FW_IQ_QSIZE = 256, 125 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 126 127 RX_IQ_QSIZE = 1024, 128 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 129 130 EQ_ESIZE = 64, /* All egress queues use this entry size */ 131 132 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 133 #if MJUMPAGESIZE != MCLBYTES 134 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 135 #else 136 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 137 #endif 138 OFLD_BUF_SIZE = MJUM16BYTES, /* size of fl buffer for TOE rxq */ 139 140 CTRL_EQ_QSIZE = 128, 141 142 TX_EQ_QSIZE = 1024, 143 TX_SGL_SEGS = 36, 144 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 145 }; 146 147 #ifdef T4_PKT_TIMESTAMP 148 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 149 #else 150 #define RX_COPY_THRESHOLD MINCLSIZE 151 #endif 152 153 enum { 154 /* adapter intr_type */ 155 INTR_INTX = (1 << 0), 156 INTR_MSI = (1 << 1), 157 INTR_MSIX = (1 << 2) 158 }; 159 160 enum { 161 /* flags understood by begin_synchronized_op */ 162 HOLD_LOCK = (1 << 0), 163 SLEEP_OK = (1 << 1), 164 INTR_OK = (1 << 2), 165 166 /* flags understood by end_synchronized_op */ 167 LOCK_HELD = HOLD_LOCK, 168 }; 169 170 enum { 171 /* adapter flags */ 172 FULL_INIT_DONE = (1 << 0), 173 FW_OK = (1 << 1), 174 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 175 MASTER_PF = (1 << 3), 176 ADAP_SYSCTL_CTX = (1 << 4), 177 TOM_INIT_DONE = (1 << 5), 178 179 CXGBE_BUSY = (1 << 9), 180 181 /* port flags */ 182 DOOMED = (1 << 0), 183 PORT_INIT_DONE = (1 << 1), 184 PORT_SYSCTL_CTX = (1 << 2), 185 }; 186 187 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 188 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 189 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 190 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 191 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 192 193 struct port_info { 194 device_t dev; 195 struct adapter *adapter; 196 197 struct ifnet *ifp; 198 struct ifmedia media; 199 200 struct mtx pi_lock; 201 char lockname[16]; 202 unsigned long flags; 203 int if_flags; 204 205 uint16_t viid; 206 int16_t xact_addr_filt;/* index of exact MAC address filter */ 207 uint16_t rss_size; /* size of VI's RSS table slice */ 208 uint8_t lport; /* associated offload logical port */ 209 int8_t mdio_addr; 210 uint8_t port_type; 211 uint8_t mod_type; 212 uint8_t port_id; 213 uint8_t tx_chan; 214 215 /* These need to be int as they are used in sysctl */ 216 int ntxq; /* # of tx queues */ 217 int first_txq; /* index of first tx queue */ 218 int nrxq; /* # of rx queues */ 219 int first_rxq; /* index of first rx queue */ 220 #ifdef TCP_OFFLOAD 221 int nofldtxq; /* # of offload tx queues */ 222 int first_ofld_txq; /* index of first offload tx queue */ 223 int nofldrxq; /* # of offload rx queues */ 224 int first_ofld_rxq; /* index of first offload rx queue */ 225 #endif 226 int tmr_idx; 227 int pktc_idx; 228 int qsize_rxq; 229 int qsize_txq; 230 231 struct link_config link_cfg; 232 struct port_stats stats; 233 234 eventhandler_tag vlan_c; 235 236 struct callout tick; 237 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 238 239 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 240 }; 241 242 struct fl_sdesc { 243 struct mbuf *m; 244 bus_dmamap_t map; 245 caddr_t cl; 246 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 247 #ifdef INVARIANTS 248 __be64 ba_tag; 249 #endif 250 }; 251 252 struct tx_desc { 253 __be64 flit[8]; 254 }; 255 256 struct tx_map { 257 struct mbuf *m; 258 bus_dmamap_t map; 259 }; 260 261 /* DMA maps used for tx */ 262 struct tx_maps { 263 struct tx_map *maps; 264 uint32_t map_total; /* # of DMA maps */ 265 uint32_t map_pidx; /* next map to be used */ 266 uint32_t map_cidx; /* reclaimed up to this index */ 267 uint32_t map_avail; /* # of available maps */ 268 }; 269 270 struct tx_sdesc { 271 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 272 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 273 }; 274 275 enum { 276 /* iq flags */ 277 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 278 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 279 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 280 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 281 282 /* iq state */ 283 IQS_DISABLED = 0, 284 IQS_BUSY = 1, 285 IQS_IDLE = 2, 286 }; 287 288 /* 289 * Ingress Queue: T4 is producer, driver is consumer. 290 */ 291 struct sge_iq { 292 bus_dma_tag_t desc_tag; 293 bus_dmamap_t desc_map; 294 bus_addr_t ba; /* bus address of descriptor ring */ 295 uint32_t flags; 296 uint16_t abs_id; /* absolute SGE id for the iq */ 297 int8_t intr_pktc_idx; /* packet count threshold index */ 298 int8_t pad0; 299 __be64 *desc; /* KVA of descriptor ring */ 300 301 volatile int state; 302 struct adapter *adapter; 303 const __be64 *cdesc; /* current descriptor */ 304 uint8_t gen; /* generation bit */ 305 uint8_t intr_params; /* interrupt holdoff parameters */ 306 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 307 uint8_t esize; /* size (bytes) of each entry in the queue */ 308 uint16_t qsize; /* size (# of entries) of the queue */ 309 uint16_t cidx; /* consumer index */ 310 uint16_t cntxt_id; /* SGE context id for the iq */ 311 312 STAILQ_ENTRY(sge_iq) link; 313 }; 314 315 enum { 316 EQ_CTRL = 1, 317 EQ_ETH = 2, 318 #ifdef TCP_OFFLOAD 319 EQ_OFLD = 3, 320 #endif 321 322 /* eq flags */ 323 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 324 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 325 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 326 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 327 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 328 }; 329 330 /* 331 * Egress Queue: driver is producer, T4 is consumer. 332 * 333 * Note: A free list is an egress queue (driver produces the buffers and T4 334 * consumes them) but it's special enough to have its own struct (see sge_fl). 335 */ 336 struct sge_eq { 337 unsigned int flags; /* MUST be first */ 338 unsigned int cntxt_id; /* SGE context id for the eq */ 339 bus_dma_tag_t desc_tag; 340 bus_dmamap_t desc_map; 341 char lockname[16]; 342 struct mtx eq_lock; 343 344 struct tx_desc *desc; /* KVA of descriptor ring */ 345 bus_addr_t ba; /* bus address of descriptor ring */ 346 struct sge_qstat *spg; /* status page, for convenience */ 347 uint16_t cap; /* max # of desc, for convenience */ 348 uint16_t avail; /* available descriptors, for convenience */ 349 uint16_t qsize; /* size (# of entries) of the queue */ 350 uint16_t cidx; /* consumer idx (desc idx) */ 351 uint16_t pidx; /* producer idx (desc idx) */ 352 uint16_t pending; /* # of descriptors used since last doorbell */ 353 uint16_t iqid; /* iq that gets egr_update for the eq */ 354 uint8_t tx_chan; /* tx channel used by the eq */ 355 struct task tx_task; 356 struct callout tx_callout; 357 358 /* stats */ 359 360 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 361 uint32_t unstalled; /* recovered from stall */ 362 }; 363 364 enum { 365 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 366 FL_DOOMED = (1 << 1), /* about to be destroyed */ 367 }; 368 369 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 370 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 371 372 struct sge_fl { 373 bus_dma_tag_t desc_tag; 374 bus_dmamap_t desc_map; 375 bus_dma_tag_t tag[FL_BUF_SIZES]; 376 uint8_t tag_idx; 377 struct mtx fl_lock; 378 char lockname[16]; 379 int flags; 380 381 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 382 bus_addr_t ba; /* bus address of descriptor ring */ 383 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 384 uint32_t cap; /* max # of buffers, for convenience */ 385 uint16_t qsize; /* size (# of entries) of the queue */ 386 uint16_t cntxt_id; /* SGE context id for the freelist */ 387 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 388 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 389 uint32_t needed; /* # of buffers needed to fill up fl. */ 390 uint32_t lowat; /* # of buffers <= this means fl needs help */ 391 uint32_t pending; /* # of bufs allocated since last doorbell */ 392 unsigned int dmamap_failed; 393 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 394 }; 395 396 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 397 struct sge_txq { 398 struct sge_eq eq; /* MUST be first */ 399 400 struct ifnet *ifp; /* the interface this txq belongs to */ 401 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 402 struct buf_ring *br; /* tx buffer ring */ 403 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 404 struct mbuf *m; /* held up due to temporary resource shortage */ 405 406 struct tx_maps txmaps; 407 408 /* stats for common events first */ 409 410 uint64_t txcsum; /* # of times hardware assisted with checksum */ 411 uint64_t tso_wrs; /* # of TSO work requests */ 412 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 413 uint64_t imm_wrs; /* # of work requests with immediate data */ 414 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 415 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 416 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 417 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 418 419 /* stats for not-that-common events */ 420 421 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 422 uint32_t no_desc; /* out of hardware descriptors */ 423 } __aligned(CACHE_LINE_SIZE); 424 425 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 426 struct sge_rxq { 427 struct sge_iq iq; /* MUST be first */ 428 struct sge_fl fl; /* MUST follow iq */ 429 430 struct ifnet *ifp; /* the interface this rxq belongs to */ 431 #if defined(INET) || defined(INET6) 432 struct lro_ctrl lro; /* LRO state */ 433 #endif 434 435 /* stats for common events first */ 436 437 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 438 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 439 440 /* stats for not-that-common events */ 441 442 } __aligned(CACHE_LINE_SIZE); 443 444 static inline struct sge_rxq * 445 iq_to_rxq(struct sge_iq *iq) 446 { 447 448 return (__containerof(iq, struct sge_rxq, iq)); 449 } 450 451 452 #ifdef TCP_OFFLOAD 453 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 454 struct sge_ofld_rxq { 455 struct sge_iq iq; /* MUST be first */ 456 struct sge_fl fl; /* MUST follow iq */ 457 } __aligned(CACHE_LINE_SIZE); 458 459 static inline struct sge_ofld_rxq * 460 iq_to_ofld_rxq(struct sge_iq *iq) 461 { 462 463 return (__containerof(iq, struct sge_ofld_rxq, iq)); 464 } 465 #endif 466 467 struct wrqe { 468 STAILQ_ENTRY(wrqe) link; 469 struct sge_wrq *wrq; 470 int wr_len; 471 uint64_t wr[] __aligned(16); 472 }; 473 474 /* 475 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 476 * and offload tx queues are of this type. 477 */ 478 struct sge_wrq { 479 struct sge_eq eq; /* MUST be first */ 480 481 struct adapter *adapter; 482 483 /* List of WRs held up due to lack of tx descriptors */ 484 STAILQ_HEAD(, wrqe) wr_list; 485 486 /* stats for common events first */ 487 488 uint64_t tx_wrs; /* # of tx work requests */ 489 490 /* stats for not-that-common events */ 491 492 uint32_t no_desc; /* out of hardware descriptors */ 493 } __aligned(CACHE_LINE_SIZE); 494 495 struct sge { 496 int timer_val[SGE_NTIMERS]; 497 int counter_val[SGE_NCOUNTERS]; 498 int fl_starve_threshold; 499 500 int nrxq; /* total # of Ethernet rx queues */ 501 int ntxq; /* total # of Ethernet tx tx queues */ 502 #ifdef TCP_OFFLOAD 503 int nofldrxq; /* total # of TOE rx queues */ 504 int nofldtxq; /* total # of TOE tx queues */ 505 #endif 506 int niq; /* total # of ingress queues */ 507 int neq; /* total # of egress queues */ 508 509 struct sge_iq fwq; /* Firmware event queue */ 510 struct sge_wrq mgmtq; /* Management queue (control queue) */ 511 struct sge_wrq *ctrlq; /* Control queues */ 512 struct sge_txq *txq; /* NIC tx queues */ 513 struct sge_rxq *rxq; /* NIC rx queues */ 514 #ifdef TCP_OFFLOAD 515 struct sge_wrq *ofld_txq; /* TOE tx queues */ 516 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 517 #endif 518 519 uint16_t iq_start; 520 int eq_start; 521 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 522 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 523 }; 524 525 struct rss_header; 526 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 527 struct mbuf *); 528 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 529 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 530 531 struct adapter { 532 SLIST_ENTRY(adapter) link; 533 device_t dev; 534 struct cdev *cdev; 535 536 /* PCIe register resources */ 537 int regs_rid; 538 struct resource *regs_res; 539 int msix_rid; 540 struct resource *msix_res; 541 bus_space_handle_t bh; 542 bus_space_tag_t bt; 543 bus_size_t mmio_len; 544 545 unsigned int pf; 546 unsigned int mbox; 547 548 /* Interrupt information */ 549 int intr_type; 550 int intr_count; 551 struct irq { 552 struct resource *res; 553 int rid; 554 void *tag; 555 } *irq; 556 557 bus_dma_tag_t dmat; /* Parent DMA tag */ 558 559 struct sge sge; 560 561 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 562 struct port_info *port[MAX_NPORTS]; 563 uint8_t chan_map[NCHAN]; 564 uint32_t filter_mode; 565 566 #ifdef TCP_OFFLOAD 567 void *tom_softc; /* (struct tom_data *) */ 568 struct tom_tunables tt; 569 #endif 570 struct l2t_data *l2t; /* L2 table */ 571 struct tid_info tids; 572 573 int open_device_map; 574 #ifdef TCP_OFFLOAD 575 int offload_map; 576 #endif 577 int flags; 578 579 char fw_version[32]; 580 char cfg_file[32]; 581 u_int cfcsum; 582 struct adapter_params params; 583 struct t4_virt_res vres; 584 585 uint16_t linkcaps; 586 uint16_t niccaps; 587 uint16_t toecaps; 588 uint16_t rdmacaps; 589 uint16_t iscsicaps; 590 uint16_t fcoecaps; 591 592 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 593 594 struct mtx sc_lock; 595 char lockname[16]; 596 597 /* Starving free lists */ 598 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 599 TAILQ_HEAD(, sge_fl) sfl; 600 struct callout sfl_callout; 601 602 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 603 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 604 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 605 606 #ifdef INVARIANTS 607 const char *last_op; 608 const void *last_op_thr; 609 #endif 610 }; 611 612 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 613 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 614 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 615 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 616 617 /* XXX: not bulletproof, but much better than nothing */ 618 #define ASSERT_SYNCHRONIZED_OP(sc) \ 619 KASSERT(IS_BUSY(sc) && \ 620 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 621 ("%s: operation not synchronized.", __func__)) 622 623 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 624 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 625 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 626 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 627 628 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 629 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 630 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 631 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 632 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 633 634 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 635 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 636 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 637 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 638 639 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 640 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 641 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 642 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 643 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 644 645 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 646 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 647 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 648 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 649 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 650 651 #define for_each_txq(pi, iter, q) \ 652 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 653 iter < pi->ntxq; ++iter, ++q) 654 #define for_each_rxq(pi, iter, q) \ 655 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 656 iter < pi->nrxq; ++iter, ++q) 657 #define for_each_ofld_txq(pi, iter, q) \ 658 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 659 iter < pi->nofldtxq; ++iter, ++q) 660 #define for_each_ofld_rxq(pi, iter, q) \ 661 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 662 iter < pi->nofldrxq; ++iter, ++q) 663 664 /* One for errors, one for firmware events */ 665 #define T4_EXTRA_INTR 2 666 667 static inline uint32_t 668 t4_read_reg(struct adapter *sc, uint32_t reg) 669 { 670 671 return bus_space_read_4(sc->bt, sc->bh, reg); 672 } 673 674 static inline void 675 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 676 { 677 678 bus_space_write_4(sc->bt, sc->bh, reg, val); 679 } 680 681 static inline uint64_t 682 t4_read_reg64(struct adapter *sc, uint32_t reg) 683 { 684 685 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 686 } 687 688 static inline void 689 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 690 { 691 692 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 693 } 694 695 static inline void 696 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 697 { 698 699 *val = pci_read_config(sc->dev, reg, 1); 700 } 701 702 static inline void 703 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 704 { 705 706 pci_write_config(sc->dev, reg, val, 1); 707 } 708 709 static inline void 710 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 711 { 712 713 *val = pci_read_config(sc->dev, reg, 2); 714 } 715 716 static inline void 717 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 718 { 719 720 pci_write_config(sc->dev, reg, val, 2); 721 } 722 723 static inline void 724 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 725 { 726 727 *val = pci_read_config(sc->dev, reg, 4); 728 } 729 730 static inline void 731 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 732 { 733 734 pci_write_config(sc->dev, reg, val, 4); 735 } 736 737 static inline struct port_info * 738 adap2pinfo(struct adapter *sc, int idx) 739 { 740 741 return (sc->port[idx]); 742 } 743 744 static inline void 745 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 746 { 747 748 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 749 } 750 751 static inline bool is_10G_port(const struct port_info *pi) 752 { 753 754 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 755 } 756 757 static inline int tx_resume_threshold(struct sge_eq *eq) 758 { 759 760 return (eq->qsize / 4); 761 } 762 763 /* t4_main.c */ 764 void t4_tx_task(void *, int); 765 void t4_tx_callout(void *); 766 int t4_os_find_pci_capability(struct adapter *, int); 767 int t4_os_pci_save_state(struct adapter *); 768 int t4_os_pci_restore_state(struct adapter *); 769 void t4_os_portmod_changed(const struct adapter *, int); 770 void t4_os_link_changed(struct adapter *, int, int); 771 void t4_iterate(void (*)(struct adapter *, void *), void *); 772 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 773 int t4_register_an_handler(struct adapter *, an_handler_t); 774 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 775 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 776 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 777 void end_synchronized_op(struct adapter *, int); 778 779 /* t4_sge.c */ 780 void t4_sge_modload(void); 781 int t4_sge_init(struct adapter *); 782 int t4_create_dma_tag(struct adapter *); 783 int t4_destroy_dma_tag(struct adapter *); 784 int t4_setup_adapter_queues(struct adapter *); 785 int t4_teardown_adapter_queues(struct adapter *); 786 int t4_setup_port_queues(struct port_info *); 787 int t4_teardown_port_queues(struct port_info *); 788 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 789 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 790 void t4_intr_all(void *); 791 void t4_intr(void *); 792 void t4_intr_err(void *); 793 void t4_intr_evt(void *); 794 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 795 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 796 void t4_update_fl_bufsize(struct ifnet *); 797 int can_resume_tx(struct sge_eq *); 798 799 static inline struct wrqe * 800 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 801 { 802 int len = offsetof(struct wrqe, wr) + wr_len; 803 struct wrqe *wr; 804 805 wr = malloc(len, M_CXGBE, M_NOWAIT); 806 if (__predict_false(wr == NULL)) 807 return (NULL); 808 wr->wr_len = wr_len; 809 wr->wrq = wrq; 810 return (wr); 811 } 812 813 static inline void * 814 wrtod(struct wrqe *wr) 815 { 816 return (&wr->wr[0]); 817 } 818 819 static inline void 820 free_wrqe(struct wrqe *wr) 821 { 822 free(wr, M_CXGBE); 823 } 824 825 static inline void 826 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 827 { 828 struct sge_wrq *wrq = wr->wrq; 829 830 TXQ_LOCK(wrq); 831 t4_wrq_tx_locked(sc, wrq, wr); 832 TXQ_UNLOCK(wrq); 833 } 834 835 #endif 836