1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "firmware/t4fw_interface.h" 58 59 MALLOC_DECLARE(M_CXGBE); 60 #define CXGBE_UNIMPLEMENTED(s) \ 61 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 62 63 #if defined(__i386__) || defined(__amd64__) 64 static __inline void 65 prefetch(void *x) 66 { 67 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 68 } 69 #else 70 #define prefetch(x) 71 #endif 72 73 #ifndef SYSCTL_ADD_UQUAD 74 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 75 #define sysctl_handle_64 sysctl_handle_quad 76 #define CTLTYPE_U64 CTLTYPE_QUAD 77 #endif 78 79 #if (__FreeBSD_version >= 900030) || \ 80 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 81 #define SBUF_DRAIN 1 82 #endif 83 84 #ifdef __amd64__ 85 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 86 static __inline uint64_t 87 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 88 bus_size_t offset) 89 { 90 KASSERT(tag == X86_BUS_SPACE_MEM, 91 ("%s: can only handle mem space", __func__)); 92 93 return (*(volatile uint64_t *)(handle + offset)); 94 } 95 96 static __inline void 97 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 98 bus_size_t offset, uint64_t value) 99 { 100 KASSERT(tag == X86_BUS_SPACE_MEM, 101 ("%s: can only handle mem space", __func__)); 102 103 *(volatile uint64_t *)(bsh + offset) = value; 104 } 105 #else 106 static __inline uint64_t 107 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 108 bus_size_t offset) 109 { 110 return (uint64_t)bus_space_read_4(tag, handle, offset) + 111 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 112 } 113 114 static __inline void 115 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 116 bus_size_t offset, uint64_t value) 117 { 118 bus_space_write_4(tag, bsh, offset, value); 119 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 120 } 121 #endif 122 123 struct adapter; 124 typedef struct adapter adapter_t; 125 126 enum { 127 FW_IQ_QSIZE = 256, 128 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 129 130 RX_IQ_QSIZE = 1024, 131 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 132 133 EQ_ESIZE = 64, /* All egress queues use this entry size */ 134 135 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 136 #if MJUMPAGESIZE != MCLBYTES 137 FL_BUF_SIZES_MAX = 5, /* cluster, jumbop, jumbo9k, jumbo16k, extra */ 138 #else 139 FL_BUF_SIZES_MAX = 4, /* cluster, jumbo9k, jumbo16k, extra */ 140 #endif 141 142 CTRL_EQ_QSIZE = 128, 143 144 TX_EQ_QSIZE = 1024, 145 TX_SGL_SEGS = 36, 146 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 147 }; 148 149 enum { 150 /* adapter intr_type */ 151 INTR_INTX = (1 << 0), 152 INTR_MSI = (1 << 1), 153 INTR_MSIX = (1 << 2) 154 }; 155 156 enum { 157 /* flags understood by begin_synchronized_op */ 158 HOLD_LOCK = (1 << 0), 159 SLEEP_OK = (1 << 1), 160 INTR_OK = (1 << 2), 161 162 /* flags understood by end_synchronized_op */ 163 LOCK_HELD = HOLD_LOCK, 164 }; 165 166 enum { 167 /* adapter flags */ 168 FULL_INIT_DONE = (1 << 0), 169 FW_OK = (1 << 1), 170 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 171 MASTER_PF = (1 << 3), 172 ADAP_SYSCTL_CTX = (1 << 4), 173 TOM_INIT_DONE = (1 << 5), 174 BUF_PACKING_OK = (1 << 6), 175 176 CXGBE_BUSY = (1 << 9), 177 178 /* port flags */ 179 DOOMED = (1 << 0), 180 PORT_INIT_DONE = (1 << 1), 181 PORT_SYSCTL_CTX = (1 << 2), 182 HAS_TRACEQ = (1 << 3), 183 }; 184 185 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 186 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 187 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 188 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 189 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 190 191 struct port_info { 192 device_t dev; 193 struct adapter *adapter; 194 195 struct ifnet *ifp; 196 struct ifmedia media; 197 198 struct mtx pi_lock; 199 char lockname[16]; 200 unsigned long flags; 201 int if_flags; 202 203 uint16_t viid; 204 int16_t xact_addr_filt;/* index of exact MAC address filter */ 205 uint16_t rss_size; /* size of VI's RSS table slice */ 206 uint8_t lport; /* associated offload logical port */ 207 int8_t mdio_addr; 208 uint8_t port_type; 209 uint8_t mod_type; 210 uint8_t port_id; 211 uint8_t tx_chan; 212 213 /* These need to be int as they are used in sysctl */ 214 int ntxq; /* # of tx queues */ 215 int first_txq; /* index of first tx queue */ 216 int nrxq; /* # of rx queues */ 217 int first_rxq; /* index of first rx queue */ 218 #ifdef TCP_OFFLOAD 219 int nofldtxq; /* # of offload tx queues */ 220 int first_ofld_txq; /* index of first offload tx queue */ 221 int nofldrxq; /* # of offload rx queues */ 222 int first_ofld_rxq; /* index of first offload rx queue */ 223 #endif 224 int tmr_idx; 225 int pktc_idx; 226 int qsize_rxq; 227 int qsize_txq; 228 229 int linkdnrc; 230 struct link_config link_cfg; 231 struct port_stats stats; 232 233 eventhandler_tag vlan_c; 234 235 struct callout tick; 236 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 237 238 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 239 }; 240 241 struct fl_sdesc { 242 bus_dmamap_t map; 243 caddr_t cl; 244 uint8_t tag_idx; /* the fl->tag entry this map comes from */ 245 #ifdef INVARIANTS 246 __be64 ba_hwtag; 247 #endif 248 }; 249 250 struct tx_desc { 251 __be64 flit[8]; 252 }; 253 254 struct tx_map { 255 struct mbuf *m; 256 bus_dmamap_t map; 257 }; 258 259 /* DMA maps used for tx */ 260 struct tx_maps { 261 struct tx_map *maps; 262 uint32_t map_total; /* # of DMA maps */ 263 uint32_t map_pidx; /* next map to be used */ 264 uint32_t map_cidx; /* reclaimed up to this index */ 265 uint32_t map_avail; /* # of available maps */ 266 }; 267 268 struct tx_sdesc { 269 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 270 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 271 }; 272 273 enum { 274 /* iq flags */ 275 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 276 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 277 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 278 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 279 280 /* iq state */ 281 IQS_DISABLED = 0, 282 IQS_BUSY = 1, 283 IQS_IDLE = 2, 284 }; 285 286 /* 287 * Ingress Queue: T4 is producer, driver is consumer. 288 */ 289 struct sge_iq { 290 bus_dma_tag_t desc_tag; 291 bus_dmamap_t desc_map; 292 bus_addr_t ba; /* bus address of descriptor ring */ 293 uint32_t flags; 294 uint16_t abs_id; /* absolute SGE id for the iq */ 295 int8_t intr_pktc_idx; /* packet count threshold index */ 296 int8_t pad0; 297 __be64 *desc; /* KVA of descriptor ring */ 298 299 volatile int state; 300 struct adapter *adapter; 301 const __be64 *cdesc; /* current descriptor */ 302 uint8_t gen; /* generation bit */ 303 uint8_t intr_params; /* interrupt holdoff parameters */ 304 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 305 uint8_t esize; /* size (bytes) of each entry in the queue */ 306 uint16_t qsize; /* size (# of entries) of the queue */ 307 uint16_t cidx; /* consumer index */ 308 uint16_t cntxt_id; /* SGE context id for the iq */ 309 310 STAILQ_ENTRY(sge_iq) link; 311 }; 312 313 enum { 314 EQ_CTRL = 1, 315 EQ_ETH = 2, 316 #ifdef TCP_OFFLOAD 317 EQ_OFLD = 3, 318 #endif 319 320 /* eq flags */ 321 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 322 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 323 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 324 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 325 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 326 }; 327 328 /* Listed in order of preference. Update t4_sysctls too if you change these */ 329 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 330 331 /* 332 * Egress Queue: driver is producer, T4 is consumer. 333 * 334 * Note: A free list is an egress queue (driver produces the buffers and T4 335 * consumes them) but it's special enough to have its own struct (see sge_fl). 336 */ 337 struct sge_eq { 338 unsigned int flags; /* MUST be first */ 339 unsigned int cntxt_id; /* SGE context id for the eq */ 340 bus_dma_tag_t desc_tag; 341 bus_dmamap_t desc_map; 342 char lockname[16]; 343 struct mtx eq_lock; 344 345 struct tx_desc *desc; /* KVA of descriptor ring */ 346 bus_addr_t ba; /* bus address of descriptor ring */ 347 struct sge_qstat *spg; /* status page, for convenience */ 348 int doorbells; 349 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 350 u_int udb_qid; /* relative qid within the doorbell page */ 351 uint16_t cap; /* max # of desc, for convenience */ 352 uint16_t avail; /* available descriptors, for convenience */ 353 uint16_t qsize; /* size (# of entries) of the queue */ 354 uint16_t cidx; /* consumer idx (desc idx) */ 355 uint16_t pidx; /* producer idx (desc idx) */ 356 uint16_t pending; /* # of descriptors used since last doorbell */ 357 uint16_t iqid; /* iq that gets egr_update for the eq */ 358 uint8_t tx_chan; /* tx channel used by the eq */ 359 struct task tx_task; 360 struct callout tx_callout; 361 362 /* stats */ 363 364 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 365 uint32_t unstalled; /* recovered from stall */ 366 }; 367 368 struct fl_buf_info { 369 u_int size; 370 int type; 371 int hwtag:4; /* tag in low 4 bits of the pa. */ 372 uma_zone_t zone; 373 }; 374 #define FL_BUF_SIZES(sc) (sc->sge.fl_buf_sizes) 375 #define FL_BUF_SIZE(sc, x) (sc->sge.fl_buf_info[x].size) 376 #define FL_BUF_TYPE(sc, x) (sc->sge.fl_buf_info[x].type) 377 #define FL_BUF_HWTAG(sc, x) (sc->sge.fl_buf_info[x].hwtag) 378 #define FL_BUF_ZONE(sc, x) (sc->sge.fl_buf_info[x].zone) 379 380 enum { 381 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 382 FL_DOOMED = (1 << 1), /* about to be destroyed */ 383 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 384 }; 385 386 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 387 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 388 389 struct sge_fl { 390 bus_dma_tag_t desc_tag; 391 bus_dmamap_t desc_map; 392 bus_dma_tag_t tag[FL_BUF_SIZES_MAX]; /* only first FL_BUF_SIZES(sc) are 393 valid */ 394 uint8_t tag_idx; 395 struct mtx fl_lock; 396 char lockname[16]; 397 int flags; 398 399 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 400 bus_addr_t ba; /* bus address of descriptor ring */ 401 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 402 uint32_t cap; /* max # of buffers, for convenience */ 403 uint16_t qsize; /* size (# of entries) of the queue */ 404 uint16_t cntxt_id; /* SGE context id for the freelist */ 405 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 406 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 407 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 408 uint32_t needed; /* # of buffers needed to fill up fl. */ 409 uint32_t lowat; /* # of buffers <= this means fl needs help */ 410 uint32_t pending; /* # of bufs allocated since last doorbell */ 411 u_int dmamap_failed; 412 struct mbuf *mstash[8]; 413 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 414 }; 415 416 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 417 struct sge_txq { 418 struct sge_eq eq; /* MUST be first */ 419 420 struct ifnet *ifp; /* the interface this txq belongs to */ 421 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 422 struct buf_ring *br; /* tx buffer ring */ 423 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 424 struct mbuf *m; /* held up due to temporary resource shortage */ 425 426 struct tx_maps txmaps; 427 428 /* stats for common events first */ 429 430 uint64_t txcsum; /* # of times hardware assisted with checksum */ 431 uint64_t tso_wrs; /* # of TSO work requests */ 432 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 433 uint64_t imm_wrs; /* # of work requests with immediate data */ 434 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 435 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 436 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 437 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 438 439 /* stats for not-that-common events */ 440 441 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 442 uint32_t no_desc; /* out of hardware descriptors */ 443 } __aligned(CACHE_LINE_SIZE); 444 445 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 446 struct sge_rxq { 447 struct sge_iq iq; /* MUST be first */ 448 struct sge_fl fl; /* MUST follow iq */ 449 450 struct ifnet *ifp; /* the interface this rxq belongs to */ 451 #if defined(INET) || defined(INET6) 452 struct lro_ctrl lro; /* LRO state */ 453 #endif 454 455 /* stats for common events first */ 456 457 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 458 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 459 460 /* stats for not-that-common events */ 461 462 } __aligned(CACHE_LINE_SIZE); 463 464 static inline struct sge_rxq * 465 iq_to_rxq(struct sge_iq *iq) 466 { 467 468 return (__containerof(iq, struct sge_rxq, iq)); 469 } 470 471 472 #ifdef TCP_OFFLOAD 473 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 474 struct sge_ofld_rxq { 475 struct sge_iq iq; /* MUST be first */ 476 struct sge_fl fl; /* MUST follow iq */ 477 } __aligned(CACHE_LINE_SIZE); 478 479 static inline struct sge_ofld_rxq * 480 iq_to_ofld_rxq(struct sge_iq *iq) 481 { 482 483 return (__containerof(iq, struct sge_ofld_rxq, iq)); 484 } 485 #endif 486 487 struct wrqe { 488 STAILQ_ENTRY(wrqe) link; 489 struct sge_wrq *wrq; 490 int wr_len; 491 uint64_t wr[] __aligned(16); 492 }; 493 494 /* 495 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 496 * and offload tx queues are of this type. 497 */ 498 struct sge_wrq { 499 struct sge_eq eq; /* MUST be first */ 500 501 struct adapter *adapter; 502 503 /* List of WRs held up due to lack of tx descriptors */ 504 STAILQ_HEAD(, wrqe) wr_list; 505 506 /* stats for common events first */ 507 508 uint64_t tx_wrs; /* # of tx work requests */ 509 510 /* stats for not-that-common events */ 511 512 uint32_t no_desc; /* out of hardware descriptors */ 513 } __aligned(CACHE_LINE_SIZE); 514 515 struct sge { 516 int timer_val[SGE_NTIMERS]; 517 int counter_val[SGE_NCOUNTERS]; 518 int fl_starve_threshold; 519 int eq_s_qpp; 520 int iq_s_qpp; 521 522 int nrxq; /* total # of Ethernet rx queues */ 523 int ntxq; /* total # of Ethernet tx tx queues */ 524 #ifdef TCP_OFFLOAD 525 int nofldrxq; /* total # of TOE rx queues */ 526 int nofldtxq; /* total # of TOE tx queues */ 527 #endif 528 int niq; /* total # of ingress queues */ 529 int neq; /* total # of egress queues */ 530 531 struct sge_iq fwq; /* Firmware event queue */ 532 struct sge_wrq mgmtq; /* Management queue (control queue) */ 533 struct sge_wrq *ctrlq; /* Control queues */ 534 struct sge_txq *txq; /* NIC tx queues */ 535 struct sge_rxq *rxq; /* NIC rx queues */ 536 #ifdef TCP_OFFLOAD 537 struct sge_wrq *ofld_txq; /* TOE tx queues */ 538 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 539 #endif 540 541 uint16_t iq_start; 542 int eq_start; 543 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 544 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 545 546 u_int fl_buf_sizes __aligned(CACHE_LINE_SIZE); 547 struct fl_buf_info fl_buf_info[FL_BUF_SIZES_MAX]; 548 }; 549 550 struct rss_header; 551 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 552 struct mbuf *); 553 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 554 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 555 556 struct adapter { 557 SLIST_ENTRY(adapter) link; 558 device_t dev; 559 struct cdev *cdev; 560 561 /* PCIe register resources */ 562 int regs_rid; 563 struct resource *regs_res; 564 int msix_rid; 565 struct resource *msix_res; 566 bus_space_handle_t bh; 567 bus_space_tag_t bt; 568 bus_size_t mmio_len; 569 int udbs_rid; 570 struct resource *udbs_res; 571 volatile uint8_t *udbs_base; 572 573 unsigned int pf; 574 unsigned int mbox; 575 576 /* Interrupt information */ 577 int intr_type; 578 int intr_count; 579 struct irq { 580 struct resource *res; 581 int rid; 582 void *tag; 583 } *irq; 584 585 bus_dma_tag_t dmat; /* Parent DMA tag */ 586 587 struct sge sge; 588 int lro_timeout; 589 590 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 591 struct port_info *port[MAX_NPORTS]; 592 uint8_t chan_map[NCHAN]; 593 594 #ifdef TCP_OFFLOAD 595 void *tom_softc; /* (struct tom_data *) */ 596 struct tom_tunables tt; 597 void *iwarp_softc; /* (struct c4iw_dev *) */ 598 #endif 599 struct l2t_data *l2t; /* L2 table */ 600 struct tid_info tids; 601 602 int doorbells; 603 int open_device_map; 604 #ifdef TCP_OFFLOAD 605 int offload_map; 606 #endif 607 int flags; 608 609 char ifp_lockname[16]; 610 struct mtx ifp_lock; 611 struct ifnet *ifp; /* tracer ifp */ 612 struct ifmedia media; 613 int traceq; /* iq used by all tracers, -1 if none */ 614 int tracer_valid; /* bitmap of valid tracers */ 615 int tracer_enabled; /* bitmap of enabled tracers */ 616 617 char fw_version[32]; 618 char cfg_file[32]; 619 u_int cfcsum; 620 struct adapter_params params; 621 struct t4_virt_res vres; 622 623 uint16_t linkcaps; 624 uint16_t niccaps; 625 uint16_t toecaps; 626 uint16_t rdmacaps; 627 uint16_t iscsicaps; 628 uint16_t fcoecaps; 629 630 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 631 632 struct mtx sc_lock; 633 char lockname[16]; 634 635 /* Starving free lists */ 636 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 637 TAILQ_HEAD(, sge_fl) sfl; 638 struct callout sfl_callout; 639 640 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 641 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 642 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 643 644 #ifdef INVARIANTS 645 const char *last_op; 646 const void *last_op_thr; 647 #endif 648 }; 649 650 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 651 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 652 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 653 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 654 655 /* XXX: not bulletproof, but much better than nothing */ 656 #define ASSERT_SYNCHRONIZED_OP(sc) \ 657 KASSERT(IS_BUSY(sc) && \ 658 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 659 ("%s: operation not synchronized.", __func__)) 660 661 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 662 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 663 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 664 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 665 666 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 667 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 668 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 669 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 670 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 671 672 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 673 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 674 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 675 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 676 677 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 678 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 679 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 680 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 681 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 682 683 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 684 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 685 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 686 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 687 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 688 689 #define for_each_txq(pi, iter, q) \ 690 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 691 iter < pi->ntxq; ++iter, ++q) 692 #define for_each_rxq(pi, iter, q) \ 693 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 694 iter < pi->nrxq; ++iter, ++q) 695 #define for_each_ofld_txq(pi, iter, q) \ 696 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 697 iter < pi->nofldtxq; ++iter, ++q) 698 #define for_each_ofld_rxq(pi, iter, q) \ 699 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 700 iter < pi->nofldrxq; ++iter, ++q) 701 702 /* One for errors, one for firmware events */ 703 #define T4_EXTRA_INTR 2 704 705 static inline uint32_t 706 t4_read_reg(struct adapter *sc, uint32_t reg) 707 { 708 709 return bus_space_read_4(sc->bt, sc->bh, reg); 710 } 711 712 static inline void 713 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 714 { 715 716 bus_space_write_4(sc->bt, sc->bh, reg, val); 717 } 718 719 static inline uint64_t 720 t4_read_reg64(struct adapter *sc, uint32_t reg) 721 { 722 723 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 724 } 725 726 static inline void 727 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 728 { 729 730 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 731 } 732 733 static inline void 734 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 735 { 736 737 *val = pci_read_config(sc->dev, reg, 1); 738 } 739 740 static inline void 741 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 742 { 743 744 pci_write_config(sc->dev, reg, val, 1); 745 } 746 747 static inline void 748 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 749 { 750 751 *val = pci_read_config(sc->dev, reg, 2); 752 } 753 754 static inline void 755 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 756 { 757 758 pci_write_config(sc->dev, reg, val, 2); 759 } 760 761 static inline void 762 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 763 { 764 765 *val = pci_read_config(sc->dev, reg, 4); 766 } 767 768 static inline void 769 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 770 { 771 772 pci_write_config(sc->dev, reg, val, 4); 773 } 774 775 static inline struct port_info * 776 adap2pinfo(struct adapter *sc, int idx) 777 { 778 779 return (sc->port[idx]); 780 } 781 782 static inline void 783 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 784 { 785 786 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 787 } 788 789 static inline bool 790 is_10G_port(const struct port_info *pi) 791 { 792 793 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 794 } 795 796 static inline bool 797 is_40G_port(const struct port_info *pi) 798 { 799 800 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 801 } 802 803 static inline int 804 tx_resume_threshold(struct sge_eq *eq) 805 { 806 807 return (eq->qsize / 4); 808 } 809 810 /* t4_main.c */ 811 void t4_tx_task(void *, int); 812 void t4_tx_callout(void *); 813 int t4_os_find_pci_capability(struct adapter *, int); 814 int t4_os_pci_save_state(struct adapter *); 815 int t4_os_pci_restore_state(struct adapter *); 816 void t4_os_portmod_changed(const struct adapter *, int); 817 void t4_os_link_changed(struct adapter *, int, int, int); 818 void t4_iterate(void (*)(struct adapter *, void *), void *); 819 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 820 int t4_register_an_handler(struct adapter *, an_handler_t); 821 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 822 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 823 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 824 void end_synchronized_op(struct adapter *, int); 825 826 /* t4_sge.c */ 827 void t4_sge_modload(void); 828 void t4_init_sge_cpl_handlers(struct adapter *); 829 void t4_tweak_chip_settings(struct adapter *); 830 int t4_read_chip_settings(struct adapter *); 831 int t4_create_dma_tag(struct adapter *); 832 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 833 struct sysctl_oid_list *); 834 int t4_destroy_dma_tag(struct adapter *); 835 int t4_setup_adapter_queues(struct adapter *); 836 int t4_teardown_adapter_queues(struct adapter *); 837 int t4_setup_port_queues(struct port_info *); 838 int t4_teardown_port_queues(struct port_info *); 839 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 840 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 841 void t4_intr_all(void *); 842 void t4_intr(void *); 843 void t4_intr_err(void *); 844 void t4_intr_evt(void *); 845 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 846 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 847 void t4_update_fl_bufsize(struct ifnet *); 848 int can_resume_tx(struct sge_eq *); 849 850 /* t4_tracer.c */ 851 struct t4_tracer; 852 void t4_tracer_modload(void); 853 void t4_tracer_modunload(void); 854 void t4_tracer_port_detach(struct adapter *); 855 int t4_get_tracer(struct adapter *, struct t4_tracer *); 856 int t4_set_tracer(struct adapter *, struct t4_tracer *); 857 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 858 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 859 860 static inline struct wrqe * 861 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 862 { 863 int len = offsetof(struct wrqe, wr) + wr_len; 864 struct wrqe *wr; 865 866 wr = malloc(len, M_CXGBE, M_NOWAIT); 867 if (__predict_false(wr == NULL)) 868 return (NULL); 869 wr->wr_len = wr_len; 870 wr->wrq = wrq; 871 return (wr); 872 } 873 874 static inline void * 875 wrtod(struct wrqe *wr) 876 { 877 return (&wr->wr[0]); 878 } 879 880 static inline void 881 free_wrqe(struct wrqe *wr) 882 { 883 free(wr, M_CXGBE); 884 } 885 886 static inline void 887 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 888 { 889 struct sge_wrq *wrq = wr->wrq; 890 891 TXQ_LOCK(wrq); 892 t4_wrq_tx_locked(sc, wrq, wr); 893 TXQ_UNLOCK(wrq); 894 } 895 896 #endif 897