1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/tcp_lro.h> 48 49 #include "offload.h" 50 #include "firmware/t4fw_interface.h" 51 52 #define T4_CFGNAME "t4fw_cfg" 53 #define T4_FWNAME "t4fw" 54 55 MALLOC_DECLARE(M_CXGBE); 56 #define CXGBE_UNIMPLEMENTED(s) \ 57 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 58 59 #if defined(__i386__) || defined(__amd64__) 60 static __inline void 61 prefetch(void *x) 62 { 63 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 64 } 65 #else 66 #define prefetch(x) 67 #endif 68 69 #ifndef SYSCTL_ADD_UQUAD 70 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 71 #define sysctl_handle_64 sysctl_handle_quad 72 #define CTLTYPE_U64 CTLTYPE_QUAD 73 #endif 74 75 #if (__FreeBSD_version >= 900030) || \ 76 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 77 #define SBUF_DRAIN 1 78 #endif 79 80 #ifdef __amd64__ 81 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 82 static __inline uint64_t 83 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 84 bus_size_t offset) 85 { 86 KASSERT(tag == X86_BUS_SPACE_MEM, 87 ("%s: can only handle mem space", __func__)); 88 89 return (*(volatile uint64_t *)(handle + offset)); 90 } 91 92 static __inline void 93 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 94 bus_size_t offset, uint64_t value) 95 { 96 KASSERT(tag == X86_BUS_SPACE_MEM, 97 ("%s: can only handle mem space", __func__)); 98 99 *(volatile uint64_t *)(bsh + offset) = value; 100 } 101 #else 102 static __inline uint64_t 103 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 104 bus_size_t offset) 105 { 106 return (uint64_t)bus_space_read_4(tag, handle, offset) + 107 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 108 } 109 110 static __inline void 111 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 112 bus_size_t offset, uint64_t value) 113 { 114 bus_space_write_4(tag, bsh, offset, value); 115 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 116 } 117 #endif 118 119 struct adapter; 120 typedef struct adapter adapter_t; 121 122 enum { 123 FW_IQ_QSIZE = 256, 124 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 125 126 RX_IQ_QSIZE = 1024, 127 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 128 129 EQ_ESIZE = 64, /* All egress queues use this entry size */ 130 131 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 132 #if MJUMPAGESIZE != MCLBYTES 133 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 134 #else 135 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 136 #endif 137 138 CTRL_EQ_QSIZE = 128, 139 140 TX_EQ_QSIZE = 1024, 141 TX_SGL_SEGS = 36, 142 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 143 }; 144 145 enum { 146 /* adapter intr_type */ 147 INTR_INTX = (1 << 0), 148 INTR_MSI = (1 << 1), 149 INTR_MSIX = (1 << 2) 150 }; 151 152 enum { 153 /* adapter flags */ 154 FULL_INIT_DONE = (1 << 0), 155 FW_OK = (1 << 1), 156 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 157 MASTER_PF = (1 << 3), 158 ADAP_SYSCTL_CTX = (1 << 4), 159 160 CXGBE_BUSY = (1 << 9), 161 162 /* port flags */ 163 DOOMED = (1 << 0), 164 PORT_INIT_DONE = (1 << 1), 165 PORT_SYSCTL_CTX = (1 << 2), 166 }; 167 168 #define IS_DOOMED(pi) (pi->flags & DOOMED) 169 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 170 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 171 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 172 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 173 174 struct port_info { 175 device_t dev; 176 struct adapter *adapter; 177 178 struct ifnet *ifp; 179 struct ifmedia media; 180 181 struct mtx pi_lock; 182 char lockname[16]; 183 unsigned long flags; 184 int if_flags; 185 186 uint16_t viid; 187 int16_t xact_addr_filt;/* index of exact MAC address filter */ 188 uint16_t rss_size; /* size of VI's RSS table slice */ 189 uint8_t lport; /* associated offload logical port */ 190 int8_t mdio_addr; 191 uint8_t port_type; 192 uint8_t mod_type; 193 uint8_t port_id; 194 uint8_t tx_chan; 195 196 /* These need to be int as they are used in sysctl */ 197 int ntxq; /* # of tx queues */ 198 int first_txq; /* index of first tx queue */ 199 int nrxq; /* # of rx queues */ 200 int first_rxq; /* index of first rx queue */ 201 #ifndef TCP_OFFLOAD_DISABLE 202 int nofldtxq; /* # of offload tx queues */ 203 int first_ofld_txq; /* index of first offload tx queue */ 204 int nofldrxq; /* # of offload rx queues */ 205 int first_ofld_rxq; /* index of first offload rx queue */ 206 #endif 207 int tmr_idx; 208 int pktc_idx; 209 int qsize_rxq; 210 int qsize_txq; 211 212 struct link_config link_cfg; 213 struct port_stats stats; 214 215 struct callout tick; 216 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 217 218 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 219 }; 220 221 struct fl_sdesc { 222 struct mbuf *m; 223 bus_dmamap_t map; 224 caddr_t cl; 225 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 226 #ifdef INVARIANTS 227 __be64 ba_tag; 228 #endif 229 }; 230 231 struct tx_desc { 232 __be64 flit[8]; 233 }; 234 235 struct tx_map { 236 struct mbuf *m; 237 bus_dmamap_t map; 238 }; 239 240 /* DMA maps used for tx */ 241 struct tx_maps { 242 struct tx_map *maps; 243 uint32_t map_total; /* # of DMA maps */ 244 uint32_t map_pidx; /* next map to be used */ 245 uint32_t map_cidx; /* reclaimed up to this index */ 246 uint32_t map_avail; /* # of available maps */ 247 }; 248 249 struct tx_sdesc { 250 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 251 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 252 }; 253 254 enum { 255 /* iq flags */ 256 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 257 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 258 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 259 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 260 261 /* iq state */ 262 IQS_DISABLED = 0, 263 IQS_BUSY = 1, 264 IQS_IDLE = 2, 265 }; 266 267 /* 268 * Ingress Queue: T4 is producer, driver is consumer. 269 */ 270 struct sge_iq { 271 bus_dma_tag_t desc_tag; 272 bus_dmamap_t desc_map; 273 bus_addr_t ba; /* bus address of descriptor ring */ 274 char lockname[16]; 275 uint32_t flags; 276 uint16_t abs_id; /* absolute SGE id for the iq */ 277 int8_t intr_pktc_idx; /* packet count threshold index */ 278 int8_t pad0; 279 __be64 *desc; /* KVA of descriptor ring */ 280 281 volatile int state; 282 struct adapter *adapter; 283 const __be64 *cdesc; /* current descriptor */ 284 uint8_t gen; /* generation bit */ 285 uint8_t intr_params; /* interrupt holdoff parameters */ 286 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 287 uint8_t esize; /* size (bytes) of each entry in the queue */ 288 uint16_t qsize; /* size (# of entries) of the queue */ 289 uint16_t cidx; /* consumer index */ 290 uint16_t cntxt_id; /* SGE context id for the iq */ 291 292 STAILQ_ENTRY(sge_iq) link; 293 }; 294 295 enum { 296 EQ_CTRL = 1, 297 EQ_ETH = 2, 298 #ifndef TCP_OFFLOAD_DISABLE 299 EQ_OFLD = 3, 300 #endif 301 302 /* eq flags */ 303 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 304 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 305 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 306 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 307 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 308 }; 309 310 /* 311 * Egress Queue: driver is producer, T4 is consumer. 312 * 313 * Note: A free list is an egress queue (driver produces the buffers and T4 314 * consumes them) but it's special enough to have its own struct (see sge_fl). 315 */ 316 struct sge_eq { 317 unsigned int flags; /* MUST be first */ 318 unsigned int cntxt_id; /* SGE context id for the eq */ 319 bus_dma_tag_t desc_tag; 320 bus_dmamap_t desc_map; 321 char lockname[16]; 322 struct mtx eq_lock; 323 324 struct tx_desc *desc; /* KVA of descriptor ring */ 325 bus_addr_t ba; /* bus address of descriptor ring */ 326 struct sge_qstat *spg; /* status page, for convenience */ 327 uint16_t cap; /* max # of desc, for convenience */ 328 uint16_t avail; /* available descriptors, for convenience */ 329 uint16_t qsize; /* size (# of entries) of the queue */ 330 uint16_t cidx; /* consumer idx (desc idx) */ 331 uint16_t pidx; /* producer idx (desc idx) */ 332 uint16_t pending; /* # of descriptors used since last doorbell */ 333 uint16_t iqid; /* iq that gets egr_update for the eq */ 334 uint8_t tx_chan; /* tx channel used by the eq */ 335 struct task tx_task; 336 struct callout tx_callout; 337 338 /* stats */ 339 340 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 341 uint32_t unstalled; /* recovered from stall */ 342 }; 343 344 enum { 345 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 346 FL_DOOMED = (1 << 1), /* about to be destroyed */ 347 }; 348 349 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 350 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 351 352 struct sge_fl { 353 bus_dma_tag_t desc_tag; 354 bus_dmamap_t desc_map; 355 bus_dma_tag_t tag[FL_BUF_SIZES]; 356 uint8_t tag_idx; 357 struct mtx fl_lock; 358 char lockname[16]; 359 int flags; 360 361 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 362 bus_addr_t ba; /* bus address of descriptor ring */ 363 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 364 uint32_t cap; /* max # of buffers, for convenience */ 365 uint16_t qsize; /* size (# of entries) of the queue */ 366 uint16_t cntxt_id; /* SGE context id for the freelist */ 367 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 368 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 369 uint32_t needed; /* # of buffers needed to fill up fl. */ 370 uint32_t lowat; /* # of buffers <= this means fl needs help */ 371 uint32_t pending; /* # of bufs allocated since last doorbell */ 372 unsigned int dmamap_failed; 373 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 374 }; 375 376 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 377 struct sge_txq { 378 struct sge_eq eq; /* MUST be first */ 379 380 struct ifnet *ifp; /* the interface this txq belongs to */ 381 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 382 struct buf_ring *br; /* tx buffer ring */ 383 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 384 struct mbuf *m; /* held up due to temporary resource shortage */ 385 386 struct tx_maps txmaps; 387 388 /* stats for common events first */ 389 390 uint64_t txcsum; /* # of times hardware assisted with checksum */ 391 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 392 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 393 uint64_t imm_wrs; /* # of work requests with immediate data */ 394 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 395 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 396 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 397 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 398 399 /* stats for not-that-common events */ 400 401 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 402 uint32_t no_desc; /* out of hardware descriptors */ 403 } __aligned(CACHE_LINE_SIZE); 404 405 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 406 struct sge_rxq { 407 struct sge_iq iq; /* MUST be first */ 408 struct sge_fl fl; /* MUST follow iq */ 409 410 struct ifnet *ifp; /* the interface this rxq belongs to */ 411 #ifdef INET 412 struct lro_ctrl lro; /* LRO state */ 413 #endif 414 415 /* stats for common events first */ 416 417 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 418 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 419 420 /* stats for not-that-common events */ 421 422 } __aligned(CACHE_LINE_SIZE); 423 424 #ifndef TCP_OFFLOAD_DISABLE 425 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 426 struct sge_ofld_rxq { 427 struct sge_iq iq; /* MUST be first */ 428 struct sge_fl fl; /* MUST follow iq */ 429 } __aligned(CACHE_LINE_SIZE); 430 #endif 431 432 /* 433 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 434 * and offload tx queues are of this type. 435 */ 436 struct sge_wrq { 437 struct sge_eq eq; /* MUST be first */ 438 439 struct adapter *adapter; 440 struct mbuf *head; /* held up due to lack of descriptors */ 441 struct mbuf *tail; /* valid only if head is valid */ 442 443 /* stats for common events first */ 444 445 uint64_t tx_wrs; /* # of tx work requests */ 446 447 /* stats for not-that-common events */ 448 449 uint32_t no_desc; /* out of hardware descriptors */ 450 } __aligned(CACHE_LINE_SIZE); 451 452 struct sge { 453 int timer_val[SGE_NTIMERS]; 454 int counter_val[SGE_NCOUNTERS]; 455 int fl_starve_threshold; 456 457 int nrxq; /* total # of Ethernet rx queues */ 458 int ntxq; /* total # of Ethernet tx tx queues */ 459 #ifndef TCP_OFFLOAD_DISABLE 460 int nofldrxq; /* total # of TOE rx queues */ 461 int nofldtxq; /* total # of TOE tx queues */ 462 #endif 463 int niq; /* total # of ingress queues */ 464 int neq; /* total # of egress queues */ 465 466 struct sge_iq fwq; /* Firmware event queue */ 467 struct sge_wrq mgmtq; /* Management queue (control queue) */ 468 struct sge_wrq *ctrlq; /* Control queues */ 469 struct sge_txq *txq; /* NIC tx queues */ 470 struct sge_rxq *rxq; /* NIC rx queues */ 471 #ifndef TCP_OFFLOAD_DISABLE 472 struct sge_wrq *ofld_txq; /* TOE tx queues */ 473 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 474 #endif 475 476 uint16_t iq_start; 477 int eq_start; 478 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 479 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 480 }; 481 482 struct rss_header; 483 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 484 struct mbuf *); 485 486 struct adapter { 487 SLIST_ENTRY(adapter) link; 488 device_t dev; 489 struct cdev *cdev; 490 491 /* PCIe register resources */ 492 int regs_rid; 493 struct resource *regs_res; 494 int msix_rid; 495 struct resource *msix_res; 496 bus_space_handle_t bh; 497 bus_space_tag_t bt; 498 bus_size_t mmio_len; 499 500 unsigned int pf; 501 unsigned int mbox; 502 503 /* Interrupt information */ 504 int intr_type; 505 int intr_count; 506 struct irq { 507 struct resource *res; 508 int rid; 509 void *tag; 510 } *irq; 511 512 bus_dma_tag_t dmat; /* Parent DMA tag */ 513 514 struct sge sge; 515 516 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 517 struct port_info *port[MAX_NPORTS]; 518 uint8_t chan_map[NCHAN]; 519 uint32_t filter_mode; 520 521 #ifndef TCP_OFFLOAD_DISABLE 522 struct uld_softc tom; 523 struct tom_tunables tt; 524 #endif 525 struct l2t_data *l2t; /* L2 table */ 526 struct tid_info tids; 527 528 int open_device_map; 529 #ifndef TCP_OFFLOAD_DISABLE 530 int offload_map; 531 #endif 532 int flags; 533 534 char fw_version[32]; 535 unsigned int cfcsum; 536 struct adapter_params params; 537 struct t4_virt_res vres; 538 539 uint16_t linkcaps; 540 uint16_t niccaps; 541 uint16_t toecaps; 542 uint16_t rdmacaps; 543 uint16_t iscsicaps; 544 uint16_t fcoecaps; 545 546 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 547 548 struct mtx sc_lock; 549 char lockname[16]; 550 551 /* Starving free lists */ 552 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 553 TAILQ_HEAD(, sge_fl) sfl; 554 struct callout sfl_callout; 555 556 cpl_handler_t cpl_handler[256] __aligned(CACHE_LINE_SIZE); 557 }; 558 559 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 560 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 561 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 562 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 563 564 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 565 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 566 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 567 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 568 569 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 570 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 571 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 572 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 573 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 574 575 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 576 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 577 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 578 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 579 580 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 581 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 582 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 583 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 584 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 585 586 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 587 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 588 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 589 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 590 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 591 592 #define for_each_txq(pi, iter, txq) \ 593 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 594 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 595 #define for_each_rxq(pi, iter, rxq) \ 596 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 597 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 598 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 599 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 600 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 601 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 602 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 603 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 604 605 /* One for errors, one for firmware events */ 606 #define T4_EXTRA_INTR 2 607 608 static inline uint32_t 609 t4_read_reg(struct adapter *sc, uint32_t reg) 610 { 611 return bus_space_read_4(sc->bt, sc->bh, reg); 612 } 613 614 static inline void 615 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 616 { 617 bus_space_write_4(sc->bt, sc->bh, reg, val); 618 } 619 620 static inline uint64_t 621 t4_read_reg64(struct adapter *sc, uint32_t reg) 622 { 623 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 624 } 625 626 static inline void 627 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 628 { 629 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 630 } 631 632 static inline void 633 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 634 { 635 *val = pci_read_config(sc->dev, reg, 1); 636 } 637 638 static inline void 639 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 640 { 641 pci_write_config(sc->dev, reg, val, 1); 642 } 643 644 static inline void 645 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 646 { 647 *val = pci_read_config(sc->dev, reg, 2); 648 } 649 650 static inline void 651 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 652 { 653 pci_write_config(sc->dev, reg, val, 2); 654 } 655 656 static inline void 657 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 658 { 659 *val = pci_read_config(sc->dev, reg, 4); 660 } 661 662 static inline void 663 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 664 { 665 pci_write_config(sc->dev, reg, val, 4); 666 } 667 668 static inline struct port_info * 669 adap2pinfo(struct adapter *sc, int idx) 670 { 671 return (sc->port[idx]); 672 } 673 674 static inline void 675 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 676 { 677 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 678 } 679 680 static inline bool is_10G_port(const struct port_info *pi) 681 { 682 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 683 } 684 685 static inline int tx_resume_threshold(struct sge_eq *eq) 686 { 687 return (eq->qsize / 4); 688 } 689 690 /* t4_main.c */ 691 void t4_tx_task(void *, int); 692 void t4_tx_callout(void *); 693 int t4_os_find_pci_capability(struct adapter *, int); 694 int t4_os_pci_save_state(struct adapter *); 695 int t4_os_pci_restore_state(struct adapter *); 696 void t4_os_portmod_changed(const struct adapter *, int); 697 void t4_os_link_changed(struct adapter *, int, int); 698 void t4_iterate(void (*)(struct adapter *, void *), void *); 699 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 700 701 /* t4_sge.c */ 702 void t4_sge_modload(void); 703 int t4_sge_init(struct adapter *); 704 int t4_create_dma_tag(struct adapter *); 705 int t4_destroy_dma_tag(struct adapter *); 706 int t4_setup_adapter_queues(struct adapter *); 707 int t4_teardown_adapter_queues(struct adapter *); 708 int t4_setup_port_queues(struct port_info *); 709 int t4_teardown_port_queues(struct port_info *); 710 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 711 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 712 void t4_intr_all(void *); 713 void t4_intr(void *); 714 void t4_intr_err(void *); 715 void t4_intr_evt(void *); 716 int t4_mgmt_tx(struct adapter *, struct mbuf *); 717 int t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct mbuf *); 718 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 719 void t4_update_fl_bufsize(struct ifnet *); 720 int can_resume_tx(struct sge_eq *); 721 722 static inline int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, struct mbuf *m) 723 { 724 int rc; 725 726 TXQ_LOCK(wrq); 727 rc = t4_wrq_tx_locked(sc, wrq, m); 728 TXQ_UNLOCK(wrq); 729 return (rc); 730 } 731 732 733 #endif 734