1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "t4_ioctl.h" 58 #include "common/t4_msg.h" 59 #include "firmware/t4fw_interface.h" 60 61 #define KTR_CXGBE KTR_SPARE3 62 MALLOC_DECLARE(M_CXGBE); 63 #define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66 #if defined(__i386__) || defined(__amd64__) 67 static __inline void 68 prefetch(void *x) 69 { 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71 } 72 #else 73 #define prefetch(x) 74 #endif 75 76 #ifndef SYSCTL_ADD_UQUAD 77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78 #define sysctl_handle_64 sysctl_handle_quad 79 #define CTLTYPE_U64 CTLTYPE_QUAD 80 #endif 81 82 #if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84 #define SBUF_DRAIN 1 85 #endif 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 128, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 120 }; 121 122 enum { 123 /* adapter intr_type */ 124 INTR_INTX = (1 << 0), 125 INTR_MSI = (1 << 1), 126 INTR_MSIX = (1 << 2) 127 }; 128 129 enum { 130 XGMAC_MTU = (1 << 0), 131 XGMAC_PROMISC = (1 << 1), 132 XGMAC_ALLMULTI = (1 << 2), 133 XGMAC_VLANEX = (1 << 3), 134 XGMAC_UCADDR = (1 << 4), 135 XGMAC_MCADDRS = (1 << 5), 136 137 XGMAC_ALL = 0xffff 138 }; 139 140 enum { 141 /* flags understood by begin_synchronized_op */ 142 HOLD_LOCK = (1 << 0), 143 SLEEP_OK = (1 << 1), 144 INTR_OK = (1 << 2), 145 146 /* flags understood by end_synchronized_op */ 147 LOCK_HELD = HOLD_LOCK, 148 }; 149 150 enum { 151 /* adapter flags */ 152 FULL_INIT_DONE = (1 << 0), 153 FW_OK = (1 << 1), 154 /* INTR_DIRECT = (1 << 2), No longer used. */ 155 MASTER_PF = (1 << 3), 156 ADAP_SYSCTL_CTX = (1 << 4), 157 /* TOM_INIT_DONE= (1 << 5), No longer used */ 158 BUF_PACKING_OK = (1 << 6), 159 IS_VF = (1 << 7), 160 161 CXGBE_BUSY = (1 << 9), 162 163 /* port flags */ 164 HAS_TRACEQ = (1 << 3), 165 166 /* VI flags */ 167 DOOMED = (1 << 0), 168 VI_INIT_DONE = (1 << 1), 169 VI_SYSCTL_CTX = (1 << 2), 170 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 171 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 172 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 173 174 /* adapter debug_flags */ 175 DF_DUMP_MBOX = (1 << 0), 176 }; 177 178 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 179 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 180 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 181 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 182 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 183 184 struct vi_info { 185 device_t dev; 186 struct port_info *pi; 187 188 struct ifnet *ifp; 189 struct ifmedia media; 190 191 unsigned long flags; 192 int if_flags; 193 194 uint16_t *rss, *nm_rss; 195 int smt_idx; /* for convenience */ 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint16_t rss_base; /* start of VI's RSS table slice */ 200 201 eventhandler_tag vlan_c; 202 203 int nintr; 204 int first_intr; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 int nnmtxq; 217 int first_nm_txq; 218 int nnmrxq; 219 int first_nm_rxq; 220 int tmr_idx; 221 int pktc_idx; 222 int qsize_rxq; 223 int qsize_txq; 224 225 struct timeval last_refreshed; 226 struct fw_vi_stats_vf stats; 227 228 struct callout tick; 229 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 230 231 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 232 }; 233 234 enum { 235 /* tx_sched_class flags */ 236 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */ 237 }; 238 239 struct tx_sched_class { 240 int refcount; 241 int flags; 242 struct t4_sched_class_params params; 243 }; 244 245 struct port_info { 246 device_t dev; 247 struct adapter *adapter; 248 249 struct vi_info *vi; 250 int nvi; 251 int up_vis; 252 int uld_vis; 253 254 struct tx_sched_class *tc; /* traffic classes for this channel */ 255 256 struct mtx pi_lock; 257 char lockname[16]; 258 unsigned long flags; 259 260 uint8_t lport; /* associated offload logical port */ 261 int8_t mdio_addr; 262 uint8_t port_type; 263 uint8_t mod_type; 264 uint8_t port_id; 265 uint8_t tx_chan; 266 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 267 268 struct link_config link_cfg; 269 270 struct timeval last_refreshed; 271 struct port_stats stats; 272 u_int tnl_cong_drops; 273 u_int tx_parse_error; 274 275 struct callout tick; 276 }; 277 278 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 279 280 /* Where the cluster came from, how it has been carved up. */ 281 struct cluster_layout { 282 int8_t zidx; 283 int8_t hwidx; 284 uint16_t region1; /* mbufs laid out within this region */ 285 /* region2 is the DMA region */ 286 uint16_t region3; /* cluster_metadata within this region */ 287 }; 288 289 struct cluster_metadata { 290 u_int refcount; 291 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 292 }; 293 294 struct fl_sdesc { 295 caddr_t cl; 296 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 297 struct cluster_layout cll; 298 }; 299 300 struct tx_desc { 301 __be64 flit[8]; 302 }; 303 304 struct tx_sdesc { 305 struct mbuf *m; /* m_nextpkt linked chain of frames */ 306 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 307 }; 308 309 310 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 311 struct iq_desc { 312 struct rss_header rss; 313 uint8_t cpl[IQ_PAD]; 314 struct rsp_ctrl rsp; 315 }; 316 #undef IQ_PAD 317 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 318 319 enum { 320 /* iq flags */ 321 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 322 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 323 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 324 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 325 326 /* iq state */ 327 IQS_DISABLED = 0, 328 IQS_BUSY = 1, 329 IQS_IDLE = 2, 330 331 /* netmap related flags */ 332 NM_OFF = 0, 333 NM_ON = 1, 334 NM_BUSY = 2, 335 }; 336 337 struct sge_iq; 338 struct rss_header; 339 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 340 struct mbuf *); 341 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 342 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 343 344 /* 345 * Ingress Queue: T4 is producer, driver is consumer. 346 */ 347 struct sge_iq { 348 uint32_t flags; 349 volatile int state; 350 struct adapter *adapter; 351 cpl_handler_t set_tcb_rpl; 352 cpl_handler_t l2t_write_rpl; 353 struct iq_desc *desc; /* KVA of descriptor ring */ 354 int8_t intr_pktc_idx; /* packet count threshold index */ 355 uint8_t gen; /* generation bit */ 356 uint8_t intr_params; /* interrupt holdoff parameters */ 357 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 358 uint16_t qsize; /* size (# of entries) of the queue */ 359 uint16_t sidx; /* index of the entry with the status page */ 360 uint16_t cidx; /* consumer index */ 361 uint16_t cntxt_id; /* SGE context id for the iq */ 362 uint16_t abs_id; /* absolute SGE id for the iq */ 363 364 STAILQ_ENTRY(sge_iq) link; 365 366 bus_dma_tag_t desc_tag; 367 bus_dmamap_t desc_map; 368 bus_addr_t ba; /* bus address of descriptor ring */ 369 }; 370 371 enum { 372 EQ_CTRL = 1, 373 EQ_ETH = 2, 374 EQ_OFLD = 3, 375 376 /* eq flags */ 377 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 378 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 379 EQ_ENABLED = (1 << 3), /* open for business */ 380 }; 381 382 /* Listed in order of preference. Update t4_sysctls too if you change these */ 383 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 384 385 /* 386 * Egress Queue: driver is producer, T4 is consumer. 387 * 388 * Note: A free list is an egress queue (driver produces the buffers and T4 389 * consumes them) but it's special enough to have its own struct (see sge_fl). 390 */ 391 struct sge_eq { 392 unsigned int flags; /* MUST be first */ 393 unsigned int cntxt_id; /* SGE context id for the eq */ 394 unsigned int abs_id; /* absolute SGE id for the eq */ 395 struct mtx eq_lock; 396 397 struct tx_desc *desc; /* KVA of descriptor ring */ 398 uint16_t doorbells; 399 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 400 u_int udb_qid; /* relative qid within the doorbell page */ 401 uint16_t sidx; /* index of the entry with the status page */ 402 uint16_t cidx; /* consumer idx (desc idx) */ 403 uint16_t pidx; /* producer idx (desc idx) */ 404 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 405 uint16_t dbidx; /* pidx of the most recent doorbell */ 406 uint16_t iqid; /* iq that gets egr_update for the eq */ 407 uint8_t tx_chan; /* tx channel used by the eq */ 408 volatile u_int equiq; /* EQUIQ outstanding */ 409 410 bus_dma_tag_t desc_tag; 411 bus_dmamap_t desc_map; 412 bus_addr_t ba; /* bus address of descriptor ring */ 413 char lockname[16]; 414 }; 415 416 struct sw_zone_info { 417 uma_zone_t zone; /* zone that this cluster comes from */ 418 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 419 int type; /* EXT_xxx type of the cluster */ 420 int8_t head_hwidx; 421 int8_t tail_hwidx; 422 }; 423 424 struct hw_buf_info { 425 int8_t zidx; /* backpointer to zone; -ve means unused */ 426 int8_t next; /* next hwidx for this zone; -1 means no more */ 427 int size; 428 }; 429 430 enum { 431 NUM_MEMWIN = 3, 432 433 MEMWIN0_APERTURE = 2048, 434 MEMWIN0_BASE = 0x1b800, 435 436 MEMWIN1_APERTURE = 32768, 437 MEMWIN1_BASE = 0x28000, 438 439 MEMWIN2_APERTURE_T4 = 65536, 440 MEMWIN2_BASE_T4 = 0x30000, 441 442 MEMWIN2_APERTURE_T5 = 128 * 1024, 443 MEMWIN2_BASE_T5 = 0x60000, 444 }; 445 446 struct memwin { 447 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 448 uint32_t mw_base; /* constant after setup_memwin */ 449 uint32_t mw_aperture; /* ditto */ 450 uint32_t mw_curpos; /* protected by mw_lock */ 451 }; 452 453 enum { 454 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 455 FL_DOOMED = (1 << 1), /* about to be destroyed */ 456 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 457 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 458 }; 459 460 #define FL_RUNNING_LOW(fl) \ 461 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 462 #define FL_NOT_RUNNING_LOW(fl) \ 463 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 464 465 struct sge_fl { 466 struct mtx fl_lock; 467 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 468 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 469 struct cluster_layout cll_def; /* default refill zone, layout */ 470 uint16_t lowat; /* # of buffers <= this means fl needs help */ 471 int flags; 472 uint16_t buf_boundary; 473 474 /* The 16b idx all deal with hw descriptors */ 475 uint16_t dbidx; /* hw pidx after last doorbell */ 476 uint16_t sidx; /* index of status page */ 477 volatile uint16_t hw_cidx; 478 479 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 480 uint32_t cidx; /* consumer index */ 481 uint32_t pidx; /* producer index */ 482 483 uint32_t dbval; 484 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 485 volatile uint32_t *udb; 486 487 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 488 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 489 uint64_t cl_allocated; /* # of clusters allocated */ 490 uint64_t cl_recycled; /* # of clusters recycled */ 491 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 492 493 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 494 struct mbuf *m0; 495 struct mbuf **pnext; 496 u_int remaining; 497 498 uint16_t qsize; /* # of hw descriptors (status page included) */ 499 uint16_t cntxt_id; /* SGE context id for the freelist */ 500 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 501 bus_dma_tag_t desc_tag; 502 bus_dmamap_t desc_map; 503 char lockname[16]; 504 bus_addr_t ba; /* bus address of descriptor ring */ 505 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 506 }; 507 508 struct mp_ring; 509 510 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 511 struct sge_txq { 512 struct sge_eq eq; /* MUST be first */ 513 514 struct ifnet *ifp; /* the interface this txq belongs to */ 515 struct mp_ring *r; /* tx software ring */ 516 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 517 struct sglist *gl; 518 __be32 cpl_ctrl0; /* for convenience */ 519 int tc_idx; /* traffic class */ 520 521 struct task tx_reclaim_task; 522 /* stats for common events first */ 523 524 uint64_t txcsum; /* # of times hardware assisted with checksum */ 525 uint64_t tso_wrs; /* # of TSO work requests */ 526 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 527 uint64_t imm_wrs; /* # of work requests with immediate data */ 528 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 529 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 530 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 531 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 532 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 533 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 534 535 /* stats for not-that-common events */ 536 } __aligned(CACHE_LINE_SIZE); 537 538 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 539 struct sge_rxq { 540 struct sge_iq iq; /* MUST be first */ 541 struct sge_fl fl; /* MUST follow iq */ 542 543 struct ifnet *ifp; /* the interface this rxq belongs to */ 544 #if defined(INET) || defined(INET6) 545 struct lro_ctrl lro; /* LRO state */ 546 #endif 547 548 /* stats for common events first */ 549 550 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 551 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 552 553 /* stats for not-that-common events */ 554 555 } __aligned(CACHE_LINE_SIZE); 556 557 static inline struct sge_rxq * 558 iq_to_rxq(struct sge_iq *iq) 559 { 560 561 return (__containerof(iq, struct sge_rxq, iq)); 562 } 563 564 565 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 566 struct sge_ofld_rxq { 567 struct sge_iq iq; /* MUST be first */ 568 struct sge_fl fl; /* MUST follow iq */ 569 } __aligned(CACHE_LINE_SIZE); 570 571 static inline struct sge_ofld_rxq * 572 iq_to_ofld_rxq(struct sge_iq *iq) 573 { 574 575 return (__containerof(iq, struct sge_ofld_rxq, iq)); 576 } 577 578 struct wrqe { 579 STAILQ_ENTRY(wrqe) link; 580 struct sge_wrq *wrq; 581 int wr_len; 582 char wr[] __aligned(16); 583 }; 584 585 struct wrq_cookie { 586 TAILQ_ENTRY(wrq_cookie) link; 587 int ndesc; 588 int pidx; 589 }; 590 591 /* 592 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 593 * and offload tx queues are of this type. 594 */ 595 struct sge_wrq { 596 struct sge_eq eq; /* MUST be first */ 597 598 struct adapter *adapter; 599 struct task wrq_tx_task; 600 601 /* Tx desc reserved but WR not "committed" yet. */ 602 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 603 604 /* List of WRs ready to go out as soon as descriptors are available. */ 605 STAILQ_HEAD(, wrqe) wr_list; 606 u_int nwr_pending; 607 u_int ndesc_needed; 608 609 /* stats for common events first */ 610 611 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 612 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 613 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 614 615 /* stats for not-that-common events */ 616 617 /* 618 * Scratch space for work requests that wrap around after reaching the 619 * status page, and some information about the last WR that used it. 620 */ 621 uint16_t ss_pidx; 622 uint16_t ss_len; 623 uint8_t ss[SGE_MAX_WR_LEN]; 624 625 } __aligned(CACHE_LINE_SIZE); 626 627 628 struct sge_nm_rxq { 629 struct vi_info *vi; 630 631 struct iq_desc *iq_desc; 632 uint16_t iq_abs_id; 633 uint16_t iq_cntxt_id; 634 uint16_t iq_cidx; 635 uint16_t iq_sidx; 636 uint8_t iq_gen; 637 638 __be64 *fl_desc; 639 uint16_t fl_cntxt_id; 640 uint32_t fl_cidx; 641 uint32_t fl_pidx; 642 uint32_t fl_sidx; 643 uint32_t fl_db_val; 644 u_int fl_hwidx:4; 645 646 u_int nid; /* netmap ring # for this queue */ 647 648 /* infrequently used items after this */ 649 650 bus_dma_tag_t iq_desc_tag; 651 bus_dmamap_t iq_desc_map; 652 bus_addr_t iq_ba; 653 int intr_idx; 654 655 bus_dma_tag_t fl_desc_tag; 656 bus_dmamap_t fl_desc_map; 657 bus_addr_t fl_ba; 658 } __aligned(CACHE_LINE_SIZE); 659 660 struct sge_nm_txq { 661 struct tx_desc *desc; 662 uint16_t cidx; 663 uint16_t pidx; 664 uint16_t sidx; 665 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 666 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 667 uint16_t dbidx; /* pidx of the most recent doorbell */ 668 uint16_t doorbells; 669 volatile uint32_t *udb; 670 u_int udb_qid; 671 u_int cntxt_id; 672 __be32 cpl_ctrl0; /* for convenience */ 673 u_int nid; /* netmap ring # for this queue */ 674 675 /* infrequently used items after this */ 676 677 bus_dma_tag_t desc_tag; 678 bus_dmamap_t desc_map; 679 bus_addr_t ba; 680 int iqidx; 681 } __aligned(CACHE_LINE_SIZE); 682 683 struct sge { 684 int nrxq; /* total # of Ethernet rx queues */ 685 int ntxq; /* total # of Ethernet tx tx queues */ 686 int nofldrxq; /* total # of TOE rx queues */ 687 int nofldtxq; /* total # of TOE tx queues */ 688 int nnmrxq; /* total # of netmap rx queues */ 689 int nnmtxq; /* total # of netmap tx queues */ 690 int niq; /* total # of ingress queues */ 691 int neq; /* total # of egress queues */ 692 693 struct sge_iq fwq; /* Firmware event queue */ 694 struct sge_wrq mgmtq; /* Management queue (control queue) */ 695 struct sge_wrq *ctrlq; /* Control queues */ 696 struct sge_txq *txq; /* NIC tx queues */ 697 struct sge_rxq *rxq; /* NIC rx queues */ 698 struct sge_wrq *ofld_txq; /* TOE tx queues */ 699 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 700 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 701 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 702 703 uint16_t iq_start; /* first cntxt_id */ 704 uint16_t iq_base; /* first abs_id */ 705 int eq_start; /* first cntxt_id */ 706 int eq_base; /* first abs_id */ 707 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 708 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 709 710 int8_t safe_hwidx1; /* may not have room for metadata */ 711 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 712 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 713 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 714 }; 715 716 struct devnames { 717 const char *nexus_name; 718 const char *ifnet_name; 719 const char *vi_ifnet_name; 720 const char *pf03_drv_name; 721 const char *vf_nexus_name; 722 const char *vf_ifnet_name; 723 }; 724 725 struct adapter { 726 SLIST_ENTRY(adapter) link; 727 device_t dev; 728 struct cdev *cdev; 729 const struct devnames *names; 730 731 /* PCIe register resources */ 732 int regs_rid; 733 struct resource *regs_res; 734 int msix_rid; 735 struct resource *msix_res; 736 bus_space_handle_t bh; 737 bus_space_tag_t bt; 738 bus_size_t mmio_len; 739 int udbs_rid; 740 struct resource *udbs_res; 741 volatile uint8_t *udbs_base; 742 743 unsigned int pf; 744 unsigned int mbox; 745 unsigned int vpd_busy; 746 unsigned int vpd_flag; 747 748 /* Interrupt information */ 749 int intr_type; 750 int intr_count; 751 struct irq { 752 struct resource *res; 753 int rid; 754 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 755 void *tag; 756 struct sge_rxq *rxq; 757 struct sge_nm_rxq *nm_rxq; 758 } __aligned(CACHE_LINE_SIZE) *irq; 759 int sge_gts_reg; 760 int sge_kdoorbell_reg; 761 762 bus_dma_tag_t dmat; /* Parent DMA tag */ 763 764 struct sge sge; 765 int lro_timeout; 766 int sc_do_rxcopy; 767 768 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 769 struct port_info *port[MAX_NPORTS]; 770 uint8_t chan_map[MAX_NCHAN]; 771 772 void *tom_softc; /* (struct tom_data *) */ 773 struct tom_tunables tt; 774 void *iwarp_softc; /* (struct c4iw_dev *) */ 775 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 776 struct l2t_data *l2t; /* L2 table */ 777 struct tid_info tids; 778 779 uint16_t doorbells; 780 int offload_map; /* ports with IFCAP_TOE enabled */ 781 int active_ulds; /* ULDs activated on this adapter */ 782 int flags; 783 int debug_flags; 784 785 char ifp_lockname[16]; 786 struct mtx ifp_lock; 787 struct ifnet *ifp; /* tracer ifp */ 788 struct ifmedia media; 789 int traceq; /* iq used by all tracers, -1 if none */ 790 int tracer_valid; /* bitmap of valid tracers */ 791 int tracer_enabled; /* bitmap of enabled tracers */ 792 793 char fw_version[16]; 794 char tp_version[16]; 795 char er_version[16]; 796 char bs_version[16]; 797 char cfg_file[32]; 798 u_int cfcsum; 799 struct adapter_params params; 800 const struct chip_params *chip_params; 801 struct t4_virt_res vres; 802 803 uint16_t nbmcaps; 804 uint16_t linkcaps; 805 uint16_t switchcaps; 806 uint16_t niccaps; 807 uint16_t toecaps; 808 uint16_t rdmacaps; 809 uint16_t cryptocaps; 810 uint16_t iscsicaps; 811 uint16_t fcoecaps; 812 813 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 814 815 struct mtx sc_lock; 816 char lockname[16]; 817 818 /* Starving free lists */ 819 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 820 TAILQ_HEAD(, sge_fl) sfl; 821 struct callout sfl_callout; 822 823 struct mtx reg_lock; /* for indirect register access */ 824 825 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 826 827 const char *last_op; 828 const void *last_op_thr; 829 int last_op_flags; 830 }; 831 832 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 833 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 834 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 835 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 836 837 #define ASSERT_SYNCHRONIZED_OP(sc) \ 838 KASSERT(IS_BUSY(sc) && \ 839 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 840 ("%s: operation not synchronized.", __func__)) 841 842 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 843 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 844 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 845 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 846 847 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 848 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 849 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 850 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 851 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 852 853 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 854 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 855 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 856 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 857 858 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 859 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 860 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 861 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 862 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 863 864 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 865 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 866 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 867 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 868 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 869 870 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 871 do { \ 872 if (sc->debug_flags & DF_DUMP_MBOX) { \ 873 log(LOG_NOTICE, \ 874 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 875 "%016llx %016llx %016llx %016llx\n", \ 876 device_get_nameunit(sc->dev), mbox, \ 877 (unsigned long long)t4_read_reg64(sc, data_reg), \ 878 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 879 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 880 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 881 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 882 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 883 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 884 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 885 } \ 886 } while (0) 887 888 #define for_each_txq(vi, iter, q) \ 889 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 890 iter < vi->ntxq; ++iter, ++q) 891 #define for_each_rxq(vi, iter, q) \ 892 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 893 iter < vi->nrxq; ++iter, ++q) 894 #define for_each_ofld_txq(vi, iter, q) \ 895 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 896 iter < vi->nofldtxq; ++iter, ++q) 897 #define for_each_ofld_rxq(vi, iter, q) \ 898 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 899 iter < vi->nofldrxq; ++iter, ++q) 900 #define for_each_nm_txq(vi, iter, q) \ 901 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 902 iter < vi->nnmtxq; ++iter, ++q) 903 #define for_each_nm_rxq(vi, iter, q) \ 904 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 905 iter < vi->nnmrxq; ++iter, ++q) 906 #define for_each_vi(_pi, _iter, _vi) \ 907 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 908 ++(_iter), ++(_vi)) 909 910 #define IDXINCR(idx, incr, wrap) do { \ 911 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 912 } while (0) 913 #define IDXDIFF(head, tail, wrap) \ 914 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 915 916 /* One for errors, one for firmware events */ 917 #define T4_EXTRA_INTR 2 918 919 /* One for firmware events */ 920 #define T4VF_EXTRA_INTR 1 921 922 static inline uint32_t 923 t4_read_reg(struct adapter *sc, uint32_t reg) 924 { 925 926 return bus_space_read_4(sc->bt, sc->bh, reg); 927 } 928 929 static inline void 930 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 931 { 932 933 bus_space_write_4(sc->bt, sc->bh, reg, val); 934 } 935 936 static inline uint64_t 937 t4_read_reg64(struct adapter *sc, uint32_t reg) 938 { 939 940 #ifdef __LP64__ 941 return bus_space_read_8(sc->bt, sc->bh, reg); 942 #else 943 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 944 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 945 946 #endif 947 } 948 949 static inline void 950 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 951 { 952 953 #ifdef __LP64__ 954 bus_space_write_8(sc->bt, sc->bh, reg, val); 955 #else 956 bus_space_write_4(sc->bt, sc->bh, reg, val); 957 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 958 #endif 959 } 960 961 static inline void 962 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 963 { 964 965 *val = pci_read_config(sc->dev, reg, 1); 966 } 967 968 static inline void 969 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 970 { 971 972 pci_write_config(sc->dev, reg, val, 1); 973 } 974 975 static inline void 976 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 977 { 978 979 *val = pci_read_config(sc->dev, reg, 2); 980 } 981 982 static inline void 983 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 984 { 985 986 pci_write_config(sc->dev, reg, val, 2); 987 } 988 989 static inline void 990 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 991 { 992 993 *val = pci_read_config(sc->dev, reg, 4); 994 } 995 996 static inline void 997 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 998 { 999 1000 pci_write_config(sc->dev, reg, val, 4); 1001 } 1002 1003 static inline struct port_info * 1004 adap2pinfo(struct adapter *sc, int idx) 1005 { 1006 1007 return (sc->port[idx]); 1008 } 1009 1010 static inline void 1011 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1012 { 1013 1014 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1015 } 1016 1017 static inline bool 1018 is_10G_port(const struct port_info *pi) 1019 { 1020 1021 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1022 } 1023 1024 static inline bool 1025 is_25G_port(const struct port_info *pi) 1026 { 1027 1028 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1029 } 1030 1031 static inline bool 1032 is_40G_port(const struct port_info *pi) 1033 { 1034 1035 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1036 } 1037 1038 static inline bool 1039 is_100G_port(const struct port_info *pi) 1040 { 1041 1042 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1043 } 1044 1045 static inline int 1046 port_top_speed(const struct port_info *pi) 1047 { 1048 1049 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1050 return (100); 1051 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1052 return (40); 1053 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1054 return (25); 1055 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1056 return (10); 1057 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1058 return (1); 1059 1060 return (0); 1061 } 1062 1063 static inline int 1064 tx_resume_threshold(struct sge_eq *eq) 1065 { 1066 1067 /* not quite the same as qsize / 4, but this will do. */ 1068 return (eq->sidx / 4); 1069 } 1070 1071 static inline int 1072 t4_use_ldst(struct adapter *sc) 1073 { 1074 1075 #ifdef notyet 1076 return (sc->flags & FW_OK || !sc->use_bd); 1077 #else 1078 return (0); 1079 #endif 1080 } 1081 1082 /* t4_main.c */ 1083 extern int t4_ntxq10g; 1084 extern int t4_nrxq10g; 1085 extern int t4_ntxq1g; 1086 extern int t4_nrxq1g; 1087 extern int t4_intr_types; 1088 extern int t4_tmr_idx_10g; 1089 extern int t4_pktc_idx_10g; 1090 extern int t4_tmr_idx_1g; 1091 extern int t4_pktc_idx_1g; 1092 extern unsigned int t4_qsize_rxq; 1093 extern unsigned int t4_qsize_txq; 1094 extern device_method_t cxgbe_methods[]; 1095 1096 int t4_os_find_pci_capability(struct adapter *, int); 1097 int t4_os_pci_save_state(struct adapter *); 1098 int t4_os_pci_restore_state(struct adapter *); 1099 void t4_os_portmod_changed(const struct adapter *, int); 1100 void t4_os_link_changed(struct adapter *, int, int); 1101 void t4_iterate(void (*)(struct adapter *, void *), void *); 1102 void t4_init_devnames(struct adapter *); 1103 void t4_add_adapter(struct adapter *); 1104 int t4_detach_common(device_t); 1105 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1106 int t4_map_bars_0_and_4(struct adapter *); 1107 int t4_map_bar_2(struct adapter *); 1108 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1109 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1110 int t4_setup_intr_handlers(struct adapter *); 1111 void t4_sysctls(struct adapter *); 1112 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1113 void doom_vi(struct adapter *, struct vi_info *); 1114 void end_synchronized_op(struct adapter *, int); 1115 int update_mac_settings(struct ifnet *, int); 1116 int adapter_full_init(struct adapter *); 1117 int adapter_full_uninit(struct adapter *); 1118 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1119 int vi_full_init(struct vi_info *); 1120 int vi_full_uninit(struct vi_info *); 1121 void vi_sysctls(struct vi_info *); 1122 void vi_tick(void *); 1123 1124 #ifdef DEV_NETMAP 1125 /* t4_netmap.c */ 1126 void cxgbe_nm_attach(struct vi_info *); 1127 void cxgbe_nm_detach(struct vi_info *); 1128 void t4_nm_intr(void *); 1129 #endif 1130 1131 /* t4_sge.c */ 1132 void t4_sge_modload(void); 1133 void t4_sge_modunload(void); 1134 uint64_t t4_sge_extfree_refs(void); 1135 void t4_tweak_chip_settings(struct adapter *); 1136 int t4_read_chip_settings(struct adapter *); 1137 int t4_create_dma_tag(struct adapter *); 1138 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1139 struct sysctl_oid_list *); 1140 int t4_destroy_dma_tag(struct adapter *); 1141 int t4_setup_adapter_queues(struct adapter *); 1142 int t4_teardown_adapter_queues(struct adapter *); 1143 int t4_setup_vi_queues(struct vi_info *); 1144 int t4_teardown_vi_queues(struct vi_info *); 1145 void t4_intr_all(void *); 1146 void t4_intr(void *); 1147 void t4_vi_intr(void *); 1148 void t4_intr_err(void *); 1149 void t4_intr_evt(void *); 1150 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1151 void t4_update_fl_bufsize(struct ifnet *); 1152 int parse_pkt(struct adapter *, struct mbuf **); 1153 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1154 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1155 int tnl_cong(struct port_info *, int); 1156 int t4_register_an_handler(an_handler_t); 1157 int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1158 int t4_register_cpl_handler(int, cpl_handler_t); 1159 1160 /* t4_tracer.c */ 1161 struct t4_tracer; 1162 void t4_tracer_modload(void); 1163 void t4_tracer_modunload(void); 1164 void t4_tracer_port_detach(struct adapter *); 1165 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1166 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1167 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1168 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1169 1170 static inline struct wrqe * 1171 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1172 { 1173 int len = offsetof(struct wrqe, wr) + wr_len; 1174 struct wrqe *wr; 1175 1176 wr = malloc(len, M_CXGBE, M_NOWAIT); 1177 if (__predict_false(wr == NULL)) 1178 return (NULL); 1179 wr->wr_len = wr_len; 1180 wr->wrq = wrq; 1181 return (wr); 1182 } 1183 1184 static inline void * 1185 wrtod(struct wrqe *wr) 1186 { 1187 return (&wr->wr[0]); 1188 } 1189 1190 static inline void 1191 free_wrqe(struct wrqe *wr) 1192 { 1193 free(wr, M_CXGBE); 1194 } 1195 1196 static inline void 1197 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1198 { 1199 struct sge_wrq *wrq = wr->wrq; 1200 1201 TXQ_LOCK(wrq); 1202 t4_wrq_tx_locked(sc, wrq, wr); 1203 TXQ_UNLOCK(wrq); 1204 } 1205 1206 #endif 1207