1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2025 Chelsio Communications. 5 * Written by: Navdeep Parhar <np@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __T4_ADAPTER_H__ 31 #define __T4_ADAPTER_H__ 32 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/counter.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/seqc.h> 42 #include <sys/sx.h> 43 #include <sys/vmem.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/taskqueue.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <net/pfil.h> 57 #include <netinet/in.h> 58 #include <netinet/tcp_lro.h> 59 60 #include "offload.h" 61 #include "t4_ioctl.h" 62 #include "common/t4_msg.h" 63 #include "firmware/t4fw_interface.h" 64 65 #define KTR_CXGBE KTR_SPARE3 66 MALLOC_DECLARE(M_CXGBE); 67 #define CXGBE_UNIMPLEMENTED(s) \ 68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 69 70 /* 71 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 72 * LIST_HEAD when building iw_cxgbe. 73 */ 74 #define CXGBE_LIST_HEAD(name, type) \ 75 struct name { \ 76 struct type *lh_first; /* first element */ \ 77 } 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 SYSCTL_DECL(_hw_cxgbe); 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 1024, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_SGL_SEGS_VM = 38, 120 TX_SGL_SEGS_VM_TSO = 37, 121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 122 TX_SGL_SEGS_VXLAN_TSO = 37, 123 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 124 }; 125 126 enum { 127 /* adapter intr_type */ 128 INTR_INTX = (1 << 0), 129 INTR_MSI = (1 << 1), 130 INTR_MSIX = (1 << 2) 131 }; 132 133 enum { 134 XGMAC_MTU = (1 << 0), 135 XGMAC_PROMISC = (1 << 1), 136 XGMAC_ALLMULTI = (1 << 2), 137 XGMAC_VLANEX = (1 << 3), 138 XGMAC_UCADDR = (1 << 4), 139 XGMAC_MCADDRS = (1 << 5), 140 141 XGMAC_ALL = 0xffff 142 }; 143 144 enum { 145 /* flags understood by begin_synchronized_op */ 146 HOLD_LOCK = (1 << 0), 147 SLEEP_OK = (1 << 1), 148 INTR_OK = (1 << 2), 149 150 /* flags understood by end_synchronized_op */ 151 LOCK_HELD = HOLD_LOCK, 152 }; 153 154 enum { 155 /* adapter flags. synch_op or adapter_lock. */ 156 FULL_INIT_DONE = (1 << 0), 157 FW_OK = (1 << 1), 158 CHK_MBOX_ACCESS = (1 << 2), 159 MASTER_PF = (1 << 3), 160 BUF_PACKING_OK = (1 << 6), 161 IS_VF = (1 << 7), 162 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 163 CXGBE_BUSY = (1 << 9), 164 165 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 166 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 167 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 168 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 169 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 170 171 /* port flags */ 172 HAS_TRACEQ = (1 << 3), 173 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 174 175 /* VI flags */ 176 VI_DETACHING = (1 << 0), 177 VI_INIT_DONE = (1 << 1), 178 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 179 TX_USES_VM_WR = (1 << 3), 180 VI_SKIP_STATS = (1 << 4), 181 182 /* adapter debug_flags */ 183 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 184 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 185 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 186 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 187 188 /* adapter intr handler flags */ 189 IHF_INTR_CLEAR_ON_INIT = (1 << 0), /* Driver calls t4_intr_clear */ 190 IHF_NO_SHOW = (1 << 1), /* Do not display intr info */ 191 IHF_VERBOSE = (1 << 2), /* Display extra intr info */ 192 IHF_FATAL_IFF_ENABLED = (1 << 3), /* Fatal only if enabled */ 193 IHF_IGNORE_IF_DISABLED = (1 << 4), /* Ignore if disabled */ 194 IHF_CLR_ALL_SET = (1 << 5), /* Clear all set bits */ 195 IHF_CLR_ALL_UNIGNORED = (1 << 6), /* Clear all unignored bits */ 196 IHF_RUN_ALL_ACTIONS = (1 << 7), /* As if all cause are set */ 197 IHF_CLR_DELAYED = (1 << 9), /* Cleared in a delayed call */ 198 }; 199 200 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING) 201 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0) 202 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0) 203 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 204 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 205 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 206 207 struct vi_info { 208 device_t dev; 209 struct port_info *pi; 210 struct adapter *adapter; 211 212 if_t ifp; 213 struct pfil_head *pfil; 214 215 unsigned long flags; 216 int if_flags; 217 218 uint16_t *rss, *nm_rss; 219 uint16_t viid; /* opaque VI identifier */ 220 uint16_t smt_idx; 221 uint16_t vin; 222 uint8_t vfvld; 223 int16_t xact_addr_filt;/* index of exact MAC address filter */ 224 uint16_t rss_size; /* size of VI's RSS table slice */ 225 uint16_t rss_base; /* start of VI's RSS table slice */ 226 int hashen; 227 228 int nintr; 229 int first_intr; 230 231 /* These need to be int as they are used in sysctl */ 232 int ntxq; /* # of tx queues */ 233 int first_txq; /* index of first tx queue */ 234 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 235 int nrxq; /* # of rx queues */ 236 int first_rxq; /* index of first rx queue */ 237 int nofldtxq; /* # of offload tx queues */ 238 int first_ofld_txq; /* index of first offload tx queue */ 239 int nofldrxq; /* # of offload rx queues */ 240 int first_ofld_rxq; /* index of first offload rx queue */ 241 int nnmtxq; 242 int first_nm_txq; 243 int nnmrxq; 244 int first_nm_rxq; 245 int tmr_idx; 246 int ofld_tmr_idx; 247 int pktc_idx; 248 int ofld_pktc_idx; 249 int qsize_rxq; 250 int qsize_txq; 251 252 struct timeval last_refreshed; 253 struct fw_vi_stats_vf stats; 254 struct mtx tick_mtx; 255 struct callout tick; 256 257 struct sysctl_ctx_list ctx; 258 struct sysctl_oid *rxq_oid; 259 struct sysctl_oid *txq_oid; 260 struct sysctl_oid *nm_rxq_oid; 261 struct sysctl_oid *nm_txq_oid; 262 struct sysctl_oid *ofld_rxq_oid; 263 struct sysctl_oid *ofld_txq_oid; 264 265 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 266 u_int txq_rr; 267 u_int rxq_rr; 268 }; 269 270 struct tx_ch_rl_params { 271 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 272 uint32_t maxrate; 273 }; 274 275 /* CLRL state */ 276 enum clrl_state { 277 CS_UNINITIALIZED = 0, 278 CS_PARAMS_SET, /* sw parameters have been set. */ 279 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 280 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 281 CS_HW_CONFIGURED /* configured in the hardware. */ 282 }; 283 284 /* CLRL flags */ 285 enum { 286 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 287 }; 288 289 struct tx_cl_rl_params { 290 enum clrl_state state; 291 int refcount; 292 uint8_t flags; 293 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 294 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 295 enum fw_sched_params_mode mode; /* aggr or per-flow */ 296 uint32_t maxrate; 297 uint16_t pktsize; 298 uint16_t burstsize; 299 }; 300 301 /* Tx scheduler parameters for a channel/port */ 302 struct tx_sched_params { 303 /* Channel Rate Limiter */ 304 struct tx_ch_rl_params ch_rl; 305 306 /* Class WRR */ 307 /* XXX */ 308 309 /* Class Rate Limiter (including the default pktsize and burstsize). */ 310 int pktsize; 311 int burstsize; 312 struct tx_cl_rl_params cl_rl[]; 313 }; 314 315 struct port_info { 316 device_t dev; 317 struct adapter *adapter; 318 319 struct vi_info *vi; 320 int nvi; 321 int up_vis; 322 int uld_vis; 323 bool vxlan_tcam_entry; 324 325 struct tx_sched_params *sched_params; 326 327 struct mtx pi_lock; 328 char lockname[16]; 329 unsigned long flags; 330 331 uint8_t hw_port; /* associated hardware port idx */ 332 int8_t mdio_addr; 333 uint8_t port_type; 334 uint8_t mod_type; 335 uint8_t port_id; 336 uint8_t tx_chan; /* tx TP c-channel */ 337 uint8_t rx_chan; /* rx TP c-channel */ 338 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 339 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 340 341 struct link_config link_cfg; 342 struct ifmedia media; 343 344 struct port_stats stats; 345 u_int tnl_cong_drops; 346 u_int tx_parse_error; 347 int fcs_reg; 348 uint64_t fcs_base; 349 350 struct sysctl_ctx_list ctx; 351 }; 352 353 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 354 355 struct cluster_metadata { 356 uma_zone_t zone; 357 caddr_t cl; 358 u_int refcount; 359 }; 360 361 struct fl_sdesc { 362 caddr_t cl; 363 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 364 int16_t moff; /* offset of metadata from cl */ 365 uint8_t zidx; 366 }; 367 368 struct tx_desc { 369 __be64 flit[8]; 370 }; 371 372 struct tx_sdesc { 373 struct mbuf *m; /* m_nextpkt linked chain of frames */ 374 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 375 }; 376 377 378 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 379 struct iq_desc { 380 struct rss_header rss; 381 uint8_t cpl[IQ_PAD]; 382 struct rsp_ctrl rsp; 383 }; 384 #undef IQ_PAD 385 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 386 387 enum { 388 /* iq type */ 389 IQ_OTHER = FW_IQ_IQTYPE_OTHER, 390 IQ_ETH = FW_IQ_IQTYPE_NIC, 391 IQ_OFLD = FW_IQ_IQTYPE_OFLD, 392 393 /* iq flags */ 394 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 395 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 396 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 397 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 398 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 399 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 400 401 /* iq state */ 402 IQS_DISABLED = 0, 403 IQS_BUSY = 1, 404 IQS_IDLE = 2, 405 406 /* netmap related flags */ 407 NM_OFF = 0, 408 NM_ON = 1, 409 NM_BUSY = 2, 410 }; 411 412 enum { 413 CPL_COOKIE_RESERVED = 0, 414 CPL_COOKIE_FILTER, 415 CPL_COOKIE_DDP0, 416 CPL_COOKIE_DDP1, 417 CPL_COOKIE_TOM, 418 CPL_COOKIE_HASHFILTER, 419 CPL_COOKIE_ETHOFLD, 420 CPL_COOKIE_KERN_TLS, 421 422 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 423 }; 424 425 /* 426 * Crypto replies use the low bit in the 64-bit cookie of CPL_FW6_PLD as a 427 * CPL cookie to identify the sender/receiver. 428 */ 429 enum { 430 CPL_FW6_COOKIE_CCR = 0, 431 CPL_FW6_COOKIE_KTLS, 432 433 NUM_CPL_FW6_COOKIES = 2 /* Low bits of cookie value. */ 434 }; 435 436 _Static_assert(powerof2(NUM_CPL_FW6_COOKIES), 437 "NUM_CPL_FW6_COOKIES must be a power of 2"); 438 439 #define CPL_FW6_COOKIE_MASK (NUM_CPL_FW6_COOKIES - 1) 440 441 #define CPL_FW6_PLD_COOKIE(cpl) (be64toh((cpl)->data[1]) & ~CPL_FW6_COOKIE_MASK) 442 443 struct sge_iq; 444 struct rss_header; 445 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 446 struct mbuf *); 447 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 448 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 449 450 /* 451 * Ingress Queue: T4 is producer, driver is consumer. 452 */ 453 struct sge_iq { 454 uint16_t flags; 455 uint8_t qtype; 456 volatile int state; 457 struct adapter *adapter; 458 struct iq_desc *desc; /* KVA of descriptor ring */ 459 int8_t intr_pktc_idx; /* packet count threshold index */ 460 uint8_t gen; /* generation bit */ 461 uint8_t intr_params; /* interrupt holdoff parameters */ 462 int8_t cong_drop; /* congestion drop settings for the queue */ 463 uint16_t qsize; /* size (# of entries) of the queue */ 464 uint16_t sidx; /* index of the entry with the status page */ 465 uint16_t cidx; /* consumer index */ 466 uint16_t cntxt_id; /* SGE context id for the iq */ 467 uint16_t abs_id; /* absolute SGE id for the iq */ 468 int16_t intr_idx; /* interrupt used by the queue */ 469 470 STAILQ_ENTRY(sge_iq) link; 471 472 bus_dma_tag_t desc_tag; 473 bus_dmamap_t desc_map; 474 bus_addr_t ba; /* bus address of descriptor ring */ 475 }; 476 477 enum { 478 /* eq type */ 479 EQ_CTRL = 1, 480 EQ_ETH = 2, 481 EQ_OFLD = 3, 482 483 /* eq flags */ 484 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 485 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 486 EQ_ENABLED = (1 << 3), /* open for business */ 487 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 488 }; 489 490 /* Listed in order of preference. Update t4_sysctls too if you change these */ 491 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 492 493 /* 494 * Egress Queue: driver is producer, T4 is consumer. 495 * 496 * Note: A free list is an egress queue (driver produces the buffers and T4 497 * consumes them) but it's special enough to have its own struct (see sge_fl). 498 */ 499 struct sge_eq { 500 unsigned int flags; /* MUST be first */ 501 unsigned int cntxt_id; /* SGE context id for the eq */ 502 unsigned int abs_id; /* absolute SGE id for the eq */ 503 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 504 uint8_t doorbells; 505 uint8_t port_id; /* port_id of the port associated with the eq */ 506 uint8_t tx_chan; /* tx channel used by the eq */ 507 uint8_t hw_port; /* hw port used by the eq */ 508 struct mtx eq_lock; 509 510 struct tx_desc *desc; /* KVA of descriptor ring */ 511 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 512 u_int udb_qid; /* relative qid within the doorbell page */ 513 uint16_t sidx; /* index of the entry with the status page */ 514 uint16_t cidx; /* consumer idx (desc idx) */ 515 uint16_t pidx; /* producer idx (desc idx) */ 516 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 517 uint16_t dbidx; /* pidx of the most recent doorbell */ 518 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 519 volatile u_int equiq; /* EQUIQ outstanding */ 520 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 521 522 bus_dma_tag_t desc_tag; 523 bus_dmamap_t desc_map; 524 bus_addr_t ba; /* bus address of descriptor ring */ 525 char lockname[16]; 526 }; 527 528 struct rx_buf_info { 529 uma_zone_t zone; /* zone that this cluster comes from */ 530 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 531 * hwsize[hwidx1] = size1. No spare. */ 532 uint16_t size2; /* hwsize[hwidx2] = size2. 533 * spare in cluster = size1 - size2. */ 534 int8_t hwidx1; /* SGE bufsize idx for size1 */ 535 int8_t hwidx2; /* SGE bufsize idx for size2 */ 536 uint8_t type; /* EXT_xxx type of the cluster */ 537 }; 538 539 enum { 540 NUM_MEMWIN = 3, 541 542 MEMWIN0_APERTURE = 2048, 543 MEMWIN0_BASE = 0x1b800, 544 545 MEMWIN1_APERTURE = 32768, 546 MEMWIN1_BASE = 0x28000, 547 548 MEMWIN2_APERTURE_T4 = 65536, 549 MEMWIN2_BASE_T4 = 0x30000, 550 551 MEMWIN2_APERTURE_T5 = 128 * 1024, 552 MEMWIN2_BASE_T5 = 0x60000, 553 }; 554 555 struct memwin { 556 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 557 uint32_t mw_base; /* constant after setup_memwin */ 558 uint32_t mw_aperture; /* ditto */ 559 uint32_t mw_curpos; /* protected by mw_lock */ 560 }; 561 562 enum { 563 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 564 FL_DOOMED = (1 << 1), /* about to be destroyed */ 565 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 566 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 567 }; 568 569 #define FL_RUNNING_LOW(fl) \ 570 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 571 #define FL_NOT_RUNNING_LOW(fl) \ 572 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 573 574 struct sge_fl { 575 struct mtx fl_lock; 576 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 577 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 578 uint16_t zidx; /* refill zone idx */ 579 uint16_t safe_zidx; 580 uint16_t lowat; /* # of buffers <= this means fl needs help */ 581 int flags; 582 uint16_t buf_boundary; 583 584 /* The 16b idx all deal with hw descriptors */ 585 uint16_t dbidx; /* hw pidx after last doorbell */ 586 uint16_t sidx; /* index of status page */ 587 volatile uint16_t hw_cidx; 588 589 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 590 uint32_t cidx; /* consumer index */ 591 uint32_t pidx; /* producer index */ 592 593 uint32_t dbval; 594 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 595 volatile uint32_t *udb; 596 597 uint64_t cl_allocated; /* # of clusters allocated */ 598 uint64_t cl_recycled; /* # of clusters recycled */ 599 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 600 601 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 602 struct mbuf *m0; 603 struct mbuf **pnext; 604 u_int remaining; 605 606 uint16_t qsize; /* # of hw descriptors (status page included) */ 607 uint16_t cntxt_id; /* SGE context id for the freelist */ 608 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 609 bus_dma_tag_t desc_tag; 610 bus_dmamap_t desc_map; 611 char lockname[16]; 612 bus_addr_t ba; /* bus address of descriptor ring */ 613 }; 614 615 struct mp_ring; 616 617 struct txpkts { 618 uint8_t wr_type; /* type 0 or type 1 */ 619 uint8_t npkt; /* # of packets in this work request */ 620 uint8_t len16; /* # of 16B pieces used by this work request */ 621 uint8_t score; 622 uint8_t max_npkt; /* maximum number of packets allowed */ 623 uint16_t plen; /* total payload (sum of all packets) */ 624 625 /* straight from fw_eth_tx_pkts_vm_wr. */ 626 __u8 ethmacdst[6]; 627 __u8 ethmacsrc[6]; 628 __be16 ethtype; 629 __be16 vlantci; 630 631 struct mbuf *mb[15]; 632 }; 633 634 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 635 struct sge_txq { 636 struct sge_eq eq; /* MUST be first */ 637 638 if_t ifp; /* the interface this txq belongs to */ 639 struct mp_ring *r; /* tx software ring */ 640 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 641 struct sglist *gl; 642 __be32 cpl_ctrl0; /* for convenience */ 643 int tc_idx; /* traffic class */ 644 uint64_t last_tx; /* cycle count when eth_tx was last called */ 645 struct txpkts txp; 646 647 struct task tx_reclaim_task; 648 /* stats for common events first */ 649 650 uint64_t txcsum; /* # of times hardware assisted with checksum */ 651 uint64_t tso_wrs; /* # of TSO work requests */ 652 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 653 uint64_t imm_wrs; /* # of work requests with immediate data */ 654 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 655 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 656 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 657 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 658 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 659 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 660 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 661 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 662 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 663 uint64_t vxlan_txcsum; 664 665 uint64_t kern_tls_records; 666 uint64_t kern_tls_short; 667 uint64_t kern_tls_partial; 668 uint64_t kern_tls_full; 669 uint64_t kern_tls_octets; 670 uint64_t kern_tls_waste; 671 uint64_t kern_tls_header; 672 uint64_t kern_tls_fin_short; 673 uint64_t kern_tls_cbc; 674 uint64_t kern_tls_gcm; 675 union { 676 struct { 677 /* T6 only. */ 678 uint64_t kern_tls_options; 679 uint64_t kern_tls_fin; 680 }; 681 struct { 682 /* T7 only. */ 683 uint64_t kern_tls_ghash_received; 684 uint64_t kern_tls_ghash_requested; 685 uint64_t kern_tls_lso; 686 uint64_t kern_tls_partial_ghash; 687 uint64_t kern_tls_splitmode; 688 uint64_t kern_tls_trailer; 689 }; 690 }; 691 692 /* stats for not-that-common events */ 693 694 /* Optional scratch space for constructing work requests. */ 695 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 696 } __aligned(CACHE_LINE_SIZE); 697 698 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 699 struct sge_rxq { 700 struct sge_iq iq; /* MUST be first */ 701 struct sge_fl fl; /* MUST follow iq */ 702 703 if_t ifp; /* the interface this rxq belongs to */ 704 struct lro_ctrl lro; /* LRO state */ 705 706 /* stats for common events first */ 707 708 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 709 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 710 uint64_t vxlan_rxcsum; 711 712 /* stats for not-that-common events */ 713 714 } __aligned(CACHE_LINE_SIZE); 715 716 static inline struct sge_rxq * 717 iq_to_rxq(struct sge_iq *iq) 718 { 719 720 return (__containerof(iq, struct sge_rxq, iq)); 721 } 722 723 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 724 struct sge_ofld_rxq { 725 struct sge_iq iq; /* MUST be first */ 726 struct sge_fl fl; /* MUST follow iq */ 727 counter_u64_t rx_iscsi_ddp_setup_ok; 728 counter_u64_t rx_iscsi_ddp_setup_error; 729 uint64_t rx_iscsi_ddp_pdus; 730 uint64_t rx_iscsi_ddp_octets; 731 uint64_t rx_iscsi_fl_pdus; 732 uint64_t rx_iscsi_fl_octets; 733 uint64_t rx_iscsi_padding_errors; 734 uint64_t rx_iscsi_header_digest_errors; 735 uint64_t rx_iscsi_data_digest_errors; 736 counter_u64_t rx_nvme_ddp_setup_ok; 737 counter_u64_t rx_nvme_ddp_setup_no_stag; 738 counter_u64_t rx_nvme_ddp_setup_error; 739 counter_u64_t rx_nvme_ddp_pdus; 740 counter_u64_t rx_nvme_ddp_octets; 741 counter_u64_t rx_nvme_fl_pdus; 742 counter_u64_t rx_nvme_fl_octets; 743 counter_u64_t rx_nvme_invalid_headers; 744 counter_u64_t rx_nvme_header_digest_errors; 745 counter_u64_t rx_nvme_data_digest_errors; 746 uint64_t rx_aio_ddp_jobs; 747 uint64_t rx_aio_ddp_octets; 748 u_long rx_toe_tls_records; 749 u_long rx_toe_tls_octets; 750 u_long rx_toe_ddp_octets; 751 counter_u64_t ddp_buffer_alloc; 752 counter_u64_t ddp_buffer_reuse; 753 counter_u64_t ddp_buffer_free; 754 } __aligned(CACHE_LINE_SIZE); 755 756 static inline struct sge_ofld_rxq * 757 iq_to_ofld_rxq(struct sge_iq *iq) 758 { 759 760 return (__containerof(iq, struct sge_ofld_rxq, iq)); 761 } 762 763 struct wrqe { 764 STAILQ_ENTRY(wrqe) link; 765 struct sge_wrq *wrq; 766 int wr_len; 767 char wr[] __aligned(16); 768 }; 769 770 struct wrq_cookie { 771 TAILQ_ENTRY(wrq_cookie) link; 772 int ndesc; 773 int pidx; 774 }; 775 776 /* 777 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 778 * are of this type. 779 */ 780 struct sge_wrq { 781 struct sge_eq eq; /* MUST be first */ 782 783 struct adapter *adapter; 784 struct task wrq_tx_task; 785 786 /* Tx desc reserved but WR not "committed" yet. */ 787 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 788 789 /* List of WRs ready to go out as soon as descriptors are available. */ 790 STAILQ_HEAD(, wrqe) wr_list; 791 u_int nwr_pending; 792 u_int ndesc_needed; 793 794 /* stats for common events first */ 795 796 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 797 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 798 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 799 800 /* stats for not-that-common events */ 801 802 /* 803 * Scratch space for work requests that wrap around after reaching the 804 * status page, and some information about the last WR that used it. 805 */ 806 uint16_t ss_pidx; 807 uint16_t ss_len; 808 uint8_t ss[SGE_MAX_WR_LEN]; 809 810 } __aligned(CACHE_LINE_SIZE); 811 812 /* ofld_txq: SGE egress queue + miscellaneous items */ 813 struct sge_ofld_txq { 814 struct sge_wrq wrq; 815 counter_u64_t tx_iscsi_pdus; 816 counter_u64_t tx_iscsi_octets; 817 counter_u64_t tx_iscsi_iso_wrs; 818 counter_u64_t tx_nvme_pdus; 819 counter_u64_t tx_nvme_octets; 820 counter_u64_t tx_nvme_iso_wrs; 821 counter_u64_t tx_aio_jobs; 822 counter_u64_t tx_aio_octets; 823 counter_u64_t tx_toe_tls_records; 824 counter_u64_t tx_toe_tls_octets; 825 } __aligned(CACHE_LINE_SIZE); 826 827 static inline int 828 ofld_txq_group(int val, int mask) 829 { 830 const uint32_t ngroup = 1 << bitcount32(mask); 831 const int mshift = ffs(mask) - 1; 832 const uint32_t gmask = ngroup - 1; 833 834 return (val >> mshift & gmask); 835 } 836 837 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 838 struct sge_nm_rxq { 839 /* Items used by the driver rx ithread are in this cacheline. */ 840 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 841 u_int nid; /* netmap ring # for this queue */ 842 struct vi_info *vi; 843 844 struct iq_desc *iq_desc; 845 uint16_t iq_abs_id; 846 uint16_t iq_cntxt_id; 847 uint16_t iq_cidx; 848 uint16_t iq_sidx; 849 uint8_t iq_gen; 850 uint32_t fl_sidx; 851 852 /* Items used by netmap rxsync are in this cacheline. */ 853 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 854 uint16_t fl_cntxt_id; 855 uint32_t fl_pidx; 856 uint32_t fl_sidx2; /* copy of fl_sidx */ 857 uint32_t fl_db_val; 858 u_int fl_db_saved; 859 u_int fl_db_threshold; /* in descriptors */ 860 u_int fl_hwidx:4; 861 862 /* 863 * fl_cidx is used by both the ithread and rxsync, the rest are not used 864 * in the rx fast path. 865 */ 866 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 867 868 bus_dma_tag_t iq_desc_tag; 869 bus_dmamap_t iq_desc_map; 870 bus_addr_t iq_ba; 871 int intr_idx; 872 873 bus_dma_tag_t fl_desc_tag; 874 bus_dmamap_t fl_desc_map; 875 bus_addr_t fl_ba; 876 }; 877 878 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 879 struct sge_nm_txq { 880 struct tx_desc *desc; 881 uint16_t cidx; 882 uint16_t pidx; 883 uint16_t sidx; 884 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 885 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 886 uint16_t dbidx; /* pidx of the most recent doorbell */ 887 uint8_t doorbells; 888 volatile uint32_t *udb; 889 u_int udb_qid; 890 u_int cntxt_id; 891 __be32 cpl_ctrl0; /* for convenience */ 892 __be32 op_pkd; /* ditto */ 893 u_int nid; /* netmap ring # for this queue */ 894 895 /* infrequently used items after this */ 896 897 bus_dma_tag_t desc_tag; 898 bus_dmamap_t desc_map; 899 bus_addr_t ba; 900 int iqidx; 901 } __aligned(CACHE_LINE_SIZE); 902 903 struct sge { 904 int nctrlq; /* total # of control queues */ 905 int nrxq; /* total # of Ethernet rx queues */ 906 int ntxq; /* total # of Ethernet tx queues */ 907 int nofldrxq; /* total # of TOE rx queues */ 908 int nofldtxq; /* total # of TOE tx queues */ 909 int nnmrxq; /* total # of netmap rx queues */ 910 int nnmtxq; /* total # of netmap tx queues */ 911 int niq; /* total # of ingress queues */ 912 int neq; /* total # of egress queues */ 913 914 struct sge_iq fwq; /* Firmware event queue */ 915 struct sge_wrq *ctrlq; /* Control queues */ 916 struct sge_txq *txq; /* NIC tx queues */ 917 struct sge_rxq *rxq; /* NIC rx queues */ 918 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 919 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 920 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 921 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 922 923 uint16_t iq_start; /* first cntxt_id */ 924 uint16_t iq_base; /* first abs_id */ 925 int eq_start; /* first cntxt_id */ 926 int eq_base; /* first abs_id */ 927 int iqmap_sz; 928 int eqmap_sz; 929 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 930 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 931 932 int8_t safe_zidx; 933 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 934 }; 935 936 struct devnames { 937 const char *nexus_name; 938 const char *ifnet_name; 939 const char *vi_ifnet_name; 940 const char *pf03_drv_name; 941 const char *vf_nexus_name; 942 const char *vf_ifnet_name; 943 }; 944 945 struct clip_entry; 946 947 #define CNT_CAL_INFO 3 948 struct clock_sync { 949 uint64_t hw_cur; 950 uint64_t hw_prev; 951 sbintime_t sbt_cur; 952 sbintime_t sbt_prev; 953 seqc_t gen; 954 }; 955 956 struct adapter { 957 SLIST_ENTRY(adapter) link; 958 device_t dev; 959 struct cdev *cdev; 960 const struct devnames *names; 961 962 /* PCIe register resources */ 963 int regs_rid; 964 struct resource *regs_res; 965 int msix_rid; 966 struct resource *msix_res; 967 bus_size_t mmio_len; 968 int udbs_rid; 969 struct resource *udbs_res; 970 volatile uint8_t *udbs_base; 971 972 unsigned int pf; 973 unsigned int mbox; 974 unsigned int vpd_busy; 975 unsigned int vpd_flag; 976 977 /* Interrupt information */ 978 int intr_type; 979 int intr_count; 980 struct irq { 981 struct resource *res; 982 int rid; 983 void *tag; 984 struct sge_rxq *rxq; 985 struct sge_nm_rxq *nm_rxq; 986 } __aligned(CACHE_LINE_SIZE) *irq; 987 int sge_gts_reg; 988 int sge_kdoorbell_reg; 989 990 bus_dma_tag_t dmat; /* Parent DMA tag */ 991 992 struct sge sge; 993 int lro_timeout; 994 int sc_do_rxcopy; 995 996 int vxlan_port; 997 u_int vxlan_refcount; 998 int rawf_base; 999 int nrawf; 1000 u_int vlan_id; 1001 1002 struct taskqueue *tq[MAX_NPORTS]; /* General purpose taskqueues */ 1003 struct port_info *port[MAX_NPORTS]; 1004 uint8_t chan_map[MAX_NCHAN]; /* tx_chan -> port_id */ 1005 uint8_t port_map[MAX_NPORTS]; /* hw_port -> port_id */ 1006 1007 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 1008 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 1009 u_long clip_mask; 1010 int clip_gen; 1011 struct timeout_task clip_task; 1012 1013 void *tom_softc; /* (struct tom_data *) */ 1014 struct tom_tunables tt; 1015 struct t4_offload_policy *policy; 1016 struct rwlock policy_lock; 1017 1018 void *iwarp_softc; /* (struct c4iw_dev *) */ 1019 struct iw_tunables iwt; 1020 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 1021 void *nvme_ulp_softc; /* (struct nvmf_che_adapter *) */ 1022 struct l2t_data *l2t; /* L2 table */ 1023 struct smt_data *smt; /* Source MAC Table */ 1024 struct tid_info tids; 1025 vmem_t *key_map; 1026 struct tls_tunables tlst; 1027 1028 vmem_t *pbl_arena; 1029 vmem_t *stag_arena; 1030 1031 uint8_t doorbells; 1032 int offload_map; /* port_id's with IFCAP_TOE enabled */ 1033 int bt_map; /* hw_port's that are BASE-T */ 1034 int active_ulds; /* ULDs activated on this adapter */ 1035 int flags; 1036 int debug_flags; 1037 int error_flags; /* Used by error handler and live reset. */ 1038 int intr_flags; /* Used by interrupt setup/handlers. */ 1039 1040 char ifp_lockname[16]; 1041 struct mtx ifp_lock; 1042 if_t ifp; /* tracer ifp */ 1043 struct ifmedia media; 1044 int traceq; /* iq used by all tracers, -1 if none */ 1045 int tracer_valid; /* bitmap of valid tracers */ 1046 int tracer_enabled; /* bitmap of enabled tracers */ 1047 1048 char fw_version[16]; 1049 char tp_version[16]; 1050 char er_version[16]; 1051 char bs_version[16]; 1052 char cfg_file[32]; 1053 u_int cfcsum; 1054 struct adapter_params params; 1055 const struct chip_params *chip_params; 1056 struct t4_virt_res vres; 1057 1058 uint16_t nbmcaps; 1059 uint16_t linkcaps; 1060 uint16_t switchcaps; 1061 uint16_t nvmecaps; 1062 uint16_t niccaps; 1063 uint16_t toecaps; 1064 uint16_t rdmacaps; 1065 uint16_t cryptocaps; 1066 uint16_t iscsicaps; 1067 uint16_t fcoecaps; 1068 1069 struct sysctl_ctx_list ctx; 1070 struct sysctl_oid *ctrlq_oid; 1071 struct sysctl_oid *fwq_oid; 1072 1073 struct mtx sc_lock; 1074 char lockname[16]; 1075 1076 /* Starving free lists */ 1077 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 1078 TAILQ_HEAD(, sge_fl) sfl; 1079 struct callout sfl_callout; 1080 struct callout cal_callout; 1081 struct clock_sync cal_info[CNT_CAL_INFO]; 1082 int cal_current; 1083 int cal_count; 1084 uint32_t cal_gen; 1085 1086 /* 1087 * Driver code that can run when the adapter is suspended must use this 1088 * lock or a synchronized_op and check for HW_OFF_LIMITS before 1089 * accessing hardware. 1090 * 1091 * XXX: could be changed to rwlock. wlock in suspend/resume and for 1092 * indirect register access, rlock everywhere else. 1093 */ 1094 struct mtx reg_lock; 1095 1096 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 1097 1098 struct mtx tc_lock; 1099 struct task tc_task; 1100 1101 struct task fatal_error_task; 1102 struct task reset_task; 1103 const void *reset_thread; 1104 int num_resets; 1105 int incarnation; 1106 1107 const char *last_op; 1108 const void *last_op_thr; 1109 int last_op_flags; 1110 1111 int swintr; 1112 int sensor_resets; 1113 1114 struct callout ktls_tick; 1115 }; 1116 1117 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1118 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1119 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1120 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1121 1122 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1123 KASSERT(IS_BUSY(sc) && \ 1124 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1125 ("%s: operation not synchronized.", __func__)) 1126 1127 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1128 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1129 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1130 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1131 1132 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1133 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1134 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1135 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1136 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1137 1138 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1139 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1140 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1141 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1142 1143 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1144 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1145 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1146 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1147 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1148 1149 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1150 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1151 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1152 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1153 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1154 1155 #define for_each_txq(vi, iter, q) \ 1156 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1157 iter < vi->ntxq; ++iter, ++q) 1158 #define for_each_rxq(vi, iter, q) \ 1159 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1160 iter < vi->nrxq; ++iter, ++q) 1161 #define for_each_ofld_txq(vi, iter, q) \ 1162 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1163 iter < vi->nofldtxq; ++iter, ++q) 1164 #define for_each_ofld_rxq(vi, iter, q) \ 1165 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1166 iter < vi->nofldrxq; ++iter, ++q) 1167 #define for_each_nm_txq(vi, iter, q) \ 1168 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1169 iter < vi->nnmtxq; ++iter, ++q) 1170 #define for_each_nm_rxq(vi, iter, q) \ 1171 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1172 iter < vi->nnmrxq; ++iter, ++q) 1173 #define for_each_vi(_pi, _iter, _vi) \ 1174 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1175 ++(_iter), ++(_vi)) 1176 1177 #define IDXINCR(idx, incr, wrap) do { \ 1178 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1179 } while (0) 1180 #define IDXDIFF(head, tail, wrap) \ 1181 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1182 1183 /* One for errors, one for firmware events */ 1184 #define T4_EXTRA_INTR 2 1185 1186 /* One for firmware events */ 1187 #define T4VF_EXTRA_INTR 1 1188 1189 static inline int 1190 forwarding_intr_to_fwq(struct adapter *sc) 1191 { 1192 1193 return (sc->intr_count == 1); 1194 } 1195 1196 /* Works reliably inside a synch_op or with reg_lock held. */ 1197 static inline bool 1198 hw_off_limits(struct adapter *sc) 1199 { 1200 const int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1201 1202 return (__predict_false(off_limits != 0)); 1203 } 1204 1205 /* Works reliably inside a synch_op or with reg_lock held. */ 1206 static inline bool 1207 hw_all_ok(struct adapter *sc) 1208 { 1209 const int not_ok = atomic_load_int(&sc->error_flags) & 1210 (ADAP_STOPPED | HW_OFF_LIMITS); 1211 1212 return (__predict_true(not_ok == 0)); 1213 } 1214 1215 static inline int 1216 mbuf_nsegs(struct mbuf *m) 1217 { 1218 M_ASSERTPKTHDR(m); 1219 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 1220 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1221 1222 return (m->m_pkthdr.inner_l5hlen); 1223 } 1224 1225 static inline void 1226 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1227 { 1228 M_ASSERTPKTHDR(m); 1229 m->m_pkthdr.inner_l5hlen = nsegs; 1230 } 1231 1232 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 1233 #define MC_NOMAP 0x01 1234 #define MC_RAW_WR 0x02 1235 #define MC_TLS 0x04 1236 1237 static inline int 1238 mbuf_cflags(struct mbuf *m) 1239 { 1240 M_ASSERTPKTHDR(m); 1241 return (m->m_pkthdr.PH_loc.eight[4]); 1242 } 1243 1244 static inline void 1245 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 1246 { 1247 M_ASSERTPKTHDR(m); 1248 m->m_pkthdr.PH_loc.eight[4] = flags; 1249 } 1250 1251 static inline int 1252 mbuf_len16(struct mbuf *m) 1253 { 1254 int n; 1255 1256 M_ASSERTPKTHDR(m); 1257 n = m->m_pkthdr.PH_loc.eight[0]; 1258 if (!(mbuf_cflags(m) & MC_TLS)) 1259 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1260 1261 return (n); 1262 } 1263 1264 static inline void 1265 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1266 { 1267 M_ASSERTPKTHDR(m); 1268 if (!(mbuf_cflags(m) & MC_TLS)) 1269 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 1270 m->m_pkthdr.PH_loc.eight[0] = len16; 1271 } 1272 1273 static inline uint32_t 1274 t4_read_reg(struct adapter *sc, uint32_t reg) 1275 { 1276 if (hw_off_limits(sc)) 1277 MPASS(curthread == sc->reset_thread); 1278 return bus_read_4(sc->regs_res, reg); 1279 } 1280 1281 static inline void 1282 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1283 { 1284 if (hw_off_limits(sc)) 1285 MPASS(curthread == sc->reset_thread); 1286 bus_write_4(sc->regs_res, reg, val); 1287 } 1288 1289 static inline uint64_t 1290 t4_read_reg64(struct adapter *sc, uint32_t reg) 1291 { 1292 if (hw_off_limits(sc)) 1293 MPASS(curthread == sc->reset_thread); 1294 #ifdef __LP64__ 1295 return bus_read_8(sc->regs_res, reg); 1296 #else 1297 return (uint64_t)bus_read_4(sc->regs_res, reg) + 1298 ((uint64_t)bus_read_4(sc->regs_res, reg + 4) << 32); 1299 1300 #endif 1301 } 1302 1303 static inline void 1304 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1305 { 1306 if (hw_off_limits(sc)) 1307 MPASS(curthread == sc->reset_thread); 1308 #ifdef __LP64__ 1309 bus_write_8(sc->regs_res, reg, val); 1310 #else 1311 bus_write_4(sc->regs_res, reg, val); 1312 bus_write_4(sc->regs_res, reg + 4, val>> 32); 1313 #endif 1314 } 1315 1316 static inline void 1317 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1318 { 1319 if (hw_off_limits(sc)) 1320 MPASS(curthread == sc->reset_thread); 1321 *val = pci_read_config(sc->dev, reg, 1); 1322 } 1323 1324 static inline void 1325 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1326 { 1327 if (hw_off_limits(sc)) 1328 MPASS(curthread == sc->reset_thread); 1329 pci_write_config(sc->dev, reg, val, 1); 1330 } 1331 1332 static inline void 1333 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1334 { 1335 1336 if (hw_off_limits(sc)) 1337 MPASS(curthread == sc->reset_thread); 1338 *val = pci_read_config(sc->dev, reg, 2); 1339 } 1340 1341 static inline void 1342 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1343 { 1344 if (hw_off_limits(sc)) 1345 MPASS(curthread == sc->reset_thread); 1346 pci_write_config(sc->dev, reg, val, 2); 1347 } 1348 1349 static inline void 1350 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1351 { 1352 if (hw_off_limits(sc)) 1353 MPASS(curthread == sc->reset_thread); 1354 *val = pci_read_config(sc->dev, reg, 4); 1355 } 1356 1357 static inline void 1358 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1359 { 1360 if (hw_off_limits(sc)) 1361 MPASS(curthread == sc->reset_thread); 1362 pci_write_config(sc->dev, reg, val, 4); 1363 } 1364 1365 static inline struct port_info * 1366 adap2pinfo(struct adapter *sc, int idx) 1367 { 1368 1369 return (sc->port[idx]); 1370 } 1371 1372 static inline void 1373 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1374 { 1375 1376 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1377 } 1378 1379 static inline int 1380 tx_resume_threshold(struct sge_eq *eq) 1381 { 1382 1383 /* not quite the same as qsize / 4, but this will do. */ 1384 return (eq->sidx / 4); 1385 } 1386 1387 static inline int 1388 t4_use_ldst(struct adapter *sc) 1389 { 1390 1391 #ifdef notyet 1392 return (sc->flags & FW_OK || !sc->use_bd); 1393 #else 1394 return (0); 1395 #endif 1396 } 1397 1398 static inline void 1399 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1400 const char *msg, const __be64 *const p, const bool err) 1401 { 1402 1403 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1404 return; 1405 if (p != NULL) { 1406 log(err ? LOG_ERR : LOG_DEBUG, 1407 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1408 "%016llx %016llx %016llx %016llx\n", 1409 device_get_nameunit(sc->dev), mbox, msg, 1410 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1411 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1412 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1413 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1414 } else { 1415 log(err ? LOG_ERR : LOG_DEBUG, 1416 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1417 "%016llx %016llx %016llx %016llx\n", 1418 device_get_nameunit(sc->dev), mbox, msg, 1419 (long long)t4_read_reg64(sc, reg), 1420 (long long)t4_read_reg64(sc, reg + 8), 1421 (long long)t4_read_reg64(sc, reg + 16), 1422 (long long)t4_read_reg64(sc, reg + 24), 1423 (long long)t4_read_reg64(sc, reg + 32), 1424 (long long)t4_read_reg64(sc, reg + 40), 1425 (long long)t4_read_reg64(sc, reg + 48), 1426 (long long)t4_read_reg64(sc, reg + 56)); 1427 } 1428 } 1429 1430 /* t4_main.c */ 1431 extern int t4_ntxq; 1432 extern int t4_nrxq; 1433 extern int t4_intr_types; 1434 extern int t4_tmr_idx; 1435 extern int t4_pktc_idx; 1436 extern unsigned int t4_qsize_rxq; 1437 extern unsigned int t4_qsize_txq; 1438 extern int t4_ddp_rcvbuf_len; 1439 extern unsigned int t4_ddp_rcvbuf_cache; 1440 extern device_method_t cxgbe_methods[]; 1441 1442 int t4_os_find_pci_capability(struct adapter *, int); 1443 void t4_os_portmod_changed(struct port_info *); 1444 void t4_os_link_changed(struct port_info *); 1445 void t4_iterate(void (*)(struct adapter *, void *), void *); 1446 void t4_init_devnames(struct adapter *); 1447 void t4_add_adapter(struct adapter *); 1448 int t4_detach_common(device_t); 1449 int t4_map_bars_0_and_4(struct adapter *); 1450 int t4_map_bar_2(struct adapter *); 1451 int t4_adj_doorbells(struct adapter *); 1452 int t4_setup_intr_handlers(struct adapter *); 1453 void t4_sysctls(struct adapter *); 1454 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1455 void end_synchronized_op(struct adapter *, int); 1456 void begin_vi_detach(struct adapter *, struct vi_info *); 1457 void end_vi_detach(struct adapter *, struct vi_info *); 1458 int update_mac_settings(if_t, int); 1459 int adapter_init(struct adapter *); 1460 int vi_init(struct vi_info *); 1461 void vi_sysctls(struct vi_info *); 1462 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1463 int alloc_atid(struct adapter *, void *); 1464 void *lookup_atid(struct adapter *, int); 1465 void free_atid(struct adapter *, int); 1466 void release_tid(struct adapter *, int, struct sge_wrq *); 1467 int cxgbe_media_change(if_t); 1468 void cxgbe_media_status(if_t, struct ifmediareq *); 1469 void t4_os_cim_err(struct adapter *); 1470 int suspend_adapter(struct adapter *); 1471 int resume_adapter(struct adapter *); 1472 int toe_capability(struct vi_info *, bool); 1473 1474 #ifdef KERN_TLS 1475 /* t6_kern_tls.c */ 1476 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1477 struct m_snd_tag **); 1478 void t6_ktls_modload(void); 1479 void t6_ktls_modunload(void); 1480 int t6_ktls_try(if_t, struct socket *, struct ktls_session *); 1481 int t6_ktls_parse_pkt(struct mbuf *); 1482 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1483 1484 /* t7_kern_tls.c */ 1485 int t7_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1486 struct m_snd_tag **); 1487 void t7_ktls_modload(void); 1488 void t7_ktls_modunload(void); 1489 int t7_ktls_parse_pkt(struct mbuf *); 1490 int t7_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1491 #endif 1492 1493 /* t4_keyctx.c */ 1494 struct auth_hash; 1495 union authctx; 1496 #ifdef KERN_TLS 1497 struct ktls_session; 1498 struct tls_key_req; 1499 struct tls_keyctx; 1500 #endif 1501 1502 void t4_aes_getdeckey(void *, const void *, unsigned int); 1503 void t4_copy_partial_hash(int, union authctx *, void *); 1504 void t4_init_gmac_hash(const char *, int, char *); 1505 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1506 char *); 1507 #ifdef KERN_TLS 1508 u_int t4_tls_key_info_size(const struct ktls_session *); 1509 int t4_tls_proto_ver(const struct ktls_session *); 1510 int t4_tls_cipher_mode(const struct ktls_session *); 1511 int t4_tls_auth_mode(const struct ktls_session *); 1512 int t4_tls_hmac_ctrl(const struct ktls_session *); 1513 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1514 int t4_alloc_tls_keyid(struct adapter *); 1515 void t4_free_tls_keyid(struct adapter *, int); 1516 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1517 struct tls_key_req *); 1518 #endif 1519 1520 #ifdef DEV_NETMAP 1521 /* t4_netmap.c */ 1522 struct sge_nm_rxq; 1523 void cxgbe_nm_attach(struct vi_info *); 1524 void cxgbe_nm_detach(struct vi_info *); 1525 void service_nm_rxq(struct sge_nm_rxq *); 1526 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1527 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1528 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1529 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1530 #endif 1531 1532 /* t4_sge.c */ 1533 void t4_sge_modload(void); 1534 void t4_sge_modunload(void); 1535 uint64_t t4_sge_extfree_refs(void); 1536 void t4_tweak_chip_settings(struct adapter *); 1537 int t4_verify_chip_settings(struct adapter *); 1538 void t4_init_rx_buf_info(struct adapter *); 1539 int t4_create_dma_tag(struct adapter *); 1540 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1541 struct sysctl_oid_list *); 1542 int t4_destroy_dma_tag(struct adapter *); 1543 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1544 bus_addr_t *, void **); 1545 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1546 void *); 1547 void free_fl_buffers(struct adapter *, struct sge_fl *); 1548 int t4_setup_adapter_queues(struct adapter *); 1549 int t4_teardown_adapter_queues(struct adapter *); 1550 int t4_setup_vi_queues(struct vi_info *); 1551 int t4_teardown_vi_queues(struct vi_info *); 1552 void t4_intr_all(void *); 1553 void t4_intr(void *); 1554 #ifdef DEV_NETMAP 1555 void t4_nm_intr(void *); 1556 void t4_vi_intr(void *); 1557 #endif 1558 void t4_intr_err(void *); 1559 void t4_intr_evt(void *); 1560 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1561 void t4_update_fl_bufsize(if_t); 1562 struct mbuf *alloc_wr_mbuf(int, int); 1563 int parse_pkt(struct mbuf **, bool); 1564 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1565 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1566 int t4_sge_set_conm_context(struct adapter *, int, int, int); 1567 void t4_register_an_handler(an_handler_t); 1568 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1569 void t4_register_cpl_handler(int, cpl_handler_t); 1570 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1571 #ifdef RATELIMIT 1572 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1573 #endif 1574 1575 /* t4_tracer.c */ 1576 struct t4_tracer; 1577 void t4_tracer_modload(void); 1578 void t4_tracer_modunload(void); 1579 void t4_tracer_port_detach(struct adapter *); 1580 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1581 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1582 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1583 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1584 1585 /* t4_sched.c */ 1586 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1587 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1588 int t4_init_tx_sched(struct adapter *); 1589 int t4_free_tx_sched(struct adapter *); 1590 void t4_update_tx_sched(struct adapter *); 1591 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1592 void t4_release_cl_rl(struct adapter *, int, int); 1593 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1594 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1595 #ifdef RATELIMIT 1596 void t4_init_etid_table(struct adapter *); 1597 void t4_free_etid_table(struct adapter *); 1598 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1599 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1600 struct m_snd_tag **); 1601 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1602 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *); 1603 #endif 1604 1605 /* t4_filter.c */ 1606 int get_filter_mode(struct adapter *, uint32_t *); 1607 int set_filter_mode(struct adapter *, uint32_t); 1608 int set_filter_mask(struct adapter *, uint32_t); 1609 int get_filter(struct adapter *, struct t4_filter *); 1610 int set_filter(struct adapter *, struct t4_filter *); 1611 int del_filter(struct adapter *, struct t4_filter *); 1612 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1613 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1614 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1615 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1616 void free_hftid_hash(struct tid_info *); 1617 1618 /* t4_tpt.c */ 1619 #define T4_STAG_UNSET 0xffffffff 1620 #define T4_WRITE_MEM_DMA_LEN \ 1621 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_sgl), 16) 1622 #define T4_ULPTX_MIN_IO 32 1623 #define T4_MAX_INLINE_SIZE 96 1624 #define T4_WRITE_MEM_INLINE_LEN(len) \ 1625 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_idata) + \ 1626 roundup((len), T4_ULPTX_MIN_IO), 16) 1627 1628 uint32_t t4_pblpool_alloc(struct adapter *, int); 1629 void t4_pblpool_free(struct adapter *, uint32_t, int); 1630 uint32_t t4_stag_alloc(struct adapter *, int); 1631 void t4_stag_free(struct adapter *, uint32_t, int); 1632 void t4_init_tpt(struct adapter *); 1633 void t4_free_tpt(struct adapter *); 1634 void t4_write_mem_dma_wr(struct adapter *, void *, int, int, uint32_t, 1635 uint32_t, vm_paddr_t, uint64_t); 1636 void t4_write_mem_inline_wr(struct adapter *, void *, int, int, uint32_t, 1637 uint32_t, void *, uint64_t); 1638 1639 static inline struct wrqe * 1640 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1641 { 1642 int len = offsetof(struct wrqe, wr) + wr_len; 1643 struct wrqe *wr; 1644 1645 wr = malloc(len, M_CXGBE, M_NOWAIT); 1646 if (__predict_false(wr == NULL)) 1647 return (NULL); 1648 wr->wr_len = wr_len; 1649 wr->wrq = wrq; 1650 return (wr); 1651 } 1652 1653 static inline void * 1654 wrtod(struct wrqe *wr) 1655 { 1656 return (&wr->wr[0]); 1657 } 1658 1659 static inline void 1660 free_wrqe(struct wrqe *wr) 1661 { 1662 free(wr, M_CXGBE); 1663 } 1664 1665 static inline void 1666 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1667 { 1668 struct sge_wrq *wrq = wr->wrq; 1669 1670 TXQ_LOCK(wrq); 1671 if (__predict_true(wrq->eq.flags & EQ_HW_ALLOCATED)) 1672 t4_wrq_tx_locked(sc, wrq, wr); 1673 else 1674 free(wr, M_CXGBE); 1675 TXQ_UNLOCK(wrq); 1676 } 1677 1678 static inline int 1679 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1680 int len) 1681 { 1682 1683 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1684 } 1685 1686 static inline int 1687 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1688 const uint32_t *val, int len) 1689 { 1690 1691 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1692 } 1693 1694 /* Number of len16 -> number of descriptors */ 1695 static inline int 1696 tx_len16_to_desc(int len16) 1697 { 1698 1699 return (howmany(len16, EQ_ESIZE / 16)); 1700 } 1701 #endif 1702