1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 #define KTR_CXGBE KTR_SPARE3 61 MALLOC_DECLARE(M_CXGBE); 62 #define CXGBE_UNIMPLEMENTED(s) \ 63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 64 65 #if defined(__i386__) || defined(__amd64__) 66 static __inline void 67 prefetch(void *x) 68 { 69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 70 } 71 #else 72 #define prefetch(x) 73 #endif 74 75 #ifndef SYSCTL_ADD_UQUAD 76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 77 #define sysctl_handle_64 sysctl_handle_quad 78 #define CTLTYPE_U64 CTLTYPE_QUAD 79 #endif 80 81 #if (__FreeBSD_version >= 900030) || \ 82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 83 #define SBUF_DRAIN 1 84 #endif 85 86 #ifdef __amd64__ 87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 KASSERT(tag == X86_BUS_SPACE_MEM, 93 ("%s: can only handle mem space", __func__)); 94 95 return (*(volatile uint64_t *)(handle + offset)); 96 } 97 98 static __inline void 99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 100 bus_size_t offset, uint64_t value) 101 { 102 KASSERT(tag == X86_BUS_SPACE_MEM, 103 ("%s: can only handle mem space", __func__)); 104 105 *(volatile uint64_t *)(bsh + offset) = value; 106 } 107 #else 108 static __inline uint64_t 109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 110 bus_size_t offset) 111 { 112 return (uint64_t)bus_space_read_4(tag, handle, offset) + 113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 114 } 115 116 static __inline void 117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 118 bus_size_t offset, uint64_t value) 119 { 120 bus_space_write_4(tag, bsh, offset, value); 121 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 122 } 123 #endif 124 125 struct adapter; 126 typedef struct adapter adapter_t; 127 128 enum { 129 /* 130 * All ingress queues use this entry size. Note that the firmware event 131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 132 * be at least 64. 133 */ 134 IQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of ingress queues */ 137 FW_IQ_QSIZE = 256, 138 RX_IQ_QSIZE = 1024, 139 140 /* All egress queues use this entry size */ 141 EQ_ESIZE = 64, 142 143 /* Default queue sizes for all kinds of egress queues */ 144 CTRL_EQ_QSIZE = 128, 145 TX_EQ_QSIZE = 1024, 146 147 #if MJUMPAGESIZE != MCLBYTES 148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 149 #else 150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 151 #endif 152 CL_METADATA_SIZE = CACHE_LINE_SIZE, 153 154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 155 TX_SGL_SEGS = 39, 156 TX_SGL_SEGS_TSO = 38, 157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 158 }; 159 160 enum { 161 /* adapter intr_type */ 162 INTR_INTX = (1 << 0), 163 INTR_MSI = (1 << 1), 164 INTR_MSIX = (1 << 2) 165 }; 166 167 enum { 168 XGMAC_MTU = (1 << 0), 169 XGMAC_PROMISC = (1 << 1), 170 XGMAC_ALLMULTI = (1 << 2), 171 XGMAC_VLANEX = (1 << 3), 172 XGMAC_UCADDR = (1 << 4), 173 XGMAC_MCADDRS = (1 << 5), 174 175 XGMAC_ALL = 0xffff 176 }; 177 178 enum { 179 /* flags understood by begin_synchronized_op */ 180 HOLD_LOCK = (1 << 0), 181 SLEEP_OK = (1 << 1), 182 INTR_OK = (1 << 2), 183 184 /* flags understood by end_synchronized_op */ 185 LOCK_HELD = HOLD_LOCK, 186 }; 187 188 enum { 189 /* adapter flags */ 190 FULL_INIT_DONE = (1 << 0), 191 FW_OK = (1 << 1), 192 /* INTR_DIRECT = (1 << 2), No longer used. */ 193 MASTER_PF = (1 << 3), 194 ADAP_SYSCTL_CTX = (1 << 4), 195 /* TOM_INIT_DONE= (1 << 5), No longer used */ 196 BUF_PACKING_OK = (1 << 6), 197 198 CXGBE_BUSY = (1 << 9), 199 200 /* port flags */ 201 HAS_TRACEQ = (1 << 3), 202 203 /* VI flags */ 204 DOOMED = (1 << 0), 205 VI_INIT_DONE = (1 << 1), 206 VI_SYSCTL_CTX = (1 << 2), 207 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 208 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 209 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 210 VI_NETMAP = (1 << 6), 211 212 /* adapter debug_flags */ 213 DF_DUMP_MBOX = (1 << 0), 214 }; 215 216 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 217 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 218 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 219 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 220 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 221 222 struct vi_info { 223 device_t dev; 224 struct port_info *pi; 225 226 struct ifnet *ifp; 227 struct ifmedia media; 228 229 unsigned long flags; 230 int if_flags; 231 232 uint16_t *rss; 233 uint16_t viid; 234 int16_t xact_addr_filt;/* index of exact MAC address filter */ 235 uint16_t rss_size; /* size of VI's RSS table slice */ 236 uint16_t rss_base; /* start of VI's RSS table slice */ 237 238 eventhandler_tag vlan_c; 239 240 int nintr; 241 int first_intr; 242 243 /* These need to be int as they are used in sysctl */ 244 int ntxq; /* # of tx queues */ 245 int first_txq; /* index of first tx queue */ 246 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 247 int nrxq; /* # of rx queues */ 248 int first_rxq; /* index of first rx queue */ 249 int nofldtxq; /* # of offload tx queues */ 250 int first_ofld_txq; /* index of first offload tx queue */ 251 int nofldrxq; /* # of offload rx queues */ 252 int first_ofld_rxq; /* index of first offload rx queue */ 253 int tmr_idx; 254 int pktc_idx; 255 int qsize_rxq; 256 int qsize_txq; 257 258 struct timeval last_refreshed; 259 struct fw_vi_stats_vf stats; 260 261 struct callout tick; 262 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 263 264 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 265 }; 266 267 struct port_info { 268 device_t dev; 269 struct adapter *adapter; 270 271 struct vi_info *vi; 272 int nvi; 273 int up_vis; 274 int uld_vis; 275 276 struct mtx pi_lock; 277 char lockname[16]; 278 unsigned long flags; 279 280 uint8_t lport; /* associated offload logical port */ 281 int8_t mdio_addr; 282 uint8_t port_type; 283 uint8_t mod_type; 284 uint8_t port_id; 285 uint8_t tx_chan; 286 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 287 288 int linkdnrc; 289 struct link_config link_cfg; 290 291 struct timeval last_refreshed; 292 struct port_stats stats; 293 u_int tnl_cong_drops; 294 u_int tx_parse_error; 295 296 struct callout tick; 297 }; 298 299 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 300 301 /* Where the cluster came from, how it has been carved up. */ 302 struct cluster_layout { 303 int8_t zidx; 304 int8_t hwidx; 305 uint16_t region1; /* mbufs laid out within this region */ 306 /* region2 is the DMA region */ 307 uint16_t region3; /* cluster_metadata within this region */ 308 }; 309 310 struct cluster_metadata { 311 u_int refcount; 312 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 313 }; 314 315 struct fl_sdesc { 316 caddr_t cl; 317 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 318 struct cluster_layout cll; 319 }; 320 321 struct tx_desc { 322 __be64 flit[8]; 323 }; 324 325 struct tx_sdesc { 326 struct mbuf *m; /* m_nextpkt linked chain of frames */ 327 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 328 }; 329 330 331 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 332 struct iq_desc { 333 struct rss_header rss; 334 uint8_t cpl[IQ_PAD]; 335 struct rsp_ctrl rsp; 336 }; 337 #undef IQ_PAD 338 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 339 340 enum { 341 /* iq flags */ 342 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 343 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 344 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 345 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 346 347 /* iq state */ 348 IQS_DISABLED = 0, 349 IQS_BUSY = 1, 350 IQS_IDLE = 2, 351 }; 352 353 /* 354 * Ingress Queue: T4 is producer, driver is consumer. 355 */ 356 struct sge_iq { 357 uint32_t flags; 358 volatile int state; 359 struct adapter *adapter; 360 struct iq_desc *desc; /* KVA of descriptor ring */ 361 int8_t intr_pktc_idx; /* packet count threshold index */ 362 uint8_t gen; /* generation bit */ 363 uint8_t intr_params; /* interrupt holdoff parameters */ 364 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 365 uint16_t qsize; /* size (# of entries) of the queue */ 366 uint16_t sidx; /* index of the entry with the status page */ 367 uint16_t cidx; /* consumer index */ 368 uint16_t cntxt_id; /* SGE context id for the iq */ 369 uint16_t abs_id; /* absolute SGE id for the iq */ 370 371 STAILQ_ENTRY(sge_iq) link; 372 373 bus_dma_tag_t desc_tag; 374 bus_dmamap_t desc_map; 375 bus_addr_t ba; /* bus address of descriptor ring */ 376 }; 377 378 enum { 379 EQ_CTRL = 1, 380 EQ_ETH = 2, 381 EQ_OFLD = 3, 382 383 /* eq flags */ 384 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 385 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 386 EQ_ENABLED = (1 << 3), /* open for business */ 387 }; 388 389 /* Listed in order of preference. Update t4_sysctls too if you change these */ 390 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 391 392 /* 393 * Egress Queue: driver is producer, T4 is consumer. 394 * 395 * Note: A free list is an egress queue (driver produces the buffers and T4 396 * consumes them) but it's special enough to have its own struct (see sge_fl). 397 */ 398 struct sge_eq { 399 unsigned int flags; /* MUST be first */ 400 unsigned int cntxt_id; /* SGE context id for the eq */ 401 struct mtx eq_lock; 402 403 struct tx_desc *desc; /* KVA of descriptor ring */ 404 uint16_t doorbells; 405 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 406 u_int udb_qid; /* relative qid within the doorbell page */ 407 uint16_t sidx; /* index of the entry with the status page */ 408 uint16_t cidx; /* consumer idx (desc idx) */ 409 uint16_t pidx; /* producer idx (desc idx) */ 410 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 411 uint16_t dbidx; /* pidx of the most recent doorbell */ 412 uint16_t iqid; /* iq that gets egr_update for the eq */ 413 uint8_t tx_chan; /* tx channel used by the eq */ 414 volatile u_int equiq; /* EQUIQ outstanding */ 415 416 bus_dma_tag_t desc_tag; 417 bus_dmamap_t desc_map; 418 bus_addr_t ba; /* bus address of descriptor ring */ 419 char lockname[16]; 420 }; 421 422 struct sw_zone_info { 423 uma_zone_t zone; /* zone that this cluster comes from */ 424 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 425 int type; /* EXT_xxx type of the cluster */ 426 int8_t head_hwidx; 427 int8_t tail_hwidx; 428 }; 429 430 struct hw_buf_info { 431 int8_t zidx; /* backpointer to zone; -ve means unused */ 432 int8_t next; /* next hwidx for this zone; -1 means no more */ 433 int size; 434 }; 435 436 enum { 437 NUM_MEMWIN = 3, 438 439 MEMWIN0_APERTURE = 2048, 440 MEMWIN0_BASE = 0x1b800, 441 442 MEMWIN1_APERTURE = 32768, 443 MEMWIN1_BASE = 0x28000, 444 445 MEMWIN2_APERTURE_T4 = 65536, 446 MEMWIN2_BASE_T4 = 0x30000, 447 448 MEMWIN2_APERTURE_T5 = 128 * 1024, 449 MEMWIN2_BASE_T5 = 0x60000, 450 }; 451 452 struct memwin { 453 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 454 uint32_t mw_base; /* constant after setup_memwin */ 455 uint32_t mw_aperture; /* ditto */ 456 uint32_t mw_curpos; /* protected by mw_lock */ 457 }; 458 459 enum { 460 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 461 FL_DOOMED = (1 << 1), /* about to be destroyed */ 462 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 463 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 464 }; 465 466 #define FL_RUNNING_LOW(fl) \ 467 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 468 #define FL_NOT_RUNNING_LOW(fl) \ 469 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 470 471 struct sge_fl { 472 struct mtx fl_lock; 473 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 474 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 475 struct cluster_layout cll_def; /* default refill zone, layout */ 476 uint16_t lowat; /* # of buffers <= this means fl needs help */ 477 int flags; 478 uint16_t buf_boundary; 479 480 /* The 16b idx all deal with hw descriptors */ 481 uint16_t dbidx; /* hw pidx after last doorbell */ 482 uint16_t sidx; /* index of status page */ 483 volatile uint16_t hw_cidx; 484 485 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 486 uint32_t cidx; /* consumer index */ 487 uint32_t pidx; /* producer index */ 488 489 uint32_t dbval; 490 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 491 volatile uint32_t *udb; 492 493 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 494 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 495 uint64_t cl_allocated; /* # of clusters allocated */ 496 uint64_t cl_recycled; /* # of clusters recycled */ 497 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 498 499 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 500 struct mbuf *m0; 501 struct mbuf **pnext; 502 u_int remaining; 503 504 uint16_t qsize; /* # of hw descriptors (status page included) */ 505 uint16_t cntxt_id; /* SGE context id for the freelist */ 506 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 507 bus_dma_tag_t desc_tag; 508 bus_dmamap_t desc_map; 509 char lockname[16]; 510 bus_addr_t ba; /* bus address of descriptor ring */ 511 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 512 }; 513 514 struct mp_ring; 515 516 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 517 struct sge_txq { 518 struct sge_eq eq; /* MUST be first */ 519 520 struct ifnet *ifp; /* the interface this txq belongs to */ 521 struct mp_ring *r; /* tx software ring */ 522 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 523 struct sglist *gl; 524 __be32 cpl_ctrl0; /* for convenience */ 525 526 struct task tx_reclaim_task; 527 /* stats for common events first */ 528 529 uint64_t txcsum; /* # of times hardware assisted with checksum */ 530 uint64_t tso_wrs; /* # of TSO work requests */ 531 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 532 uint64_t imm_wrs; /* # of work requests with immediate data */ 533 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 534 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 535 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 536 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 537 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 538 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 539 540 /* stats for not-that-common events */ 541 } __aligned(CACHE_LINE_SIZE); 542 543 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 544 struct sge_rxq { 545 struct sge_iq iq; /* MUST be first */ 546 struct sge_fl fl; /* MUST follow iq */ 547 548 struct ifnet *ifp; /* the interface this rxq belongs to */ 549 #if defined(INET) || defined(INET6) 550 struct lro_ctrl lro; /* LRO state */ 551 #endif 552 553 /* stats for common events first */ 554 555 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 556 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 557 558 /* stats for not-that-common events */ 559 560 } __aligned(CACHE_LINE_SIZE); 561 562 static inline struct sge_rxq * 563 iq_to_rxq(struct sge_iq *iq) 564 { 565 566 return (__containerof(iq, struct sge_rxq, iq)); 567 } 568 569 570 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 571 struct sge_ofld_rxq { 572 struct sge_iq iq; /* MUST be first */ 573 struct sge_fl fl; /* MUST follow iq */ 574 } __aligned(CACHE_LINE_SIZE); 575 576 static inline struct sge_ofld_rxq * 577 iq_to_ofld_rxq(struct sge_iq *iq) 578 { 579 580 return (__containerof(iq, struct sge_ofld_rxq, iq)); 581 } 582 583 struct wrqe { 584 STAILQ_ENTRY(wrqe) link; 585 struct sge_wrq *wrq; 586 int wr_len; 587 char wr[] __aligned(16); 588 }; 589 590 struct wrq_cookie { 591 TAILQ_ENTRY(wrq_cookie) link; 592 int ndesc; 593 int pidx; 594 }; 595 596 /* 597 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 598 * and offload tx queues are of this type. 599 */ 600 struct sge_wrq { 601 struct sge_eq eq; /* MUST be first */ 602 603 struct adapter *adapter; 604 struct task wrq_tx_task; 605 606 /* Tx desc reserved but WR not "committed" yet. */ 607 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 608 609 /* List of WRs ready to go out as soon as descriptors are available. */ 610 STAILQ_HEAD(, wrqe) wr_list; 611 u_int nwr_pending; 612 u_int ndesc_needed; 613 614 /* stats for common events first */ 615 616 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 617 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 618 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 619 620 /* stats for not-that-common events */ 621 622 /* 623 * Scratch space for work requests that wrap around after reaching the 624 * status page, and some infomation about the last WR that used it. 625 */ 626 uint16_t ss_pidx; 627 uint16_t ss_len; 628 uint8_t ss[SGE_MAX_WR_LEN]; 629 630 } __aligned(CACHE_LINE_SIZE); 631 632 633 struct sge_nm_rxq { 634 struct vi_info *vi; 635 636 struct iq_desc *iq_desc; 637 uint16_t iq_abs_id; 638 uint16_t iq_cntxt_id; 639 uint16_t iq_cidx; 640 uint16_t iq_sidx; 641 uint8_t iq_gen; 642 643 __be64 *fl_desc; 644 uint16_t fl_cntxt_id; 645 uint32_t fl_cidx; 646 uint32_t fl_pidx; 647 uint32_t fl_sidx; 648 uint32_t fl_db_val; 649 u_int fl_hwidx:4; 650 651 u_int nid; /* netmap ring # for this queue */ 652 653 /* infrequently used items after this */ 654 655 bus_dma_tag_t iq_desc_tag; 656 bus_dmamap_t iq_desc_map; 657 bus_addr_t iq_ba; 658 int intr_idx; 659 660 bus_dma_tag_t fl_desc_tag; 661 bus_dmamap_t fl_desc_map; 662 bus_addr_t fl_ba; 663 } __aligned(CACHE_LINE_SIZE); 664 665 struct sge_nm_txq { 666 struct tx_desc *desc; 667 uint16_t cidx; 668 uint16_t pidx; 669 uint16_t sidx; 670 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 671 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 672 uint16_t dbidx; /* pidx of the most recent doorbell */ 673 uint16_t doorbells; 674 volatile uint32_t *udb; 675 u_int udb_qid; 676 u_int cntxt_id; 677 __be32 cpl_ctrl0; /* for convenience */ 678 u_int nid; /* netmap ring # for this queue */ 679 680 /* infrequently used items after this */ 681 682 bus_dma_tag_t desc_tag; 683 bus_dmamap_t desc_map; 684 bus_addr_t ba; 685 int iqidx; 686 } __aligned(CACHE_LINE_SIZE); 687 688 struct sge { 689 int nrxq; /* total # of Ethernet rx queues */ 690 int ntxq; /* total # of Ethernet tx tx queues */ 691 int nofldrxq; /* total # of TOE rx queues */ 692 int nofldtxq; /* total # of TOE tx queues */ 693 int nnmrxq; /* total # of netmap rx queues */ 694 int nnmtxq; /* total # of netmap tx queues */ 695 int niq; /* total # of ingress queues */ 696 int neq; /* total # of egress queues */ 697 698 struct sge_iq fwq; /* Firmware event queue */ 699 struct sge_wrq mgmtq; /* Management queue (control queue) */ 700 struct sge_wrq *ctrlq; /* Control queues */ 701 struct sge_txq *txq; /* NIC tx queues */ 702 struct sge_rxq *rxq; /* NIC rx queues */ 703 struct sge_wrq *ofld_txq; /* TOE tx queues */ 704 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 705 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 706 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 707 708 uint16_t iq_start; 709 int eq_start; 710 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 711 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 712 713 int8_t safe_hwidx1; /* may not have room for metadata */ 714 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 715 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 716 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 717 }; 718 719 struct rss_header; 720 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 721 struct mbuf *); 722 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 723 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 724 725 struct adapter { 726 SLIST_ENTRY(adapter) link; 727 device_t dev; 728 struct cdev *cdev; 729 730 /* PCIe register resources */ 731 int regs_rid; 732 struct resource *regs_res; 733 int msix_rid; 734 struct resource *msix_res; 735 bus_space_handle_t bh; 736 bus_space_tag_t bt; 737 bus_size_t mmio_len; 738 int udbs_rid; 739 struct resource *udbs_res; 740 volatile uint8_t *udbs_base; 741 742 unsigned int pf; 743 unsigned int mbox; 744 unsigned int vpd_busy; 745 unsigned int vpd_flag; 746 747 /* Interrupt information */ 748 int intr_type; 749 int intr_count; 750 struct irq { 751 struct resource *res; 752 int rid; 753 void *tag; 754 } *irq; 755 756 bus_dma_tag_t dmat; /* Parent DMA tag */ 757 758 struct sge sge; 759 int lro_timeout; 760 761 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 762 struct port_info *port[MAX_NPORTS]; 763 uint8_t chan_map[MAX_NCHAN]; 764 765 void *tom_softc; /* (struct tom_data *) */ 766 struct tom_tunables tt; 767 void *iwarp_softc; /* (struct c4iw_dev *) */ 768 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 769 struct l2t_data *l2t; /* L2 table */ 770 struct tid_info tids; 771 772 uint16_t doorbells; 773 int offload_map; /* ports with IFCAP_TOE enabled */ 774 int active_ulds; /* ULDs activated on this adapter */ 775 int flags; 776 int debug_flags; 777 778 char ifp_lockname[16]; 779 struct mtx ifp_lock; 780 struct ifnet *ifp; /* tracer ifp */ 781 struct ifmedia media; 782 int traceq; /* iq used by all tracers, -1 if none */ 783 int tracer_valid; /* bitmap of valid tracers */ 784 int tracer_enabled; /* bitmap of enabled tracers */ 785 786 char fw_version[16]; 787 char tp_version[16]; 788 char exprom_version[16]; 789 char cfg_file[32]; 790 u_int cfcsum; 791 struct adapter_params params; 792 const struct chip_params *chip_params; 793 struct t4_virt_res vres; 794 795 uint16_t nbmcaps; 796 uint16_t linkcaps; 797 uint16_t switchcaps; 798 uint16_t niccaps; 799 uint16_t toecaps; 800 uint16_t rdmacaps; 801 uint16_t tlscaps; 802 uint16_t iscsicaps; 803 uint16_t fcoecaps; 804 805 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 806 807 struct mtx sc_lock; 808 char lockname[16]; 809 810 /* Starving free lists */ 811 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 812 TAILQ_HEAD(, sge_fl) sfl; 813 struct callout sfl_callout; 814 815 struct mtx reg_lock; /* for indirect register access */ 816 817 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 818 819 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 820 fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */ 821 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 822 823 const char *last_op; 824 const void *last_op_thr; 825 int last_op_flags; 826 827 int sc_do_rxcopy; 828 }; 829 830 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 831 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 832 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 833 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 834 835 #define ASSERT_SYNCHRONIZED_OP(sc) \ 836 KASSERT(IS_BUSY(sc) && \ 837 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 838 ("%s: operation not synchronized.", __func__)) 839 840 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 841 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 842 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 843 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 844 845 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 846 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 847 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 848 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 849 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 850 851 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 852 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 853 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 854 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 855 856 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 857 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 858 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 859 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 860 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 861 862 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 863 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 864 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 865 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 866 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 867 868 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 869 do { \ 870 if (sc->debug_flags & DF_DUMP_MBOX) { \ 871 log(LOG_NOTICE, \ 872 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 873 "%016llx %016llx %016llx %016llx\n", \ 874 device_get_nameunit(sc->dev), mbox, \ 875 (unsigned long long)t4_read_reg64(sc, data_reg), \ 876 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 877 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 878 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 879 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 880 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 881 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 882 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 883 } \ 884 } while (0) 885 886 #define for_each_txq(vi, iter, q) \ 887 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 888 iter < vi->ntxq; ++iter, ++q) 889 #define for_each_rxq(vi, iter, q) \ 890 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 891 iter < vi->nrxq; ++iter, ++q) 892 #define for_each_ofld_txq(vi, iter, q) \ 893 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 894 iter < vi->nofldtxq; ++iter, ++q) 895 #define for_each_ofld_rxq(vi, iter, q) \ 896 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 897 iter < vi->nofldrxq; ++iter, ++q) 898 #define for_each_nm_txq(vi, iter, q) \ 899 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_txq], iter = 0; \ 900 iter < vi->ntxq; ++iter, ++q) 901 #define for_each_nm_rxq(vi, iter, q) \ 902 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_rxq], iter = 0; \ 903 iter < vi->nrxq; ++iter, ++q) 904 #define for_each_vi(_pi, _iter, _vi) \ 905 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 906 ++(_iter), ++(_vi)) 907 908 #define IDXINCR(idx, incr, wrap) do { \ 909 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 910 } while (0) 911 #define IDXDIFF(head, tail, wrap) \ 912 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 913 914 /* One for errors, one for firmware events */ 915 #define T4_EXTRA_INTR 2 916 917 static inline uint32_t 918 t4_read_reg(struct adapter *sc, uint32_t reg) 919 { 920 921 return bus_space_read_4(sc->bt, sc->bh, reg); 922 } 923 924 static inline void 925 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 926 { 927 928 bus_space_write_4(sc->bt, sc->bh, reg, val); 929 } 930 931 static inline uint64_t 932 t4_read_reg64(struct adapter *sc, uint32_t reg) 933 { 934 935 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 936 } 937 938 static inline void 939 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 940 { 941 942 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 943 } 944 945 static inline void 946 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 947 { 948 949 *val = pci_read_config(sc->dev, reg, 1); 950 } 951 952 static inline void 953 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 954 { 955 956 pci_write_config(sc->dev, reg, val, 1); 957 } 958 959 static inline void 960 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 961 { 962 963 *val = pci_read_config(sc->dev, reg, 2); 964 } 965 966 static inline void 967 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 968 { 969 970 pci_write_config(sc->dev, reg, val, 2); 971 } 972 973 static inline void 974 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 975 { 976 977 *val = pci_read_config(sc->dev, reg, 4); 978 } 979 980 static inline void 981 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 982 { 983 984 pci_write_config(sc->dev, reg, val, 4); 985 } 986 987 static inline struct port_info * 988 adap2pinfo(struct adapter *sc, int idx) 989 { 990 991 return (sc->port[idx]); 992 } 993 994 static inline void 995 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 996 { 997 998 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 999 } 1000 1001 static inline bool 1002 is_10G_port(const struct port_info *pi) 1003 { 1004 1005 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1006 } 1007 1008 static inline bool 1009 is_40G_port(const struct port_info *pi) 1010 { 1011 1012 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1013 } 1014 1015 static inline int 1016 port_top_speed(const struct port_info *pi) 1017 { 1018 1019 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1020 return (100); 1021 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1022 return (40); 1023 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1024 return (10); 1025 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1026 return (1); 1027 1028 return (0); 1029 } 1030 1031 static inline int 1032 tx_resume_threshold(struct sge_eq *eq) 1033 { 1034 1035 /* not quite the same as qsize / 4, but this will do. */ 1036 return (eq->sidx / 4); 1037 } 1038 1039 static inline int 1040 t4_use_ldst(struct adapter *sc) 1041 { 1042 1043 #ifdef notyet 1044 return (sc->flags & FW_OK || !sc->use_bd); 1045 #else 1046 return (0); 1047 #endif 1048 } 1049 1050 /* t4_main.c */ 1051 int t4_os_find_pci_capability(struct adapter *, int); 1052 int t4_os_pci_save_state(struct adapter *); 1053 int t4_os_pci_restore_state(struct adapter *); 1054 void t4_os_portmod_changed(const struct adapter *, int); 1055 void t4_os_link_changed(struct adapter *, int, int, int); 1056 void t4_iterate(void (*)(struct adapter *, void *), void *); 1057 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 1058 int t4_register_an_handler(struct adapter *, an_handler_t); 1059 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 1060 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1061 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1062 void doom_vi(struct adapter *, struct vi_info *); 1063 void end_synchronized_op(struct adapter *, int); 1064 int update_mac_settings(struct ifnet *, int); 1065 int adapter_full_init(struct adapter *); 1066 int adapter_full_uninit(struct adapter *); 1067 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1068 int vi_full_init(struct vi_info *); 1069 int vi_full_uninit(struct vi_info *); 1070 void vi_sysctls(struct vi_info *); 1071 void vi_tick(void *); 1072 1073 #ifdef DEV_NETMAP 1074 /* t4_netmap.c */ 1075 int create_netmap_ifnet(struct port_info *); 1076 int destroy_netmap_ifnet(struct port_info *); 1077 void t4_nm_intr(void *); 1078 #endif 1079 1080 /* t4_sge.c */ 1081 void t4_sge_modload(void); 1082 void t4_sge_modunload(void); 1083 uint64_t t4_sge_extfree_refs(void); 1084 void t4_init_sge_cpl_handlers(struct adapter *); 1085 void t4_tweak_chip_settings(struct adapter *); 1086 int t4_read_chip_settings(struct adapter *); 1087 int t4_create_dma_tag(struct adapter *); 1088 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1089 struct sysctl_oid_list *); 1090 int t4_destroy_dma_tag(struct adapter *); 1091 int t4_setup_adapter_queues(struct adapter *); 1092 int t4_teardown_adapter_queues(struct adapter *); 1093 int t4_setup_vi_queues(struct vi_info *); 1094 int t4_teardown_vi_queues(struct vi_info *); 1095 void t4_intr_all(void *); 1096 void t4_intr(void *); 1097 void t4_intr_err(void *); 1098 void t4_intr_evt(void *); 1099 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1100 void t4_update_fl_bufsize(struct ifnet *); 1101 int parse_pkt(struct mbuf **); 1102 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1103 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1104 int tnl_cong(struct port_info *, int); 1105 1106 /* t4_tracer.c */ 1107 struct t4_tracer; 1108 void t4_tracer_modload(void); 1109 void t4_tracer_modunload(void); 1110 void t4_tracer_port_detach(struct adapter *); 1111 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1112 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1113 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1114 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1115 1116 static inline struct wrqe * 1117 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1118 { 1119 int len = offsetof(struct wrqe, wr) + wr_len; 1120 struct wrqe *wr; 1121 1122 wr = malloc(len, M_CXGBE, M_NOWAIT); 1123 if (__predict_false(wr == NULL)) 1124 return (NULL); 1125 wr->wr_len = wr_len; 1126 wr->wrq = wrq; 1127 return (wr); 1128 } 1129 1130 static inline void * 1131 wrtod(struct wrqe *wr) 1132 { 1133 return (&wr->wr[0]); 1134 } 1135 1136 static inline void 1137 free_wrqe(struct wrqe *wr) 1138 { 1139 free(wr, M_CXGBE); 1140 } 1141 1142 static inline void 1143 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1144 { 1145 struct sge_wrq *wrq = wr->wrq; 1146 1147 TXQ_LOCK(wrq); 1148 t4_wrq_tx_locked(sc, wrq, wr); 1149 TXQ_UNLOCK(wrq); 1150 } 1151 1152 #endif 1153