1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/counter.h> 37 #include <sys/rman.h> 38 #include <sys/types.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/rwlock.h> 42 #include <sys/seqc.h> 43 #include <sys/sx.h> 44 #include <sys/vmem.h> 45 #include <vm/uma.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <machine/bus.h> 50 #include <sys/socket.h> 51 #include <sys/sysctl.h> 52 #include <sys/taskqueue.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 /* 72 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 73 * LIST_HEAD when building iw_cxgbe. 74 */ 75 #define CXGBE_LIST_HEAD(name, type) \ 76 struct name { \ 77 struct type *lh_first; /* first element */ \ 78 } 79 80 #ifndef SYSCTL_ADD_UQUAD 81 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 82 #define sysctl_handle_64 sysctl_handle_quad 83 #define CTLTYPE_U64 CTLTYPE_QUAD 84 #endif 85 86 SYSCTL_DECL(_hw_cxgbe); 87 88 struct adapter; 89 typedef struct adapter adapter_t; 90 91 enum { 92 /* 93 * All ingress queues use this entry size. Note that the firmware event 94 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 95 * be at least 64. 96 */ 97 IQ_ESIZE = 64, 98 99 /* Default queue sizes for all kinds of ingress queues */ 100 FW_IQ_QSIZE = 256, 101 RX_IQ_QSIZE = 1024, 102 103 /* All egress queues use this entry size */ 104 EQ_ESIZE = 64, 105 106 /* Default queue sizes for all kinds of egress queues */ 107 CTRL_EQ_QSIZE = 1024, 108 TX_EQ_QSIZE = 1024, 109 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 CL_METADATA_SIZE = CACHE_LINE_SIZE, 112 113 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 114 TX_SGL_SEGS = 39, 115 TX_SGL_SEGS_TSO = 38, 116 TX_SGL_SEGS_VM = 38, 117 TX_SGL_SEGS_VM_TSO = 37, 118 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 119 TX_SGL_SEGS_VXLAN_TSO = 37, 120 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 121 }; 122 123 enum { 124 /* adapter intr_type */ 125 INTR_INTX = (1 << 0), 126 INTR_MSI = (1 << 1), 127 INTR_MSIX = (1 << 2) 128 }; 129 130 enum { 131 XGMAC_MTU = (1 << 0), 132 XGMAC_PROMISC = (1 << 1), 133 XGMAC_ALLMULTI = (1 << 2), 134 XGMAC_VLANEX = (1 << 3), 135 XGMAC_UCADDR = (1 << 4), 136 XGMAC_MCADDRS = (1 << 5), 137 138 XGMAC_ALL = 0xffff 139 }; 140 141 enum { 142 /* flags understood by begin_synchronized_op */ 143 HOLD_LOCK = (1 << 0), 144 SLEEP_OK = (1 << 1), 145 INTR_OK = (1 << 2), 146 147 /* flags understood by end_synchronized_op */ 148 LOCK_HELD = HOLD_LOCK, 149 }; 150 151 enum { 152 /* adapter flags. synch_op or adapter_lock. */ 153 FULL_INIT_DONE = (1 << 0), 154 FW_OK = (1 << 1), 155 CHK_MBOX_ACCESS = (1 << 2), 156 MASTER_PF = (1 << 3), 157 BUF_PACKING_OK = (1 << 6), 158 IS_VF = (1 << 7), 159 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 160 CXGBE_BUSY = (1 << 9), 161 162 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 163 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 164 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 165 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 166 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 167 168 /* port flags */ 169 HAS_TRACEQ = (1 << 3), 170 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 171 172 /* VI flags */ 173 DOOMED = (1 << 0), 174 VI_INIT_DONE = (1 << 1), 175 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 176 TX_USES_VM_WR = (1 << 3), 177 VI_SKIP_STATS = (1 << 4), 178 179 /* adapter debug_flags */ 180 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 181 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 182 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 183 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 184 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 185 }; 186 187 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 188 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 189 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 190 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 191 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 192 193 struct vi_info { 194 device_t dev; 195 struct port_info *pi; 196 struct adapter *adapter; 197 198 if_t ifp; 199 struct pfil_head *pfil; 200 201 unsigned long flags; 202 int if_flags; 203 204 uint16_t *rss, *nm_rss; 205 uint16_t viid; /* opaque VI identifier */ 206 uint16_t smt_idx; 207 uint16_t vin; 208 uint8_t vfvld; 209 int16_t xact_addr_filt;/* index of exact MAC address filter */ 210 uint16_t rss_size; /* size of VI's RSS table slice */ 211 uint16_t rss_base; /* start of VI's RSS table slice */ 212 int hashen; 213 214 int nintr; 215 int first_intr; 216 217 /* These need to be int as they are used in sysctl */ 218 int ntxq; /* # of tx queues */ 219 int first_txq; /* index of first tx queue */ 220 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 221 int nrxq; /* # of rx queues */ 222 int first_rxq; /* index of first rx queue */ 223 int nofldtxq; /* # of offload tx queues */ 224 int first_ofld_txq; /* index of first offload tx queue */ 225 int nofldrxq; /* # of offload rx queues */ 226 int first_ofld_rxq; /* index of first offload rx queue */ 227 int nnmtxq; 228 int first_nm_txq; 229 int nnmrxq; 230 int first_nm_rxq; 231 int tmr_idx; 232 int ofld_tmr_idx; 233 int pktc_idx; 234 int ofld_pktc_idx; 235 int qsize_rxq; 236 int qsize_txq; 237 238 struct timeval last_refreshed; 239 struct fw_vi_stats_vf stats; 240 struct mtx tick_mtx; 241 struct callout tick; 242 243 struct sysctl_ctx_list ctx; 244 struct sysctl_oid *rxq_oid; 245 struct sysctl_oid *txq_oid; 246 struct sysctl_oid *nm_rxq_oid; 247 struct sysctl_oid *nm_txq_oid; 248 struct sysctl_oid *ofld_rxq_oid; 249 struct sysctl_oid *ofld_txq_oid; 250 251 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 252 u_int txq_rr; 253 u_int rxq_rr; 254 }; 255 256 struct tx_ch_rl_params { 257 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 258 uint32_t maxrate; 259 }; 260 261 /* CLRL state */ 262 enum clrl_state { 263 CS_UNINITIALIZED = 0, 264 CS_PARAMS_SET, /* sw parameters have been set. */ 265 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 266 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 267 CS_HW_CONFIGURED /* configured in the hardware. */ 268 }; 269 270 /* CLRL flags */ 271 enum { 272 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 273 }; 274 275 struct tx_cl_rl_params { 276 enum clrl_state state; 277 int refcount; 278 uint8_t flags; 279 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 280 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 281 enum fw_sched_params_mode mode; /* aggr or per-flow */ 282 uint32_t maxrate; 283 uint16_t pktsize; 284 uint16_t burstsize; 285 }; 286 287 /* Tx scheduler parameters for a channel/port */ 288 struct tx_sched_params { 289 /* Channel Rate Limiter */ 290 struct tx_ch_rl_params ch_rl; 291 292 /* Class WRR */ 293 /* XXX */ 294 295 /* Class Rate Limiter (including the default pktsize and burstsize). */ 296 int pktsize; 297 int burstsize; 298 struct tx_cl_rl_params cl_rl[]; 299 }; 300 301 struct port_info { 302 device_t dev; 303 struct adapter *adapter; 304 305 struct vi_info *vi; 306 int nvi; 307 int up_vis; 308 int uld_vis; 309 bool vxlan_tcam_entry; 310 311 struct tx_sched_params *sched_params; 312 313 struct mtx pi_lock; 314 char lockname[16]; 315 unsigned long flags; 316 317 uint8_t lport; /* associated offload logical port */ 318 int8_t mdio_addr; 319 uint8_t port_type; 320 uint8_t mod_type; 321 uint8_t port_id; 322 uint8_t tx_chan; 323 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 324 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 325 uint8_t rx_c_chan; /* rx TP c-channel */ 326 327 struct link_config link_cfg; 328 struct ifmedia media; 329 330 struct port_stats stats; 331 u_int tnl_cong_drops; 332 u_int tx_parse_error; 333 int fcs_reg; 334 uint64_t fcs_base; 335 336 struct sysctl_ctx_list ctx; 337 }; 338 339 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 340 341 struct cluster_metadata { 342 uma_zone_t zone; 343 caddr_t cl; 344 u_int refcount; 345 }; 346 347 struct fl_sdesc { 348 caddr_t cl; 349 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 350 int16_t moff; /* offset of metadata from cl */ 351 uint8_t zidx; 352 }; 353 354 struct tx_desc { 355 __be64 flit[8]; 356 }; 357 358 struct tx_sdesc { 359 struct mbuf *m; /* m_nextpkt linked chain of frames */ 360 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 361 }; 362 363 364 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 365 struct iq_desc { 366 struct rss_header rss; 367 uint8_t cpl[IQ_PAD]; 368 struct rsp_ctrl rsp; 369 }; 370 #undef IQ_PAD 371 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 372 373 enum { 374 /* iq type */ 375 IQ_OTHER = FW_IQ_IQTYPE_OTHER, 376 IQ_ETH = FW_IQ_IQTYPE_NIC, 377 IQ_OFLD = FW_IQ_IQTYPE_OFLD, 378 379 /* iq flags */ 380 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 381 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 382 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 383 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 384 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 385 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 386 387 /* iq state */ 388 IQS_DISABLED = 0, 389 IQS_BUSY = 1, 390 IQS_IDLE = 2, 391 392 /* netmap related flags */ 393 NM_OFF = 0, 394 NM_ON = 1, 395 NM_BUSY = 2, 396 }; 397 398 enum { 399 CPL_COOKIE_RESERVED = 0, 400 CPL_COOKIE_FILTER, 401 CPL_COOKIE_DDP0, 402 CPL_COOKIE_DDP1, 403 CPL_COOKIE_TOM, 404 CPL_COOKIE_HASHFILTER, 405 CPL_COOKIE_ETHOFLD, 406 CPL_COOKIE_KERN_TLS, 407 408 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 409 }; 410 411 struct sge_iq; 412 struct rss_header; 413 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 414 struct mbuf *); 415 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 416 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 417 418 /* 419 * Ingress Queue: T4 is producer, driver is consumer. 420 */ 421 struct sge_iq { 422 uint16_t flags; 423 uint8_t qtype; 424 volatile int state; 425 struct adapter *adapter; 426 struct iq_desc *desc; /* KVA of descriptor ring */ 427 int8_t intr_pktc_idx; /* packet count threshold index */ 428 uint8_t gen; /* generation bit */ 429 uint8_t intr_params; /* interrupt holdoff parameters */ 430 int8_t cong_drop; /* congestion drop settings for the queue */ 431 uint16_t qsize; /* size (# of entries) of the queue */ 432 uint16_t sidx; /* index of the entry with the status page */ 433 uint16_t cidx; /* consumer index */ 434 uint16_t cntxt_id; /* SGE context id for the iq */ 435 uint16_t abs_id; /* absolute SGE id for the iq */ 436 int16_t intr_idx; /* interrupt used by the queue */ 437 438 STAILQ_ENTRY(sge_iq) link; 439 440 bus_dma_tag_t desc_tag; 441 bus_dmamap_t desc_map; 442 bus_addr_t ba; /* bus address of descriptor ring */ 443 }; 444 445 enum { 446 /* eq type */ 447 EQ_CTRL = 1, 448 EQ_ETH = 2, 449 EQ_OFLD = 3, 450 451 /* eq flags */ 452 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 453 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 454 EQ_ENABLED = (1 << 3), /* open for business */ 455 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 456 }; 457 458 /* Listed in order of preference. Update t4_sysctls too if you change these */ 459 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 460 461 /* 462 * Egress Queue: driver is producer, T4 is consumer. 463 * 464 * Note: A free list is an egress queue (driver produces the buffers and T4 465 * consumes them) but it's special enough to have its own struct (see sge_fl). 466 */ 467 struct sge_eq { 468 unsigned int flags; /* MUST be first */ 469 unsigned int cntxt_id; /* SGE context id for the eq */ 470 unsigned int abs_id; /* absolute SGE id for the eq */ 471 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 472 uint8_t doorbells; 473 uint8_t tx_chan; /* tx channel used by the eq */ 474 struct mtx eq_lock; 475 476 struct tx_desc *desc; /* KVA of descriptor ring */ 477 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 478 u_int udb_qid; /* relative qid within the doorbell page */ 479 uint16_t sidx; /* index of the entry with the status page */ 480 uint16_t cidx; /* consumer idx (desc idx) */ 481 uint16_t pidx; /* producer idx (desc idx) */ 482 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 483 uint16_t dbidx; /* pidx of the most recent doorbell */ 484 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 485 volatile u_int equiq; /* EQUIQ outstanding */ 486 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 487 488 bus_dma_tag_t desc_tag; 489 bus_dmamap_t desc_map; 490 bus_addr_t ba; /* bus address of descriptor ring */ 491 char lockname[16]; 492 }; 493 494 struct rx_buf_info { 495 uma_zone_t zone; /* zone that this cluster comes from */ 496 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 497 * hwsize[hwidx1] = size1. No spare. */ 498 uint16_t size2; /* hwsize[hwidx2] = size2. 499 * spare in cluster = size1 - size2. */ 500 int8_t hwidx1; /* SGE bufsize idx for size1 */ 501 int8_t hwidx2; /* SGE bufsize idx for size2 */ 502 uint8_t type; /* EXT_xxx type of the cluster */ 503 }; 504 505 enum { 506 NUM_MEMWIN = 3, 507 508 MEMWIN0_APERTURE = 2048, 509 MEMWIN0_BASE = 0x1b800, 510 511 MEMWIN1_APERTURE = 32768, 512 MEMWIN1_BASE = 0x28000, 513 514 MEMWIN2_APERTURE_T4 = 65536, 515 MEMWIN2_BASE_T4 = 0x30000, 516 517 MEMWIN2_APERTURE_T5 = 128 * 1024, 518 MEMWIN2_BASE_T5 = 0x60000, 519 }; 520 521 struct memwin { 522 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 523 uint32_t mw_base; /* constant after setup_memwin */ 524 uint32_t mw_aperture; /* ditto */ 525 uint32_t mw_curpos; /* protected by mw_lock */ 526 }; 527 528 enum { 529 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 530 FL_DOOMED = (1 << 1), /* about to be destroyed */ 531 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 532 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 533 }; 534 535 #define FL_RUNNING_LOW(fl) \ 536 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 537 #define FL_NOT_RUNNING_LOW(fl) \ 538 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 539 540 struct sge_fl { 541 struct mtx fl_lock; 542 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 543 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 544 uint16_t zidx; /* refill zone idx */ 545 uint16_t safe_zidx; 546 uint16_t lowat; /* # of buffers <= this means fl needs help */ 547 int flags; 548 uint16_t buf_boundary; 549 550 /* The 16b idx all deal with hw descriptors */ 551 uint16_t dbidx; /* hw pidx after last doorbell */ 552 uint16_t sidx; /* index of status page */ 553 volatile uint16_t hw_cidx; 554 555 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 556 uint32_t cidx; /* consumer index */ 557 uint32_t pidx; /* producer index */ 558 559 uint32_t dbval; 560 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 561 volatile uint32_t *udb; 562 563 uint64_t cl_allocated; /* # of clusters allocated */ 564 uint64_t cl_recycled; /* # of clusters recycled */ 565 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 566 567 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 568 struct mbuf *m0; 569 struct mbuf **pnext; 570 u_int remaining; 571 572 uint16_t qsize; /* # of hw descriptors (status page included) */ 573 uint16_t cntxt_id; /* SGE context id for the freelist */ 574 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 575 bus_dma_tag_t desc_tag; 576 bus_dmamap_t desc_map; 577 char lockname[16]; 578 bus_addr_t ba; /* bus address of descriptor ring */ 579 }; 580 581 struct mp_ring; 582 583 struct txpkts { 584 uint8_t wr_type; /* type 0 or type 1 */ 585 uint8_t npkt; /* # of packets in this work request */ 586 uint8_t len16; /* # of 16B pieces used by this work request */ 587 uint8_t score; 588 uint8_t max_npkt; /* maximum number of packets allowed */ 589 uint16_t plen; /* total payload (sum of all packets) */ 590 591 /* straight from fw_eth_tx_pkts_vm_wr. */ 592 __u8 ethmacdst[6]; 593 __u8 ethmacsrc[6]; 594 __be16 ethtype; 595 __be16 vlantci; 596 597 struct mbuf *mb[15]; 598 }; 599 600 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 601 struct sge_txq { 602 struct sge_eq eq; /* MUST be first */ 603 604 if_t ifp; /* the interface this txq belongs to */ 605 struct mp_ring *r; /* tx software ring */ 606 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 607 struct sglist *gl; 608 __be32 cpl_ctrl0; /* for convenience */ 609 int tc_idx; /* traffic class */ 610 uint64_t last_tx; /* cycle count when eth_tx was last called */ 611 struct txpkts txp; 612 613 struct task tx_reclaim_task; 614 /* stats for common events first */ 615 616 uint64_t txcsum; /* # of times hardware assisted with checksum */ 617 uint64_t tso_wrs; /* # of TSO work requests */ 618 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 619 uint64_t imm_wrs; /* # of work requests with immediate data */ 620 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 621 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 622 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 623 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 624 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 625 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 626 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 627 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 628 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 629 uint64_t vxlan_txcsum; 630 631 uint64_t kern_tls_records; 632 uint64_t kern_tls_short; 633 uint64_t kern_tls_partial; 634 uint64_t kern_tls_full; 635 uint64_t kern_tls_octets; 636 uint64_t kern_tls_waste; 637 uint64_t kern_tls_options; 638 uint64_t kern_tls_header; 639 uint64_t kern_tls_fin; 640 uint64_t kern_tls_fin_short; 641 uint64_t kern_tls_cbc; 642 uint64_t kern_tls_gcm; 643 644 /* stats for not-that-common events */ 645 646 /* Optional scratch space for constructing work requests. */ 647 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 648 } __aligned(CACHE_LINE_SIZE); 649 650 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 651 struct sge_rxq { 652 struct sge_iq iq; /* MUST be first */ 653 struct sge_fl fl; /* MUST follow iq */ 654 655 if_t ifp; /* the interface this rxq belongs to */ 656 struct lro_ctrl lro; /* LRO state */ 657 658 /* stats for common events first */ 659 660 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 661 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 662 uint64_t vxlan_rxcsum; 663 664 /* stats for not-that-common events */ 665 666 } __aligned(CACHE_LINE_SIZE); 667 668 static inline struct sge_rxq * 669 iq_to_rxq(struct sge_iq *iq) 670 { 671 672 return (__containerof(iq, struct sge_rxq, iq)); 673 } 674 675 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 676 struct sge_ofld_rxq { 677 struct sge_iq iq; /* MUST be first */ 678 struct sge_fl fl; /* MUST follow iq */ 679 counter_u64_t rx_iscsi_ddp_setup_ok; 680 counter_u64_t rx_iscsi_ddp_setup_error; 681 uint64_t rx_iscsi_ddp_pdus; 682 uint64_t rx_iscsi_ddp_octets; 683 uint64_t rx_iscsi_fl_pdus; 684 uint64_t rx_iscsi_fl_octets; 685 uint64_t rx_iscsi_padding_errors; 686 uint64_t rx_iscsi_header_digest_errors; 687 uint64_t rx_iscsi_data_digest_errors; 688 u_long rx_toe_tls_records; 689 u_long rx_toe_tls_octets; 690 } __aligned(CACHE_LINE_SIZE); 691 692 static inline struct sge_ofld_rxq * 693 iq_to_ofld_rxq(struct sge_iq *iq) 694 { 695 696 return (__containerof(iq, struct sge_ofld_rxq, iq)); 697 } 698 699 struct wrqe { 700 STAILQ_ENTRY(wrqe) link; 701 struct sge_wrq *wrq; 702 int wr_len; 703 char wr[] __aligned(16); 704 }; 705 706 struct wrq_cookie { 707 TAILQ_ENTRY(wrq_cookie) link; 708 int ndesc; 709 int pidx; 710 }; 711 712 /* 713 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 714 * are of this type. 715 */ 716 struct sge_wrq { 717 struct sge_eq eq; /* MUST be first */ 718 719 struct adapter *adapter; 720 struct task wrq_tx_task; 721 722 /* Tx desc reserved but WR not "committed" yet. */ 723 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 724 725 /* List of WRs ready to go out as soon as descriptors are available. */ 726 STAILQ_HEAD(, wrqe) wr_list; 727 u_int nwr_pending; 728 u_int ndesc_needed; 729 730 /* stats for common events first */ 731 732 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 733 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 734 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 735 736 /* stats for not-that-common events */ 737 738 /* 739 * Scratch space for work requests that wrap around after reaching the 740 * status page, and some information about the last WR that used it. 741 */ 742 uint16_t ss_pidx; 743 uint16_t ss_len; 744 uint8_t ss[SGE_MAX_WR_LEN]; 745 746 } __aligned(CACHE_LINE_SIZE); 747 748 /* ofld_txq: SGE egress queue + miscellaneous items */ 749 struct sge_ofld_txq { 750 struct sge_wrq wrq; 751 counter_u64_t tx_iscsi_pdus; 752 counter_u64_t tx_iscsi_octets; 753 counter_u64_t tx_iscsi_iso_wrs; 754 counter_u64_t tx_toe_tls_records; 755 counter_u64_t tx_toe_tls_octets; 756 } __aligned(CACHE_LINE_SIZE); 757 758 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 759 struct sge_nm_rxq { 760 /* Items used by the driver rx ithread are in this cacheline. */ 761 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 762 u_int nid; /* netmap ring # for this queue */ 763 struct vi_info *vi; 764 765 struct iq_desc *iq_desc; 766 uint16_t iq_abs_id; 767 uint16_t iq_cntxt_id; 768 uint16_t iq_cidx; 769 uint16_t iq_sidx; 770 uint8_t iq_gen; 771 uint32_t fl_sidx; 772 773 /* Items used by netmap rxsync are in this cacheline. */ 774 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 775 uint16_t fl_cntxt_id; 776 uint32_t fl_pidx; 777 uint32_t fl_sidx2; /* copy of fl_sidx */ 778 uint32_t fl_db_val; 779 u_int fl_db_saved; 780 u_int fl_db_threshold; /* in descriptors */ 781 u_int fl_hwidx:4; 782 783 /* 784 * fl_cidx is used by both the ithread and rxsync, the rest are not used 785 * in the rx fast path. 786 */ 787 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 788 789 bus_dma_tag_t iq_desc_tag; 790 bus_dmamap_t iq_desc_map; 791 bus_addr_t iq_ba; 792 int intr_idx; 793 794 bus_dma_tag_t fl_desc_tag; 795 bus_dmamap_t fl_desc_map; 796 bus_addr_t fl_ba; 797 }; 798 799 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 800 struct sge_nm_txq { 801 struct tx_desc *desc; 802 uint16_t cidx; 803 uint16_t pidx; 804 uint16_t sidx; 805 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 806 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 807 uint16_t dbidx; /* pidx of the most recent doorbell */ 808 uint8_t doorbells; 809 volatile uint32_t *udb; 810 u_int udb_qid; 811 u_int cntxt_id; 812 __be32 cpl_ctrl0; /* for convenience */ 813 __be32 op_pkd; /* ditto */ 814 u_int nid; /* netmap ring # for this queue */ 815 816 /* infrequently used items after this */ 817 818 bus_dma_tag_t desc_tag; 819 bus_dmamap_t desc_map; 820 bus_addr_t ba; 821 int iqidx; 822 } __aligned(CACHE_LINE_SIZE); 823 824 struct sge { 825 int nrxq; /* total # of Ethernet rx queues */ 826 int ntxq; /* total # of Ethernet tx queues */ 827 int nofldrxq; /* total # of TOE rx queues */ 828 int nofldtxq; /* total # of TOE tx queues */ 829 int nnmrxq; /* total # of netmap rx queues */ 830 int nnmtxq; /* total # of netmap tx queues */ 831 int niq; /* total # of ingress queues */ 832 int neq; /* total # of egress queues */ 833 834 struct sge_iq fwq; /* Firmware event queue */ 835 struct sge_wrq *ctrlq; /* Control queues */ 836 struct sge_txq *txq; /* NIC tx queues */ 837 struct sge_rxq *rxq; /* NIC rx queues */ 838 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 839 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 840 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 841 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 842 843 uint16_t iq_start; /* first cntxt_id */ 844 uint16_t iq_base; /* first abs_id */ 845 int eq_start; /* first cntxt_id */ 846 int eq_base; /* first abs_id */ 847 int iqmap_sz; 848 int eqmap_sz; 849 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 850 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 851 852 int8_t safe_zidx; 853 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 854 }; 855 856 struct devnames { 857 const char *nexus_name; 858 const char *ifnet_name; 859 const char *vi_ifnet_name; 860 const char *pf03_drv_name; 861 const char *vf_nexus_name; 862 const char *vf_ifnet_name; 863 }; 864 865 struct clip_entry; 866 867 #define CNT_CAL_INFO 3 868 struct clock_sync { 869 uint64_t hw_cur; 870 uint64_t hw_prev; 871 sbintime_t sbt_cur; 872 sbintime_t sbt_prev; 873 seqc_t gen; 874 }; 875 876 struct adapter { 877 SLIST_ENTRY(adapter) link; 878 device_t dev; 879 struct cdev *cdev; 880 const struct devnames *names; 881 882 /* PCIe register resources */ 883 int regs_rid; 884 struct resource *regs_res; 885 int msix_rid; 886 struct resource *msix_res; 887 bus_space_handle_t bh; 888 bus_space_tag_t bt; 889 bus_size_t mmio_len; 890 int udbs_rid; 891 struct resource *udbs_res; 892 volatile uint8_t *udbs_base; 893 894 unsigned int pf; 895 unsigned int mbox; 896 unsigned int vpd_busy; 897 unsigned int vpd_flag; 898 899 /* Interrupt information */ 900 int intr_type; 901 int intr_count; 902 struct irq { 903 struct resource *res; 904 int rid; 905 void *tag; 906 struct sge_rxq *rxq; 907 struct sge_nm_rxq *nm_rxq; 908 } __aligned(CACHE_LINE_SIZE) *irq; 909 int sge_gts_reg; 910 int sge_kdoorbell_reg; 911 912 bus_dma_tag_t dmat; /* Parent DMA tag */ 913 914 struct sge sge; 915 int lro_timeout; 916 int sc_do_rxcopy; 917 918 int vxlan_port; 919 u_int vxlan_refcount; 920 int rawf_base; 921 int nrawf; 922 923 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 924 struct port_info *port[MAX_NPORTS]; 925 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 926 927 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 928 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 929 u_long clip_mask; 930 int clip_gen; 931 struct timeout_task clip_task; 932 933 void *tom_softc; /* (struct tom_data *) */ 934 struct tom_tunables tt; 935 struct t4_offload_policy *policy; 936 struct rwlock policy_lock; 937 938 void *iwarp_softc; /* (struct c4iw_dev *) */ 939 struct iw_tunables iwt; 940 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 941 struct l2t_data *l2t; /* L2 table */ 942 struct smt_data *smt; /* Source MAC Table */ 943 struct tid_info tids; 944 vmem_t *key_map; 945 struct tls_tunables tlst; 946 947 uint8_t doorbells; 948 int offload_map; /* port_id's with IFCAP_TOE enabled */ 949 int bt_map; /* tx_chan's with BASE-T */ 950 int active_ulds; /* ULDs activated on this adapter */ 951 int flags; 952 int debug_flags; 953 int error_flags; /* Used by error handler and live reset. */ 954 955 char ifp_lockname[16]; 956 struct mtx ifp_lock; 957 if_t ifp; /* tracer ifp */ 958 struct ifmedia media; 959 int traceq; /* iq used by all tracers, -1 if none */ 960 int tracer_valid; /* bitmap of valid tracers */ 961 int tracer_enabled; /* bitmap of enabled tracers */ 962 963 char fw_version[16]; 964 char tp_version[16]; 965 char er_version[16]; 966 char bs_version[16]; 967 char cfg_file[32]; 968 u_int cfcsum; 969 struct adapter_params params; 970 const struct chip_params *chip_params; 971 struct t4_virt_res vres; 972 973 uint16_t nbmcaps; 974 uint16_t linkcaps; 975 uint16_t switchcaps; 976 uint16_t niccaps; 977 uint16_t toecaps; 978 uint16_t rdmacaps; 979 uint16_t cryptocaps; 980 uint16_t iscsicaps; 981 uint16_t fcoecaps; 982 983 struct sysctl_ctx_list ctx; 984 struct sysctl_oid *ctrlq_oid; 985 struct sysctl_oid *fwq_oid; 986 987 struct mtx sc_lock; 988 char lockname[16]; 989 990 /* Starving free lists */ 991 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 992 TAILQ_HEAD(, sge_fl) sfl; 993 struct callout sfl_callout; 994 struct callout cal_callout; 995 struct clock_sync cal_info[CNT_CAL_INFO]; 996 int cal_current; 997 int cal_count; 998 uint32_t cal_gen; 999 1000 /* 1001 * Driver code that can run when the adapter is suspended must use this 1002 * lock or a synchronized_op and check for HW_OFF_LIMITS before 1003 * accessing hardware. 1004 * 1005 * XXX: could be changed to rwlock. wlock in suspend/resume and for 1006 * indirect register access, rlock everywhere else. 1007 */ 1008 struct mtx reg_lock; 1009 1010 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 1011 1012 struct mtx tc_lock; 1013 struct task tc_task; 1014 1015 struct task fatal_error_task; 1016 struct task reset_task; 1017 const void *reset_thread; 1018 int num_resets; 1019 int incarnation; 1020 1021 const char *last_op; 1022 const void *last_op_thr; 1023 int last_op_flags; 1024 1025 int swintr; 1026 int sensor_resets; 1027 1028 struct callout ktls_tick; 1029 }; 1030 1031 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1032 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1033 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1034 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1035 1036 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1037 KASSERT(IS_BUSY(sc) && \ 1038 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1039 ("%s: operation not synchronized.", __func__)) 1040 1041 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1042 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1043 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1044 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1045 1046 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1047 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1048 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1049 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1050 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1051 1052 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1053 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1054 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1055 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1056 1057 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1058 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1059 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1060 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1061 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1062 1063 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1064 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1065 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1066 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1067 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1068 1069 #define for_each_txq(vi, iter, q) \ 1070 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1071 iter < vi->ntxq; ++iter, ++q) 1072 #define for_each_rxq(vi, iter, q) \ 1073 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1074 iter < vi->nrxq; ++iter, ++q) 1075 #define for_each_ofld_txq(vi, iter, q) \ 1076 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1077 iter < vi->nofldtxq; ++iter, ++q) 1078 #define for_each_ofld_rxq(vi, iter, q) \ 1079 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1080 iter < vi->nofldrxq; ++iter, ++q) 1081 #define for_each_nm_txq(vi, iter, q) \ 1082 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1083 iter < vi->nnmtxq; ++iter, ++q) 1084 #define for_each_nm_rxq(vi, iter, q) \ 1085 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1086 iter < vi->nnmrxq; ++iter, ++q) 1087 #define for_each_vi(_pi, _iter, _vi) \ 1088 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1089 ++(_iter), ++(_vi)) 1090 1091 #define IDXINCR(idx, incr, wrap) do { \ 1092 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1093 } while (0) 1094 #define IDXDIFF(head, tail, wrap) \ 1095 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1096 1097 /* One for errors, one for firmware events */ 1098 #define T4_EXTRA_INTR 2 1099 1100 /* One for firmware events */ 1101 #define T4VF_EXTRA_INTR 1 1102 1103 static inline int 1104 forwarding_intr_to_fwq(struct adapter *sc) 1105 { 1106 1107 return (sc->intr_count == 1); 1108 } 1109 1110 /* Works reliably inside a sync_op or with reg_lock held. */ 1111 static inline bool 1112 hw_off_limits(struct adapter *sc) 1113 { 1114 int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1115 1116 return (__predict_false(off_limits != 0)); 1117 } 1118 1119 static inline int 1120 mbuf_nsegs(struct mbuf *m) 1121 { 1122 M_ASSERTPKTHDR(m); 1123 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 1124 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1125 1126 return (m->m_pkthdr.inner_l5hlen); 1127 } 1128 1129 static inline void 1130 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1131 { 1132 M_ASSERTPKTHDR(m); 1133 m->m_pkthdr.inner_l5hlen = nsegs; 1134 } 1135 1136 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 1137 #define MC_NOMAP 0x01 1138 #define MC_RAW_WR 0x02 1139 #define MC_TLS 0x04 1140 1141 static inline int 1142 mbuf_cflags(struct mbuf *m) 1143 { 1144 M_ASSERTPKTHDR(m); 1145 return (m->m_pkthdr.PH_loc.eight[4]); 1146 } 1147 1148 static inline void 1149 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 1150 { 1151 M_ASSERTPKTHDR(m); 1152 m->m_pkthdr.PH_loc.eight[4] = flags; 1153 } 1154 1155 static inline int 1156 mbuf_len16(struct mbuf *m) 1157 { 1158 int n; 1159 1160 M_ASSERTPKTHDR(m); 1161 n = m->m_pkthdr.PH_loc.eight[0]; 1162 if (!(mbuf_cflags(m) & MC_TLS)) 1163 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1164 1165 return (n); 1166 } 1167 1168 static inline void 1169 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1170 { 1171 M_ASSERTPKTHDR(m); 1172 if (!(mbuf_cflags(m) & MC_TLS)) 1173 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 1174 m->m_pkthdr.PH_loc.eight[0] = len16; 1175 } 1176 1177 static inline uint32_t 1178 t4_read_reg(struct adapter *sc, uint32_t reg) 1179 { 1180 if (hw_off_limits(sc)) 1181 MPASS(curthread == sc->reset_thread); 1182 return bus_space_read_4(sc->bt, sc->bh, reg); 1183 } 1184 1185 static inline void 1186 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1187 { 1188 if (hw_off_limits(sc)) 1189 MPASS(curthread == sc->reset_thread); 1190 bus_space_write_4(sc->bt, sc->bh, reg, val); 1191 } 1192 1193 static inline uint64_t 1194 t4_read_reg64(struct adapter *sc, uint32_t reg) 1195 { 1196 if (hw_off_limits(sc)) 1197 MPASS(curthread == sc->reset_thread); 1198 #ifdef __LP64__ 1199 return bus_space_read_8(sc->bt, sc->bh, reg); 1200 #else 1201 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1202 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1203 1204 #endif 1205 } 1206 1207 static inline void 1208 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1209 { 1210 if (hw_off_limits(sc)) 1211 MPASS(curthread == sc->reset_thread); 1212 #ifdef __LP64__ 1213 bus_space_write_8(sc->bt, sc->bh, reg, val); 1214 #else 1215 bus_space_write_4(sc->bt, sc->bh, reg, val); 1216 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1217 #endif 1218 } 1219 1220 static inline void 1221 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1222 { 1223 if (hw_off_limits(sc)) 1224 MPASS(curthread == sc->reset_thread); 1225 *val = pci_read_config(sc->dev, reg, 1); 1226 } 1227 1228 static inline void 1229 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1230 { 1231 if (hw_off_limits(sc)) 1232 MPASS(curthread == sc->reset_thread); 1233 pci_write_config(sc->dev, reg, val, 1); 1234 } 1235 1236 static inline void 1237 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1238 { 1239 1240 if (hw_off_limits(sc)) 1241 MPASS(curthread == sc->reset_thread); 1242 *val = pci_read_config(sc->dev, reg, 2); 1243 } 1244 1245 static inline void 1246 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1247 { 1248 if (hw_off_limits(sc)) 1249 MPASS(curthread == sc->reset_thread); 1250 pci_write_config(sc->dev, reg, val, 2); 1251 } 1252 1253 static inline void 1254 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1255 { 1256 if (hw_off_limits(sc)) 1257 MPASS(curthread == sc->reset_thread); 1258 *val = pci_read_config(sc->dev, reg, 4); 1259 } 1260 1261 static inline void 1262 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1263 { 1264 if (hw_off_limits(sc)) 1265 MPASS(curthread == sc->reset_thread); 1266 pci_write_config(sc->dev, reg, val, 4); 1267 } 1268 1269 static inline struct port_info * 1270 adap2pinfo(struct adapter *sc, int idx) 1271 { 1272 1273 return (sc->port[idx]); 1274 } 1275 1276 static inline void 1277 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1278 { 1279 1280 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1281 } 1282 1283 static inline int 1284 tx_resume_threshold(struct sge_eq *eq) 1285 { 1286 1287 /* not quite the same as qsize / 4, but this will do. */ 1288 return (eq->sidx / 4); 1289 } 1290 1291 static inline int 1292 t4_use_ldst(struct adapter *sc) 1293 { 1294 1295 #ifdef notyet 1296 return (sc->flags & FW_OK || !sc->use_bd); 1297 #else 1298 return (0); 1299 #endif 1300 } 1301 1302 static inline void 1303 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1304 const char *msg, const __be64 *const p, const bool err) 1305 { 1306 1307 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1308 return; 1309 if (p != NULL) { 1310 log(err ? LOG_ERR : LOG_DEBUG, 1311 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1312 "%016llx %016llx %016llx %016llx\n", 1313 device_get_nameunit(sc->dev), mbox, msg, 1314 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1315 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1316 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1317 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1318 } else { 1319 log(err ? LOG_ERR : LOG_DEBUG, 1320 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1321 "%016llx %016llx %016llx %016llx\n", 1322 device_get_nameunit(sc->dev), mbox, msg, 1323 (long long)t4_read_reg64(sc, reg), 1324 (long long)t4_read_reg64(sc, reg + 8), 1325 (long long)t4_read_reg64(sc, reg + 16), 1326 (long long)t4_read_reg64(sc, reg + 24), 1327 (long long)t4_read_reg64(sc, reg + 32), 1328 (long long)t4_read_reg64(sc, reg + 40), 1329 (long long)t4_read_reg64(sc, reg + 48), 1330 (long long)t4_read_reg64(sc, reg + 56)); 1331 } 1332 } 1333 1334 /* t4_main.c */ 1335 extern int t4_ntxq; 1336 extern int t4_nrxq; 1337 extern int t4_intr_types; 1338 extern int t4_tmr_idx; 1339 extern int t4_pktc_idx; 1340 extern unsigned int t4_qsize_rxq; 1341 extern unsigned int t4_qsize_txq; 1342 extern device_method_t cxgbe_methods[]; 1343 1344 int t4_os_find_pci_capability(struct adapter *, int); 1345 int t4_os_pci_save_state(struct adapter *); 1346 int t4_os_pci_restore_state(struct adapter *); 1347 void t4_os_portmod_changed(struct port_info *); 1348 void t4_os_link_changed(struct port_info *); 1349 void t4_iterate(void (*)(struct adapter *, void *), void *); 1350 void t4_init_devnames(struct adapter *); 1351 void t4_add_adapter(struct adapter *); 1352 int t4_detach_common(device_t); 1353 int t4_map_bars_0_and_4(struct adapter *); 1354 int t4_map_bar_2(struct adapter *); 1355 int t4_setup_intr_handlers(struct adapter *); 1356 void t4_sysctls(struct adapter *); 1357 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1358 void doom_vi(struct adapter *, struct vi_info *); 1359 void end_synchronized_op(struct adapter *, int); 1360 int update_mac_settings(if_t, int); 1361 int adapter_init(struct adapter *); 1362 int vi_init(struct vi_info *); 1363 void vi_sysctls(struct vi_info *); 1364 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1365 int alloc_atid(struct adapter *, void *); 1366 void *lookup_atid(struct adapter *, int); 1367 void free_atid(struct adapter *, int); 1368 void release_tid(struct adapter *, int, struct sge_wrq *); 1369 int cxgbe_media_change(if_t); 1370 void cxgbe_media_status(if_t, struct ifmediareq *); 1371 void t4_os_cim_err(struct adapter *); 1372 1373 #ifdef KERN_TLS 1374 /* t6_kern_tls.c */ 1375 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1376 struct m_snd_tag **); 1377 void t6_ktls_modload(void); 1378 void t6_ktls_modunload(void); 1379 int t6_ktls_try(if_t, struct socket *, struct ktls_session *); 1380 int t6_ktls_parse_pkt(struct mbuf *); 1381 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1382 #endif 1383 1384 /* t4_keyctx.c */ 1385 struct auth_hash; 1386 union authctx; 1387 #ifdef KERN_TLS 1388 struct ktls_session; 1389 struct tls_key_req; 1390 struct tls_keyctx; 1391 #endif 1392 1393 void t4_aes_getdeckey(void *, const void *, unsigned int); 1394 void t4_copy_partial_hash(int, union authctx *, void *); 1395 void t4_init_gmac_hash(const char *, int, char *); 1396 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1397 char *); 1398 #ifdef KERN_TLS 1399 u_int t4_tls_key_info_size(const struct ktls_session *); 1400 int t4_tls_proto_ver(const struct ktls_session *); 1401 int t4_tls_cipher_mode(const struct ktls_session *); 1402 int t4_tls_auth_mode(const struct ktls_session *); 1403 int t4_tls_hmac_ctrl(const struct ktls_session *); 1404 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1405 int t4_alloc_tls_keyid(struct adapter *); 1406 void t4_free_tls_keyid(struct adapter *, int); 1407 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1408 struct tls_key_req *); 1409 #endif 1410 1411 #ifdef DEV_NETMAP 1412 /* t4_netmap.c */ 1413 struct sge_nm_rxq; 1414 void cxgbe_nm_attach(struct vi_info *); 1415 void cxgbe_nm_detach(struct vi_info *); 1416 void service_nm_rxq(struct sge_nm_rxq *); 1417 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1418 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1419 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1420 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1421 #endif 1422 1423 /* t4_sge.c */ 1424 void t4_sge_modload(void); 1425 void t4_sge_modunload(void); 1426 uint64_t t4_sge_extfree_refs(void); 1427 void t4_tweak_chip_settings(struct adapter *); 1428 int t4_verify_chip_settings(struct adapter *); 1429 void t4_init_rx_buf_info(struct adapter *); 1430 int t4_create_dma_tag(struct adapter *); 1431 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1432 struct sysctl_oid_list *); 1433 int t4_destroy_dma_tag(struct adapter *); 1434 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1435 bus_addr_t *, void **); 1436 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1437 void *); 1438 void free_fl_buffers(struct adapter *, struct sge_fl *); 1439 int t4_setup_adapter_queues(struct adapter *); 1440 int t4_teardown_adapter_queues(struct adapter *); 1441 int t4_setup_vi_queues(struct vi_info *); 1442 int t4_teardown_vi_queues(struct vi_info *); 1443 void t4_intr_all(void *); 1444 void t4_intr(void *); 1445 #ifdef DEV_NETMAP 1446 void t4_nm_intr(void *); 1447 void t4_vi_intr(void *); 1448 #endif 1449 void t4_intr_err(void *); 1450 void t4_intr_evt(void *); 1451 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1452 void t4_update_fl_bufsize(if_t); 1453 struct mbuf *alloc_wr_mbuf(int, int); 1454 int parse_pkt(struct mbuf **, bool); 1455 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1456 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1457 int t4_sge_set_conm_context(struct adapter *, int, int, int); 1458 void t4_register_an_handler(an_handler_t); 1459 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1460 void t4_register_cpl_handler(int, cpl_handler_t); 1461 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1462 #ifdef RATELIMIT 1463 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1464 #endif 1465 1466 /* t4_tracer.c */ 1467 struct t4_tracer; 1468 void t4_tracer_modload(void); 1469 void t4_tracer_modunload(void); 1470 void t4_tracer_port_detach(struct adapter *); 1471 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1472 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1473 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1474 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1475 1476 /* t4_sched.c */ 1477 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1478 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1479 int t4_init_tx_sched(struct adapter *); 1480 int t4_free_tx_sched(struct adapter *); 1481 void t4_update_tx_sched(struct adapter *); 1482 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1483 void t4_release_cl_rl(struct adapter *, int, int); 1484 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1485 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1486 #ifdef RATELIMIT 1487 void t4_init_etid_table(struct adapter *); 1488 void t4_free_etid_table(struct adapter *); 1489 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1490 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1491 struct m_snd_tag **); 1492 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1493 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *); 1494 #endif 1495 1496 /* t4_filter.c */ 1497 int get_filter_mode(struct adapter *, uint32_t *); 1498 int set_filter_mode(struct adapter *, uint32_t); 1499 int set_filter_mask(struct adapter *, uint32_t); 1500 int get_filter(struct adapter *, struct t4_filter *); 1501 int set_filter(struct adapter *, struct t4_filter *); 1502 int del_filter(struct adapter *, struct t4_filter *); 1503 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1504 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1505 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1506 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1507 void free_hftid_hash(struct tid_info *); 1508 1509 static inline struct wrqe * 1510 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1511 { 1512 int len = offsetof(struct wrqe, wr) + wr_len; 1513 struct wrqe *wr; 1514 1515 wr = malloc(len, M_CXGBE, M_NOWAIT); 1516 if (__predict_false(wr == NULL)) 1517 return (NULL); 1518 wr->wr_len = wr_len; 1519 wr->wrq = wrq; 1520 return (wr); 1521 } 1522 1523 static inline void * 1524 wrtod(struct wrqe *wr) 1525 { 1526 return (&wr->wr[0]); 1527 } 1528 1529 static inline void 1530 free_wrqe(struct wrqe *wr) 1531 { 1532 free(wr, M_CXGBE); 1533 } 1534 1535 static inline void 1536 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1537 { 1538 struct sge_wrq *wrq = wr->wrq; 1539 1540 TXQ_LOCK(wrq); 1541 t4_wrq_tx_locked(sc, wrq, wr); 1542 TXQ_UNLOCK(wrq); 1543 } 1544 1545 static inline int 1546 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1547 int len) 1548 { 1549 1550 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1551 } 1552 1553 static inline int 1554 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1555 const uint32_t *val, int len) 1556 { 1557 1558 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1559 } 1560 1561 /* Number of len16 -> number of descriptors */ 1562 static inline int 1563 tx_len16_to_desc(int len16) 1564 { 1565 1566 return (howmany(len16, EQ_ESIZE / 16)); 1567 } 1568 #endif 1569