1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/bus.h> 35 #include <sys/rman.h> 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcireg.h> 40 #include <machine/bus.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_media.h> 46 #include <netinet/tcp_lro.h> 47 48 #include "offload.h" 49 #include "common/t4fw_interface.h" 50 51 #define T4_FWNAME "t4fw" 52 53 MALLOC_DECLARE(M_CXGBE); 54 #define CXGBE_UNIMPLEMENTED(s) \ 55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56 57 #if defined(__i386__) || defined(__amd64__) 58 static __inline void 59 prefetch(void *x) 60 { 61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62 } 63 #else 64 #define prefetch(x) 65 #endif 66 67 #ifdef __amd64__ 68 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 69 static __inline uint64_t 70 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 71 bus_size_t offset) 72 { 73 KASSERT(tag == X86_BUS_SPACE_IO, 74 ("64-bit reads from I/O space not possible.")); 75 76 return (*(volatile uint64_t *)(handle + offset)); 77 } 78 79 static __inline void 80 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 81 bus_size_t offset, uint64_t value) 82 { 83 KASSERT(tag == X86_BUS_SPACE_IO, 84 ("64-bit writes to I/O space not possible.")); 85 *(volatile uint64_t *)(bsh + offset) = value; 86 } 87 #else 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 return (uint64_t)bus_space_read_4(tag, handle, offset) + 93 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 94 } 95 96 static __inline void 97 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 98 bus_size_t offset, uint64_t value) 99 { 100 bus_space_write_4(tag, bsh, offset, value); 101 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 102 } 103 #endif 104 105 struct adapter; 106 typedef struct adapter adapter_t; 107 108 enum { 109 FW_IQ_QSIZE = 256, 110 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 111 112 RX_IQ_QSIZE = 1024, 113 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 114 115 RX_FL_ESIZE = 64, /* 8 64bit addresses */ 116 117 FL_BUF_SIZES = 4, 118 119 TX_EQ_QSIZE = 1024, 120 TX_EQ_ESIZE = 64, 121 TX_SGL_SEGS = 36, 122 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 123 }; 124 125 enum { 126 /* adapter flags */ 127 FULL_INIT_DONE = (1 << 0), 128 FW_OK = (1 << 1), 129 INTR_FWD = (1 << 2), 130 131 CXGBE_BUSY = (1 << 9), 132 133 /* port flags */ 134 DOOMED = (1 << 0), 135 VI_ENABLED = (1 << 1), 136 }; 137 138 #define IS_DOOMED(pi) (pi->flags & DOOMED) 139 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 140 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 141 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 142 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 143 144 struct port_info { 145 device_t dev; 146 struct adapter *adapter; 147 148 struct ifnet *ifp; 149 struct ifmedia media; 150 151 struct mtx pi_lock; 152 char lockname[16]; 153 unsigned long flags; 154 int if_flags; 155 156 uint16_t viid; 157 int16_t xact_addr_filt;/* index of exact MAC address filter */ 158 uint16_t rss_size; /* size of VI's RSS table slice */ 159 uint8_t lport; /* associated offload logical port */ 160 int8_t mdio_addr; 161 uint8_t port_type; 162 uint8_t mod_type; 163 uint8_t port_id; 164 uint8_t tx_chan; 165 166 /* These need to be int as they are used in sysctl */ 167 int ntxq; /* # of tx queues */ 168 int first_txq; /* index of first tx queue */ 169 int nrxq; /* # of rx queues */ 170 int first_rxq; /* index of first rx queue */ 171 int tmr_idx; 172 int pktc_idx; 173 int qsize_rxq; 174 int qsize_txq; 175 176 struct link_config link_cfg; 177 struct port_stats stats; 178 179 struct callout tick; 180 struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */ 181 struct sysctl_oid *oid_rxq; 182 struct sysctl_oid *oid_txq; 183 184 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 185 }; 186 187 struct fl_sdesc { 188 struct mbuf *m; 189 bus_dmamap_t map; 190 caddr_t cl; 191 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 192 #ifdef INVARIANTS 193 __be64 ba_tag; 194 #endif 195 }; 196 197 struct tx_desc { 198 __be64 flit[8]; 199 }; 200 201 struct tx_map { 202 struct mbuf *m; 203 bus_dmamap_t map; 204 }; 205 206 struct tx_sdesc { 207 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 208 uint8_t map_used; /* # of frames sent out in the WR */ 209 }; 210 211 typedef void (iq_intr_handler_t)(void *); 212 213 enum { 214 /* iq flags */ 215 IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ 216 IQ_STARTED = (1 << 2), /* started */ 217 }; 218 219 /* 220 * Ingress Queue: T4 is producer, driver is consumer. 221 */ 222 struct sge_iq { 223 bus_dma_tag_t desc_tag; 224 bus_dmamap_t desc_map; 225 struct mtx iq_lock; 226 char lockname[16]; 227 unsigned int flags; 228 struct adapter *adapter; 229 230 __be64 *desc; /* KVA of descriptor ring */ 231 bus_addr_t ba; /* bus address of descriptor ring */ 232 const __be64 *cdesc; /* current descriptor */ 233 uint8_t gen; /* generation bit */ 234 uint8_t intr_params; /* interrupt holdoff parameters */ 235 int8_t intr_pktc_idx; /* packet count threshold index */ 236 uint8_t intr_next; /* holdoff for next interrupt */ 237 uint8_t esize; /* size (bytes) of each entry in the queue */ 238 uint16_t qsize; /* size (# of entries) of the queue */ 239 uint16_t cidx; /* consumer index */ 240 uint16_t cntxt_id; /* SGE context id for the iq */ 241 uint16_t abs_id; /* absolute SGE id for the iq */ 242 iq_intr_handler_t *handler; 243 }; 244 245 enum { 246 /* eq flags */ 247 EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ 248 EQ_STARTED = (1 << 2), /* started */ 249 EQ_STALLED = (1 << 3), /* currently stalled */ 250 }; 251 252 /* 253 * Egress Queue: driver is producer, T4 is consumer. 254 * 255 * Note: A free list is an egress queue (driver produces the buffers and T4 256 * consumes them) but it's special enough to have its own struct (see sge_fl). 257 */ 258 struct sge_eq { 259 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 260 bus_dma_tag_t desc_tag; 261 bus_dmamap_t desc_map; 262 char lockname[16]; 263 unsigned int flags; 264 struct mtx eq_lock; 265 266 struct tx_desc *desc; /* KVA of descriptor ring */ 267 bus_addr_t ba; /* bus address of descriptor ring */ 268 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 269 struct buf_ring *br; /* tx buffer ring */ 270 struct sge_qstat *spg; /* status page, for convenience */ 271 uint16_t cap; /* max # of desc, for convenience */ 272 uint16_t avail; /* available descriptors, for convenience */ 273 uint16_t qsize; /* size (# of entries) of the queue */ 274 uint16_t cidx; /* consumer idx (desc idx) */ 275 uint16_t pidx; /* producer idx (desc idx) */ 276 uint16_t pending; /* # of descriptors used since last doorbell */ 277 uint32_t cntxt_id; /* SGE context id for the eq */ 278 279 /* DMA maps used for tx */ 280 struct tx_map *maps; 281 uint32_t map_total; /* # of DMA maps */ 282 uint32_t map_pidx; /* next map to be used */ 283 uint32_t map_cidx; /* reclaimed up to this index */ 284 uint32_t map_avail; /* # of available maps */ 285 } __aligned(CACHE_LINE_SIZE); 286 287 struct sge_fl { 288 bus_dma_tag_t desc_tag; 289 bus_dmamap_t desc_map; 290 bus_dma_tag_t tag[FL_BUF_SIZES]; 291 uint8_t tag_idx; 292 struct mtx fl_lock; 293 char lockname[16]; 294 295 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 296 bus_addr_t ba; /* bus address of descriptor ring */ 297 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 298 uint32_t cap; /* max # of buffers, for convenience */ 299 uint16_t qsize; /* size (# of entries) of the queue */ 300 uint16_t cntxt_id; /* SGE context id for the freelist */ 301 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 302 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 303 uint32_t needed; /* # of buffers needed to fill up fl. */ 304 uint32_t pending; /* # of bufs allocated since last doorbell */ 305 unsigned int dmamap_failed; 306 }; 307 308 /* txq: SGE egress queue + miscellaneous items */ 309 struct sge_txq { 310 struct sge_eq eq; /* MUST be first */ 311 struct mbuf *m; /* held up due to temporary resource shortage */ 312 313 /* stats for common events first */ 314 315 uint64_t txcsum; /* # of times hardware assisted with checksum */ 316 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 317 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 318 uint64_t imm_wrs; /* # of work requests with immediate data */ 319 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 320 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 321 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 322 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 323 324 /* stats for not-that-common events */ 325 326 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 327 uint32_t no_desc; /* out of hardware descriptors */ 328 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */ 329 }; 330 331 enum { 332 RXQ_LRO_ENABLED = (1 << 0) 333 }; 334 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 335 struct sge_rxq { 336 struct sge_iq iq; /* MUST be first */ 337 struct sge_fl fl; 338 339 unsigned int flags; 340 struct port_info *port; /* the port this rxq belongs to */ 341 struct lro_ctrl lro; /* LRO state */ 342 343 /* stats for common events first */ 344 345 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 346 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 347 348 /* stats for not-that-common events */ 349 350 } __aligned(CACHE_LINE_SIZE); 351 352 struct sge { 353 uint16_t timer_val[SGE_NTIMERS]; 354 uint8_t counter_val[SGE_NCOUNTERS]; 355 356 int nrxq; /* total rx queues (all ports and the rest) */ 357 int ntxq; /* total tx queues (all ports and the rest) */ 358 int niq; /* total ingress queues */ 359 int neq; /* total egress queues */ 360 361 struct sge_iq fwq; /* Firmware event queue */ 362 struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */ 363 struct sge_txq *txq; /* NIC tx queues */ 364 struct sge_rxq *rxq; /* NIC rx queues */ 365 366 uint16_t iq_start; 367 int eq_start; 368 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 369 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 370 }; 371 372 struct adapter { 373 device_t dev; 374 struct cdev *cdev; 375 376 /* PCIe register resources */ 377 int regs_rid; 378 struct resource *regs_res; 379 int msix_rid; 380 struct resource *msix_res; 381 bus_space_handle_t bh; 382 bus_space_tag_t bt; 383 bus_size_t mmio_len; 384 385 unsigned int pf; 386 unsigned int mbox; 387 388 /* Interrupt information */ 389 int intr_type; 390 int intr_count; 391 struct irq { 392 struct resource *res; 393 int rid; 394 void *tag; 395 } *irq; 396 397 bus_dma_tag_t dmat; /* Parent DMA tag */ 398 399 struct sge sge; 400 401 struct port_info *port[MAX_NPORTS]; 402 uint8_t chan_map[NCHAN]; 403 404 struct tid_info tids; 405 406 int registered_device_map; 407 int open_device_map; 408 int flags; 409 410 char fw_version[32]; 411 struct adapter_params params; 412 struct t4_virt_res vres; 413 414 struct mtx sc_lock; 415 char lockname[16]; 416 }; 417 418 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 419 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 420 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 421 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 422 423 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 424 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 425 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 426 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 427 428 #define IQ_LOCK(iq) mtx_lock(&(iq)->iq_lock) 429 #define IQ_UNLOCK(iq) mtx_unlock(&(iq)->iq_lock) 430 #define IQ_LOCK_ASSERT_OWNED(iq) mtx_assert(&(iq)->iq_lock, MA_OWNED) 431 #define IQ_LOCK_ASSERT_NOTOWNED(iq) mtx_assert(&(iq)->iq_lock, MA_NOTOWNED) 432 433 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 434 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 435 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 436 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 437 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 438 439 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 440 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 441 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 442 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 443 444 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 445 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 446 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 447 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 448 449 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 450 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 451 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 452 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 453 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 454 455 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 456 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 457 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 458 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 459 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 460 461 #define for_each_txq(pi, iter, txq) \ 462 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 463 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 464 #define for_each_rxq(pi, iter, rxq) \ 465 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 466 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 467 468 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 469 470 static inline uint32_t 471 t4_read_reg(struct adapter *sc, uint32_t reg) 472 { 473 return bus_space_read_4(sc->bt, sc->bh, reg); 474 } 475 476 static inline void 477 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 478 { 479 bus_space_write_4(sc->bt, sc->bh, reg, val); 480 } 481 482 static inline uint64_t 483 t4_read_reg64(struct adapter *sc, uint32_t reg) 484 { 485 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 486 } 487 488 static inline void 489 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 490 { 491 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 492 } 493 494 static inline void 495 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 496 { 497 *val = pci_read_config(sc->dev, reg, 1); 498 } 499 500 static inline void 501 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 502 { 503 pci_write_config(sc->dev, reg, val, 1); 504 } 505 506 static inline void 507 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 508 { 509 *val = pci_read_config(sc->dev, reg, 2); 510 } 511 512 static inline void 513 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 514 { 515 pci_write_config(sc->dev, reg, val, 2); 516 } 517 518 static inline void 519 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 520 { 521 *val = pci_read_config(sc->dev, reg, 4); 522 } 523 524 static inline void 525 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 526 { 527 pci_write_config(sc->dev, reg, val, 4); 528 } 529 530 static inline struct port_info * 531 adap2pinfo(struct adapter *sc, int idx) 532 { 533 return (sc->port[idx]); 534 } 535 536 static inline void 537 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 538 { 539 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 540 } 541 542 static inline bool is_10G_port(const struct port_info *pi) 543 { 544 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 545 } 546 547 int t4_os_find_pci_capability(struct adapter *, int); 548 int t4_os_pci_save_state(struct adapter *); 549 int t4_os_pci_restore_state(struct adapter *); 550 551 void t4_os_portmod_changed(const struct adapter *, int); 552 void t4_os_link_changed(struct adapter *, int, int); 553 554 void t4_sge_init(struct adapter *); 555 int t4_create_dma_tag(struct adapter *); 556 int t4_destroy_dma_tag(struct adapter *); 557 int t4_setup_adapter_iqs(struct adapter *); 558 int t4_teardown_adapter_iqs(struct adapter *); 559 int t4_setup_eth_queues(struct port_info *); 560 int t4_teardown_eth_queues(struct port_info *); 561 void t4_intr_all(void *); 562 void t4_intr_fwd(void *); 563 void t4_intr_err(void *); 564 void t4_intr_evt(void *); 565 void t4_intr_data(void *); 566 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 567 void t4_update_fl_bufsize(struct ifnet *); 568 569 #endif 570