1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 #if defined(__i386__) || defined(__amd64__) 72 static __inline void 73 prefetch(void *x) 74 { 75 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 76 } 77 #else 78 #define prefetch(x) __builtin_prefetch(x) 79 #endif 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 ADAP_SYSCTL_CTX = (1 << 4), 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 167 CXGBE_BUSY = (1 << 9), 168 169 /* port flags */ 170 HAS_TRACEQ = (1 << 3), 171 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 172 173 /* VI flags */ 174 DOOMED = (1 << 0), 175 VI_INIT_DONE = (1 << 1), 176 VI_SYSCTL_CTX = (1 << 2), 177 TX_USES_VM_WR = (1 << 3), 178 179 /* adapter debug_flags */ 180 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 181 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 182 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 183 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 184 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 185 }; 186 187 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 188 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 189 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 190 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 191 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 192 193 struct vi_info { 194 device_t dev; 195 struct port_info *pi; 196 struct adapter *adapter; 197 198 struct ifnet *ifp; 199 struct pfil_head *pfil; 200 201 unsigned long flags; 202 int if_flags; 203 204 uint16_t *rss, *nm_rss; 205 uint16_t viid; /* opaque VI identifier */ 206 uint16_t smt_idx; 207 uint16_t vin; 208 uint8_t vfvld; 209 int16_t xact_addr_filt;/* index of exact MAC address filter */ 210 uint16_t rss_size; /* size of VI's RSS table slice */ 211 uint16_t rss_base; /* start of VI's RSS table slice */ 212 int hashen; 213 214 int nintr; 215 int first_intr; 216 217 /* These need to be int as they are used in sysctl */ 218 int ntxq; /* # of tx queues */ 219 int first_txq; /* index of first tx queue */ 220 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 221 int nrxq; /* # of rx queues */ 222 int first_rxq; /* index of first rx queue */ 223 int nofldtxq; /* # of offload tx queues */ 224 int first_ofld_txq; /* index of first offload tx queue */ 225 int nofldrxq; /* # of offload rx queues */ 226 int first_ofld_rxq; /* index of first offload rx queue */ 227 int nnmtxq; 228 int first_nm_txq; 229 int nnmrxq; 230 int first_nm_rxq; 231 int tmr_idx; 232 int ofld_tmr_idx; 233 int pktc_idx; 234 int ofld_pktc_idx; 235 int qsize_rxq; 236 int qsize_txq; 237 238 struct timeval last_refreshed; 239 struct fw_vi_stats_vf stats; 240 struct mtx tick_mtx; 241 struct callout tick; 242 243 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 244 245 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 246 }; 247 248 struct tx_ch_rl_params { 249 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 250 uint32_t maxrate; 251 }; 252 253 enum { 254 CLRL_USER = (1 << 0), /* allocated manually. */ 255 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 256 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 257 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 258 }; 259 260 struct tx_cl_rl_params { 261 int refcount; 262 uint8_t flags; 263 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 264 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 265 enum fw_sched_params_mode mode; /* aggr or per-flow */ 266 uint32_t maxrate; 267 uint16_t pktsize; 268 uint16_t burstsize; 269 }; 270 271 /* Tx scheduler parameters for a channel/port */ 272 struct tx_sched_params { 273 /* Channel Rate Limiter */ 274 struct tx_ch_rl_params ch_rl; 275 276 /* Class WRR */ 277 /* XXX */ 278 279 /* Class Rate Limiter (including the default pktsize and burstsize). */ 280 int pktsize; 281 int burstsize; 282 struct tx_cl_rl_params cl_rl[]; 283 }; 284 285 struct port_info { 286 device_t dev; 287 struct adapter *adapter; 288 289 struct vi_info *vi; 290 int nvi; 291 int up_vis; 292 int uld_vis; 293 bool vxlan_tcam_entry; 294 295 struct tx_sched_params *sched_params; 296 297 struct mtx pi_lock; 298 char lockname[16]; 299 unsigned long flags; 300 301 uint8_t lport; /* associated offload logical port */ 302 int8_t mdio_addr; 303 uint8_t port_type; 304 uint8_t mod_type; 305 uint8_t port_id; 306 uint8_t tx_chan; 307 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 308 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 309 uint8_t rx_c_chan; /* rx TP c-channel */ 310 311 struct link_config link_cfg; 312 struct ifmedia media; 313 314 struct timeval last_refreshed; 315 struct port_stats stats; 316 u_int tnl_cong_drops; 317 u_int tx_parse_error; 318 int fcs_reg; 319 uint64_t fcs_base; 320 }; 321 322 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 323 324 struct cluster_metadata { 325 uma_zone_t zone; 326 caddr_t cl; 327 u_int refcount; 328 }; 329 330 struct fl_sdesc { 331 caddr_t cl; 332 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 333 int16_t moff; /* offset of metadata from cl */ 334 uint8_t zidx; 335 }; 336 337 struct tx_desc { 338 __be64 flit[8]; 339 }; 340 341 struct tx_sdesc { 342 struct mbuf *m; /* m_nextpkt linked chain of frames */ 343 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 344 }; 345 346 347 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 348 struct iq_desc { 349 struct rss_header rss; 350 uint8_t cpl[IQ_PAD]; 351 struct rsp_ctrl rsp; 352 }; 353 #undef IQ_PAD 354 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 355 356 enum { 357 /* iq flags */ 358 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 359 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 360 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 361 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 362 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 363 364 /* iq state */ 365 IQS_DISABLED = 0, 366 IQS_BUSY = 1, 367 IQS_IDLE = 2, 368 369 /* netmap related flags */ 370 NM_OFF = 0, 371 NM_ON = 1, 372 NM_BUSY = 2, 373 }; 374 375 enum { 376 CPL_COOKIE_RESERVED = 0, 377 CPL_COOKIE_FILTER, 378 CPL_COOKIE_DDP0, 379 CPL_COOKIE_DDP1, 380 CPL_COOKIE_TOM, 381 CPL_COOKIE_HASHFILTER, 382 CPL_COOKIE_ETHOFLD, 383 CPL_COOKIE_KERN_TLS, 384 385 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 386 }; 387 388 struct sge_iq; 389 struct rss_header; 390 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 391 struct mbuf *); 392 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 393 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 394 395 /* 396 * Ingress Queue: T4 is producer, driver is consumer. 397 */ 398 struct sge_iq { 399 uint32_t flags; 400 volatile int state; 401 struct adapter *adapter; 402 struct iq_desc *desc; /* KVA of descriptor ring */ 403 int8_t intr_pktc_idx; /* packet count threshold index */ 404 uint8_t gen; /* generation bit */ 405 uint8_t intr_params; /* interrupt holdoff parameters */ 406 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 407 uint16_t qsize; /* size (# of entries) of the queue */ 408 uint16_t sidx; /* index of the entry with the status page */ 409 uint16_t cidx; /* consumer index */ 410 uint16_t cntxt_id; /* SGE context id for the iq */ 411 uint16_t abs_id; /* absolute SGE id for the iq */ 412 413 STAILQ_ENTRY(sge_iq) link; 414 415 bus_dma_tag_t desc_tag; 416 bus_dmamap_t desc_map; 417 bus_addr_t ba; /* bus address of descriptor ring */ 418 }; 419 420 enum { 421 EQ_CTRL = 1, 422 EQ_ETH = 2, 423 EQ_OFLD = 3, 424 425 /* eq flags */ 426 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 427 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 428 EQ_ENABLED = (1 << 3), /* open for business */ 429 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 430 }; 431 432 /* Listed in order of preference. Update t4_sysctls too if you change these */ 433 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 434 435 /* 436 * Egress Queue: driver is producer, T4 is consumer. 437 * 438 * Note: A free list is an egress queue (driver produces the buffers and T4 439 * consumes them) but it's special enough to have its own struct (see sge_fl). 440 */ 441 struct sge_eq { 442 unsigned int flags; /* MUST be first */ 443 unsigned int cntxt_id; /* SGE context id for the eq */ 444 unsigned int abs_id; /* absolute SGE id for the eq */ 445 struct mtx eq_lock; 446 447 struct tx_desc *desc; /* KVA of descriptor ring */ 448 uint8_t doorbells; 449 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 450 u_int udb_qid; /* relative qid within the doorbell page */ 451 uint16_t sidx; /* index of the entry with the status page */ 452 uint16_t cidx; /* consumer idx (desc idx) */ 453 uint16_t pidx; /* producer idx (desc idx) */ 454 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 455 uint16_t dbidx; /* pidx of the most recent doorbell */ 456 uint16_t iqid; /* iq that gets egr_update for the eq */ 457 uint8_t tx_chan; /* tx channel used by the eq */ 458 volatile u_int equiq; /* EQUIQ outstanding */ 459 460 bus_dma_tag_t desc_tag; 461 bus_dmamap_t desc_map; 462 bus_addr_t ba; /* bus address of descriptor ring */ 463 char lockname[16]; 464 }; 465 466 struct rx_buf_info { 467 uma_zone_t zone; /* zone that this cluster comes from */ 468 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 469 * hwsize[hwidx1] = size1. No spare. */ 470 uint16_t size2; /* hwsize[hwidx2] = size2. 471 * spare in cluster = size1 - size2. */ 472 int8_t hwidx1; /* SGE bufsize idx for size1 */ 473 int8_t hwidx2; /* SGE bufsize idx for size2 */ 474 uint8_t type; /* EXT_xxx type of the cluster */ 475 }; 476 477 enum { 478 NUM_MEMWIN = 3, 479 480 MEMWIN0_APERTURE = 2048, 481 MEMWIN0_BASE = 0x1b800, 482 483 MEMWIN1_APERTURE = 32768, 484 MEMWIN1_BASE = 0x28000, 485 486 MEMWIN2_APERTURE_T4 = 65536, 487 MEMWIN2_BASE_T4 = 0x30000, 488 489 MEMWIN2_APERTURE_T5 = 128 * 1024, 490 MEMWIN2_BASE_T5 = 0x60000, 491 }; 492 493 struct memwin { 494 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 495 uint32_t mw_base; /* constant after setup_memwin */ 496 uint32_t mw_aperture; /* ditto */ 497 uint32_t mw_curpos; /* protected by mw_lock */ 498 }; 499 500 enum { 501 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 502 FL_DOOMED = (1 << 1), /* about to be destroyed */ 503 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 504 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 505 }; 506 507 #define FL_RUNNING_LOW(fl) \ 508 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 509 #define FL_NOT_RUNNING_LOW(fl) \ 510 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 511 512 struct sge_fl { 513 struct mtx fl_lock; 514 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 515 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 516 uint16_t zidx; /* refill zone idx */ 517 uint16_t safe_zidx; 518 uint16_t lowat; /* # of buffers <= this means fl needs help */ 519 int flags; 520 uint16_t buf_boundary; 521 522 /* The 16b idx all deal with hw descriptors */ 523 uint16_t dbidx; /* hw pidx after last doorbell */ 524 uint16_t sidx; /* index of status page */ 525 volatile uint16_t hw_cidx; 526 527 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 528 uint32_t cidx; /* consumer index */ 529 uint32_t pidx; /* producer index */ 530 531 uint32_t dbval; 532 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 533 volatile uint32_t *udb; 534 535 uint64_t cl_allocated; /* # of clusters allocated */ 536 uint64_t cl_recycled; /* # of clusters recycled */ 537 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 538 539 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 540 struct mbuf *m0; 541 struct mbuf **pnext; 542 u_int remaining; 543 544 uint16_t qsize; /* # of hw descriptors (status page included) */ 545 uint16_t cntxt_id; /* SGE context id for the freelist */ 546 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 547 bus_dma_tag_t desc_tag; 548 bus_dmamap_t desc_map; 549 char lockname[16]; 550 bus_addr_t ba; /* bus address of descriptor ring */ 551 }; 552 553 struct mp_ring; 554 555 struct txpkts { 556 uint8_t wr_type; /* type 0 or type 1 */ 557 uint8_t npkt; /* # of packets in this work request */ 558 uint8_t len16; /* # of 16B pieces used by this work request */ 559 uint8_t score; 560 uint8_t max_npkt; /* maximum number of packets allowed */ 561 uint16_t plen; /* total payload (sum of all packets) */ 562 563 /* straight from fw_eth_tx_pkts_vm_wr. */ 564 __u8 ethmacdst[6]; 565 __u8 ethmacsrc[6]; 566 __be16 ethtype; 567 __be16 vlantci; 568 569 struct mbuf *mb[15]; 570 }; 571 572 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 573 struct sge_txq { 574 struct sge_eq eq; /* MUST be first */ 575 576 struct ifnet *ifp; /* the interface this txq belongs to */ 577 struct mp_ring *r; /* tx software ring */ 578 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 579 struct sglist *gl; 580 __be32 cpl_ctrl0; /* for convenience */ 581 int tc_idx; /* traffic class */ 582 uint64_t last_tx; /* cycle count when eth_tx was last called */ 583 struct txpkts txp; 584 585 struct task tx_reclaim_task; 586 /* stats for common events first */ 587 588 uint64_t txcsum; /* # of times hardware assisted with checksum */ 589 uint64_t tso_wrs; /* # of TSO work requests */ 590 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 591 uint64_t imm_wrs; /* # of work requests with immediate data */ 592 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 593 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 594 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 595 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 596 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 597 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 598 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 599 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 600 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 601 uint64_t vxlan_txcsum; 602 603 uint64_t kern_tls_records; 604 uint64_t kern_tls_short; 605 uint64_t kern_tls_partial; 606 uint64_t kern_tls_full; 607 uint64_t kern_tls_octets; 608 uint64_t kern_tls_waste; 609 uint64_t kern_tls_options; 610 uint64_t kern_tls_header; 611 uint64_t kern_tls_fin; 612 uint64_t kern_tls_fin_short; 613 uint64_t kern_tls_cbc; 614 uint64_t kern_tls_gcm; 615 616 /* stats for not-that-common events */ 617 618 /* Optional scratch space for constructing work requests. */ 619 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 620 } __aligned(CACHE_LINE_SIZE); 621 622 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 623 struct sge_rxq { 624 struct sge_iq iq; /* MUST be first */ 625 struct sge_fl fl; /* MUST follow iq */ 626 627 struct ifnet *ifp; /* the interface this rxq belongs to */ 628 struct lro_ctrl lro; /* LRO state */ 629 630 /* stats for common events first */ 631 632 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 633 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 634 uint64_t vxlan_rxcsum; 635 636 /* stats for not-that-common events */ 637 638 } __aligned(CACHE_LINE_SIZE); 639 640 static inline struct sge_rxq * 641 iq_to_rxq(struct sge_iq *iq) 642 { 643 644 return (__containerof(iq, struct sge_rxq, iq)); 645 } 646 647 648 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 649 struct sge_ofld_rxq { 650 struct sge_iq iq; /* MUST be first */ 651 struct sge_fl fl; /* MUST follow iq */ 652 u_long rx_toe_tls_records; 653 u_long rx_toe_tls_octets; 654 } __aligned(CACHE_LINE_SIZE); 655 656 static inline struct sge_ofld_rxq * 657 iq_to_ofld_rxq(struct sge_iq *iq) 658 { 659 660 return (__containerof(iq, struct sge_ofld_rxq, iq)); 661 } 662 663 struct wrqe { 664 STAILQ_ENTRY(wrqe) link; 665 struct sge_wrq *wrq; 666 int wr_len; 667 char wr[] __aligned(16); 668 }; 669 670 struct wrq_cookie { 671 TAILQ_ENTRY(wrq_cookie) link; 672 int ndesc; 673 int pidx; 674 }; 675 676 /* 677 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 678 * are of this type. 679 */ 680 struct sge_wrq { 681 struct sge_eq eq; /* MUST be first */ 682 683 struct adapter *adapter; 684 struct task wrq_tx_task; 685 686 /* Tx desc reserved but WR not "committed" yet. */ 687 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 688 689 /* List of WRs ready to go out as soon as descriptors are available. */ 690 STAILQ_HEAD(, wrqe) wr_list; 691 u_int nwr_pending; 692 u_int ndesc_needed; 693 694 /* stats for common events first */ 695 696 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 697 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 698 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 699 700 /* stats for not-that-common events */ 701 702 /* 703 * Scratch space for work requests that wrap around after reaching the 704 * status page, and some information about the last WR that used it. 705 */ 706 uint16_t ss_pidx; 707 uint16_t ss_len; 708 uint8_t ss[SGE_MAX_WR_LEN]; 709 710 } __aligned(CACHE_LINE_SIZE); 711 712 /* ofld_txq: SGE egress queue + miscellaneous items */ 713 struct sge_ofld_txq { 714 struct sge_wrq wrq; 715 counter_u64_t tx_toe_tls_records; 716 counter_u64_t tx_toe_tls_octets; 717 } __aligned(CACHE_LINE_SIZE); 718 719 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 720 struct sge_nm_rxq { 721 /* Items used by the driver rx ithread are in this cacheline. */ 722 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 723 u_int nid; /* netmap ring # for this queue */ 724 struct vi_info *vi; 725 726 struct iq_desc *iq_desc; 727 uint16_t iq_abs_id; 728 uint16_t iq_cntxt_id; 729 uint16_t iq_cidx; 730 uint16_t iq_sidx; 731 uint8_t iq_gen; 732 uint32_t fl_sidx; 733 734 /* Items used by netmap rxsync are in this cacheline. */ 735 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 736 uint16_t fl_cntxt_id; 737 uint32_t fl_pidx; 738 uint32_t fl_sidx2; /* copy of fl_sidx */ 739 uint32_t fl_db_val; 740 u_int fl_db_saved; 741 u_int fl_db_threshold; /* in descriptors */ 742 u_int fl_hwidx:4; 743 744 /* 745 * fl_cidx is used by both the ithread and rxsync, the rest are not used 746 * in the rx fast path. 747 */ 748 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 749 750 bus_dma_tag_t iq_desc_tag; 751 bus_dmamap_t iq_desc_map; 752 bus_addr_t iq_ba; 753 int intr_idx; 754 755 bus_dma_tag_t fl_desc_tag; 756 bus_dmamap_t fl_desc_map; 757 bus_addr_t fl_ba; 758 }; 759 760 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 761 struct sge_nm_txq { 762 struct tx_desc *desc; 763 uint16_t cidx; 764 uint16_t pidx; 765 uint16_t sidx; 766 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 767 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 768 uint16_t dbidx; /* pidx of the most recent doorbell */ 769 uint8_t doorbells; 770 volatile uint32_t *udb; 771 u_int udb_qid; 772 u_int cntxt_id; 773 __be32 cpl_ctrl0; /* for convenience */ 774 __be32 op_pkd; /* ditto */ 775 u_int nid; /* netmap ring # for this queue */ 776 777 /* infrequently used items after this */ 778 779 bus_dma_tag_t desc_tag; 780 bus_dmamap_t desc_map; 781 bus_addr_t ba; 782 int iqidx; 783 } __aligned(CACHE_LINE_SIZE); 784 785 struct sge { 786 int nrxq; /* total # of Ethernet rx queues */ 787 int ntxq; /* total # of Ethernet tx queues */ 788 int nofldrxq; /* total # of TOE rx queues */ 789 int nofldtxq; /* total # of TOE tx queues */ 790 int nnmrxq; /* total # of netmap rx queues */ 791 int nnmtxq; /* total # of netmap tx queues */ 792 int niq; /* total # of ingress queues */ 793 int neq; /* total # of egress queues */ 794 795 struct sge_iq fwq; /* Firmware event queue */ 796 struct sge_wrq *ctrlq; /* Control queues */ 797 struct sge_txq *txq; /* NIC tx queues */ 798 struct sge_rxq *rxq; /* NIC rx queues */ 799 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 800 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 801 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 802 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 803 804 uint16_t iq_start; /* first cntxt_id */ 805 uint16_t iq_base; /* first abs_id */ 806 int eq_start; /* first cntxt_id */ 807 int eq_base; /* first abs_id */ 808 int iqmap_sz; 809 int eqmap_sz; 810 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 811 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 812 813 int8_t safe_zidx; 814 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 815 }; 816 817 struct devnames { 818 const char *nexus_name; 819 const char *ifnet_name; 820 const char *vi_ifnet_name; 821 const char *pf03_drv_name; 822 const char *vf_nexus_name; 823 const char *vf_ifnet_name; 824 }; 825 826 struct clip_entry; 827 828 struct adapter { 829 SLIST_ENTRY(adapter) link; 830 device_t dev; 831 struct cdev *cdev; 832 const struct devnames *names; 833 834 /* PCIe register resources */ 835 int regs_rid; 836 struct resource *regs_res; 837 int msix_rid; 838 struct resource *msix_res; 839 bus_space_handle_t bh; 840 bus_space_tag_t bt; 841 bus_size_t mmio_len; 842 int udbs_rid; 843 struct resource *udbs_res; 844 volatile uint8_t *udbs_base; 845 846 unsigned int pf; 847 unsigned int mbox; 848 unsigned int vpd_busy; 849 unsigned int vpd_flag; 850 851 /* Interrupt information */ 852 int intr_type; 853 int intr_count; 854 struct irq { 855 struct resource *res; 856 int rid; 857 void *tag; 858 struct sge_rxq *rxq; 859 struct sge_nm_rxq *nm_rxq; 860 } __aligned(CACHE_LINE_SIZE) *irq; 861 int sge_gts_reg; 862 int sge_kdoorbell_reg; 863 864 bus_dma_tag_t dmat; /* Parent DMA tag */ 865 866 struct sge sge; 867 int lro_timeout; 868 int sc_do_rxcopy; 869 870 int vxlan_port; 871 u_int vxlan_refcount; 872 int rawf_base; 873 int nrawf; 874 875 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 876 struct task async_event_task; 877 struct port_info *port[MAX_NPORTS]; 878 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 879 880 struct mtx clip_table_lock; 881 TAILQ_HEAD(, clip_entry) clip_table; 882 int clip_gen; 883 884 void *tom_softc; /* (struct tom_data *) */ 885 struct tom_tunables tt; 886 struct t4_offload_policy *policy; 887 struct rwlock policy_lock; 888 889 void *iwarp_softc; /* (struct c4iw_dev *) */ 890 struct iw_tunables iwt; 891 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 892 void *ccr_softc; /* (struct ccr_softc *) */ 893 struct l2t_data *l2t; /* L2 table */ 894 struct smt_data *smt; /* Source MAC Table */ 895 struct tid_info tids; 896 vmem_t *key_map; 897 struct tls_tunables tlst; 898 899 uint8_t doorbells; 900 int offload_map; /* ports with IFCAP_TOE enabled */ 901 int active_ulds; /* ULDs activated on this adapter */ 902 int flags; 903 int debug_flags; 904 905 char ifp_lockname[16]; 906 struct mtx ifp_lock; 907 struct ifnet *ifp; /* tracer ifp */ 908 struct ifmedia media; 909 int traceq; /* iq used by all tracers, -1 if none */ 910 int tracer_valid; /* bitmap of valid tracers */ 911 int tracer_enabled; /* bitmap of enabled tracers */ 912 913 char fw_version[16]; 914 char tp_version[16]; 915 char er_version[16]; 916 char bs_version[16]; 917 char cfg_file[32]; 918 u_int cfcsum; 919 struct adapter_params params; 920 const struct chip_params *chip_params; 921 struct t4_virt_res vres; 922 923 uint16_t nbmcaps; 924 uint16_t linkcaps; 925 uint16_t switchcaps; 926 uint16_t niccaps; 927 uint16_t toecaps; 928 uint16_t rdmacaps; 929 uint16_t cryptocaps; 930 uint16_t iscsicaps; 931 uint16_t fcoecaps; 932 933 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 934 935 struct mtx sc_lock; 936 char lockname[16]; 937 938 /* Starving free lists */ 939 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 940 TAILQ_HEAD(, sge_fl) sfl; 941 struct callout sfl_callout; 942 943 struct mtx reg_lock; /* for indirect register access */ 944 945 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 946 947 struct mtx tc_lock; 948 struct task tc_task; 949 950 const char *last_op; 951 const void *last_op_thr; 952 int last_op_flags; 953 954 int swintr; 955 int sensor_resets; 956 957 struct callout ktls_tick; 958 }; 959 960 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 961 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 962 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 963 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 964 965 #define ASSERT_SYNCHRONIZED_OP(sc) \ 966 KASSERT(IS_BUSY(sc) && \ 967 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 968 ("%s: operation not synchronized.", __func__)) 969 970 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 971 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 972 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 973 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 974 975 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 976 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 977 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 978 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 979 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 980 981 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 982 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 983 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 984 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 985 986 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 987 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 988 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 989 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 990 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 991 992 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 993 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 994 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 995 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 996 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 997 998 #define for_each_txq(vi, iter, q) \ 999 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1000 iter < vi->ntxq; ++iter, ++q) 1001 #define for_each_rxq(vi, iter, q) \ 1002 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1003 iter < vi->nrxq; ++iter, ++q) 1004 #define for_each_ofld_txq(vi, iter, q) \ 1005 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1006 iter < vi->nofldtxq; ++iter, ++q) 1007 #define for_each_ofld_rxq(vi, iter, q) \ 1008 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1009 iter < vi->nofldrxq; ++iter, ++q) 1010 #define for_each_nm_txq(vi, iter, q) \ 1011 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1012 iter < vi->nnmtxq; ++iter, ++q) 1013 #define for_each_nm_rxq(vi, iter, q) \ 1014 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1015 iter < vi->nnmrxq; ++iter, ++q) 1016 #define for_each_vi(_pi, _iter, _vi) \ 1017 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1018 ++(_iter), ++(_vi)) 1019 1020 #define IDXINCR(idx, incr, wrap) do { \ 1021 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1022 } while (0) 1023 #define IDXDIFF(head, tail, wrap) \ 1024 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1025 1026 /* One for errors, one for firmware events */ 1027 #define T4_EXTRA_INTR 2 1028 1029 /* One for firmware events */ 1030 #define T4VF_EXTRA_INTR 1 1031 1032 static inline int 1033 forwarding_intr_to_fwq(struct adapter *sc) 1034 { 1035 1036 return (sc->intr_count == 1); 1037 } 1038 1039 static inline uint32_t 1040 t4_read_reg(struct adapter *sc, uint32_t reg) 1041 { 1042 1043 return bus_space_read_4(sc->bt, sc->bh, reg); 1044 } 1045 1046 static inline void 1047 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1048 { 1049 1050 bus_space_write_4(sc->bt, sc->bh, reg, val); 1051 } 1052 1053 static inline uint64_t 1054 t4_read_reg64(struct adapter *sc, uint32_t reg) 1055 { 1056 1057 #ifdef __LP64__ 1058 return bus_space_read_8(sc->bt, sc->bh, reg); 1059 #else 1060 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1061 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1062 1063 #endif 1064 } 1065 1066 static inline void 1067 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1068 { 1069 1070 #ifdef __LP64__ 1071 bus_space_write_8(sc->bt, sc->bh, reg, val); 1072 #else 1073 bus_space_write_4(sc->bt, sc->bh, reg, val); 1074 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1075 #endif 1076 } 1077 1078 static inline void 1079 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1080 { 1081 1082 *val = pci_read_config(sc->dev, reg, 1); 1083 } 1084 1085 static inline void 1086 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1087 { 1088 1089 pci_write_config(sc->dev, reg, val, 1); 1090 } 1091 1092 static inline void 1093 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1094 { 1095 1096 *val = pci_read_config(sc->dev, reg, 2); 1097 } 1098 1099 static inline void 1100 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1101 { 1102 1103 pci_write_config(sc->dev, reg, val, 2); 1104 } 1105 1106 static inline void 1107 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1108 { 1109 1110 *val = pci_read_config(sc->dev, reg, 4); 1111 } 1112 1113 static inline void 1114 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1115 { 1116 1117 pci_write_config(sc->dev, reg, val, 4); 1118 } 1119 1120 static inline struct port_info * 1121 adap2pinfo(struct adapter *sc, int idx) 1122 { 1123 1124 return (sc->port[idx]); 1125 } 1126 1127 static inline void 1128 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1129 { 1130 1131 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1132 } 1133 1134 static inline int 1135 tx_resume_threshold(struct sge_eq *eq) 1136 { 1137 1138 /* not quite the same as qsize / 4, but this will do. */ 1139 return (eq->sidx / 4); 1140 } 1141 1142 static inline int 1143 t4_use_ldst(struct adapter *sc) 1144 { 1145 1146 #ifdef notyet 1147 return (sc->flags & FW_OK || !sc->use_bd); 1148 #else 1149 return (0); 1150 #endif 1151 } 1152 1153 static inline void 1154 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1155 const char *msg, const __be64 *const p, const bool err) 1156 { 1157 1158 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1159 return; 1160 if (p != NULL) { 1161 log(err ? LOG_ERR : LOG_DEBUG, 1162 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1163 "%016llx %016llx %016llx %016llx\n", 1164 device_get_nameunit(sc->dev), mbox, msg, 1165 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1166 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1167 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1168 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1169 } else { 1170 log(err ? LOG_ERR : LOG_DEBUG, 1171 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1172 "%016llx %016llx %016llx %016llx\n", 1173 device_get_nameunit(sc->dev), mbox, msg, 1174 (long long)t4_read_reg64(sc, reg), 1175 (long long)t4_read_reg64(sc, reg + 8), 1176 (long long)t4_read_reg64(sc, reg + 16), 1177 (long long)t4_read_reg64(sc, reg + 24), 1178 (long long)t4_read_reg64(sc, reg + 32), 1179 (long long)t4_read_reg64(sc, reg + 40), 1180 (long long)t4_read_reg64(sc, reg + 48), 1181 (long long)t4_read_reg64(sc, reg + 56)); 1182 } 1183 } 1184 1185 /* t4_main.c */ 1186 extern int t4_ntxq; 1187 extern int t4_nrxq; 1188 extern int t4_intr_types; 1189 extern int t4_tmr_idx; 1190 extern int t4_pktc_idx; 1191 extern unsigned int t4_qsize_rxq; 1192 extern unsigned int t4_qsize_txq; 1193 extern device_method_t cxgbe_methods[]; 1194 1195 int t4_os_find_pci_capability(struct adapter *, int); 1196 int t4_os_pci_save_state(struct adapter *); 1197 int t4_os_pci_restore_state(struct adapter *); 1198 void t4_os_portmod_changed(struct port_info *); 1199 void t4_os_link_changed(struct port_info *); 1200 void t4_iterate(void (*)(struct adapter *, void *), void *); 1201 void t4_init_devnames(struct adapter *); 1202 void t4_add_adapter(struct adapter *); 1203 int t4_detach_common(device_t); 1204 int t4_map_bars_0_and_4(struct adapter *); 1205 int t4_map_bar_2(struct adapter *); 1206 int t4_setup_intr_handlers(struct adapter *); 1207 void t4_sysctls(struct adapter *); 1208 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1209 void doom_vi(struct adapter *, struct vi_info *); 1210 void end_synchronized_op(struct adapter *, int); 1211 int update_mac_settings(struct ifnet *, int); 1212 int adapter_full_init(struct adapter *); 1213 int adapter_full_uninit(struct adapter *); 1214 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1215 int vi_full_init(struct vi_info *); 1216 int vi_full_uninit(struct vi_info *); 1217 void vi_sysctls(struct vi_info *); 1218 void vi_tick(void *); 1219 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1220 int alloc_atid(struct adapter *, void *); 1221 void *lookup_atid(struct adapter *, int); 1222 void free_atid(struct adapter *, int); 1223 void release_tid(struct adapter *, int, struct sge_wrq *); 1224 int cxgbe_media_change(struct ifnet *); 1225 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1226 bool t4_os_dump_cimla(struct adapter *, int, bool); 1227 void t4_os_dump_devlog(struct adapter *); 1228 1229 #ifdef KERN_TLS 1230 /* t4_kern_tls.c */ 1231 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1232 struct m_snd_tag **); 1233 void cxgbe_tls_tag_free(struct m_snd_tag *); 1234 void t6_ktls_modload(void); 1235 void t6_ktls_modunload(void); 1236 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1237 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1238 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1239 #endif 1240 1241 /* t4_keyctx.c */ 1242 struct auth_hash; 1243 union authctx; 1244 1245 void t4_aes_getdeckey(void *, const void *, unsigned int); 1246 void t4_copy_partial_hash(int, union authctx *, void *); 1247 void t4_init_gmac_hash(const char *, int, char *); 1248 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *); 1249 1250 #ifdef DEV_NETMAP 1251 /* t4_netmap.c */ 1252 struct sge_nm_rxq; 1253 void cxgbe_nm_attach(struct vi_info *); 1254 void cxgbe_nm_detach(struct vi_info *); 1255 void service_nm_rxq(struct sge_nm_rxq *); 1256 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 1257 struct sysctl_oid *); 1258 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1259 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 1260 struct sysctl_oid *); 1261 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1262 #endif 1263 1264 /* t4_sge.c */ 1265 void t4_sge_modload(void); 1266 void t4_sge_modunload(void); 1267 uint64_t t4_sge_extfree_refs(void); 1268 void t4_tweak_chip_settings(struct adapter *); 1269 int t4_verify_chip_settings(struct adapter *); 1270 void t4_init_rx_buf_info(struct adapter *); 1271 int t4_create_dma_tag(struct adapter *); 1272 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1273 struct sysctl_oid_list *); 1274 int t4_destroy_dma_tag(struct adapter *); 1275 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1276 bus_addr_t *, void **); 1277 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1278 void *); 1279 int t4_setup_adapter_queues(struct adapter *); 1280 int t4_teardown_adapter_queues(struct adapter *); 1281 int t4_setup_vi_queues(struct vi_info *); 1282 int t4_teardown_vi_queues(struct vi_info *); 1283 void t4_intr_all(void *); 1284 void t4_intr(void *); 1285 #ifdef DEV_NETMAP 1286 void t4_nm_intr(void *); 1287 void t4_vi_intr(void *); 1288 #endif 1289 void t4_intr_err(void *); 1290 void t4_intr_evt(void *); 1291 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1292 void t4_update_fl_bufsize(struct ifnet *); 1293 struct mbuf *alloc_wr_mbuf(int, int); 1294 int parse_pkt(struct mbuf **, bool); 1295 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1296 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1297 int tnl_cong(struct port_info *, int); 1298 void t4_register_an_handler(an_handler_t); 1299 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1300 void t4_register_cpl_handler(int, cpl_handler_t); 1301 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1302 #ifdef RATELIMIT 1303 int ethofld_transmit(struct ifnet *, struct mbuf *); 1304 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1305 #endif 1306 1307 /* t4_tracer.c */ 1308 struct t4_tracer; 1309 void t4_tracer_modload(void); 1310 void t4_tracer_modunload(void); 1311 void t4_tracer_port_detach(struct adapter *); 1312 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1313 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1314 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1315 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1316 1317 /* t4_sched.c */ 1318 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1319 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1320 int t4_init_tx_sched(struct adapter *); 1321 int t4_free_tx_sched(struct adapter *); 1322 void t4_update_tx_sched(struct adapter *); 1323 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1324 void t4_release_cl_rl(struct adapter *, int, int); 1325 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1326 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1327 #ifdef RATELIMIT 1328 void t4_init_etid_table(struct adapter *); 1329 void t4_free_etid_table(struct adapter *); 1330 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1331 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1332 struct m_snd_tag **); 1333 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1334 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1335 void cxgbe_rate_tag_free(struct m_snd_tag *); 1336 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1337 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1338 #endif 1339 1340 /* t4_filter.c */ 1341 int get_filter_mode(struct adapter *, uint32_t *); 1342 int set_filter_mode(struct adapter *, uint32_t); 1343 int set_filter_mask(struct adapter *, uint32_t); 1344 int get_filter(struct adapter *, struct t4_filter *); 1345 int set_filter(struct adapter *, struct t4_filter *); 1346 int del_filter(struct adapter *, struct t4_filter *); 1347 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1348 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1349 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1350 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1351 void free_hftid_hash(struct tid_info *); 1352 1353 static inline struct wrqe * 1354 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1355 { 1356 int len = offsetof(struct wrqe, wr) + wr_len; 1357 struct wrqe *wr; 1358 1359 wr = malloc(len, M_CXGBE, M_NOWAIT); 1360 if (__predict_false(wr == NULL)) 1361 return (NULL); 1362 wr->wr_len = wr_len; 1363 wr->wrq = wrq; 1364 return (wr); 1365 } 1366 1367 static inline void * 1368 wrtod(struct wrqe *wr) 1369 { 1370 return (&wr->wr[0]); 1371 } 1372 1373 static inline void 1374 free_wrqe(struct wrqe *wr) 1375 { 1376 free(wr, M_CXGBE); 1377 } 1378 1379 static inline void 1380 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1381 { 1382 struct sge_wrq *wrq = wr->wrq; 1383 1384 TXQ_LOCK(wrq); 1385 t4_wrq_tx_locked(sc, wrq, wr); 1386 TXQ_UNLOCK(wrq); 1387 } 1388 1389 static inline int 1390 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1391 int len) 1392 { 1393 1394 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1395 } 1396 1397 static inline int 1398 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1399 const uint32_t *val, int len) 1400 { 1401 1402 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1403 } 1404 1405 /* Number of len16 -> number of descriptors */ 1406 static inline int 1407 tx_len16_to_desc(int len16) 1408 { 1409 1410 return (howmany(len16, EQ_ESIZE / 16)); 1411 } 1412 #endif 1413