1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/types.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/rwlock.h> 43 #include <sys/sx.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <net/ethernet.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_media.h> 55 #include <netinet/in.h> 56 #include <netinet/tcp_lro.h> 57 58 #include "offload.h" 59 #include "t4_ioctl.h" 60 #include "common/t4_msg.h" 61 #include "firmware/t4fw_interface.h" 62 63 #define KTR_CXGBE KTR_SPARE3 64 MALLOC_DECLARE(M_CXGBE); 65 #define CXGBE_UNIMPLEMENTED(s) \ 66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 67 68 #if defined(__i386__) || defined(__amd64__) 69 static __inline void 70 prefetch(void *x) 71 { 72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 73 } 74 #else 75 #define prefetch(x) __builtin_prefetch(x) 76 #endif 77 78 #ifndef SYSCTL_ADD_UQUAD 79 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 80 #define sysctl_handle_64 sysctl_handle_quad 81 #define CTLTYPE_U64 CTLTYPE_QUAD 82 #endif 83 84 struct adapter; 85 typedef struct adapter adapter_t; 86 87 enum { 88 /* 89 * All ingress queues use this entry size. Note that the firmware event 90 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 91 * be at least 64. 92 */ 93 IQ_ESIZE = 64, 94 95 /* Default queue sizes for all kinds of ingress queues */ 96 FW_IQ_QSIZE = 256, 97 RX_IQ_QSIZE = 1024, 98 99 /* All egress queues use this entry size */ 100 EQ_ESIZE = 64, 101 102 /* Default queue sizes for all kinds of egress queues */ 103 CTRL_EQ_QSIZE = 1024, 104 TX_EQ_QSIZE = 1024, 105 106 #if MJUMPAGESIZE != MCLBYTES 107 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 108 #else 109 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 110 #endif 111 CL_METADATA_SIZE = CACHE_LINE_SIZE, 112 113 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 114 TX_SGL_SEGS = 39, 115 TX_SGL_SEGS_TSO = 38, 116 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 117 }; 118 119 enum { 120 /* adapter intr_type */ 121 INTR_INTX = (1 << 0), 122 INTR_MSI = (1 << 1), 123 INTR_MSIX = (1 << 2) 124 }; 125 126 enum { 127 XGMAC_MTU = (1 << 0), 128 XGMAC_PROMISC = (1 << 1), 129 XGMAC_ALLMULTI = (1 << 2), 130 XGMAC_VLANEX = (1 << 3), 131 XGMAC_UCADDR = (1 << 4), 132 XGMAC_MCADDRS = (1 << 5), 133 134 XGMAC_ALL = 0xffff 135 }; 136 137 enum { 138 /* flags understood by begin_synchronized_op */ 139 HOLD_LOCK = (1 << 0), 140 SLEEP_OK = (1 << 1), 141 INTR_OK = (1 << 2), 142 143 /* flags understood by end_synchronized_op */ 144 LOCK_HELD = HOLD_LOCK, 145 }; 146 147 enum { 148 /* adapter flags */ 149 FULL_INIT_DONE = (1 << 0), 150 FW_OK = (1 << 1), 151 CHK_MBOX_ACCESS = (1 << 2), 152 MASTER_PF = (1 << 3), 153 ADAP_SYSCTL_CTX = (1 << 4), 154 /* TOM_INIT_DONE= (1 << 5), No longer used */ 155 BUF_PACKING_OK = (1 << 6), 156 IS_VF = (1 << 7), 157 158 CXGBE_BUSY = (1 << 9), 159 160 /* port flags */ 161 HAS_TRACEQ = (1 << 3), 162 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 163 164 /* VI flags */ 165 DOOMED = (1 << 0), 166 VI_INIT_DONE = (1 << 1), 167 VI_SYSCTL_CTX = (1 << 2), 168 169 /* adapter debug_flags */ 170 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 171 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 172 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 173 }; 174 175 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 176 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 177 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 178 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 179 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 180 181 struct vi_info { 182 device_t dev; 183 struct port_info *pi; 184 185 struct ifnet *ifp; 186 187 unsigned long flags; 188 int if_flags; 189 190 uint16_t *rss, *nm_rss; 191 int smt_idx; /* for convenience */ 192 uint16_t viid; 193 int16_t xact_addr_filt;/* index of exact MAC address filter */ 194 uint16_t rss_size; /* size of VI's RSS table slice */ 195 uint16_t rss_base; /* start of VI's RSS table slice */ 196 197 int nintr; 198 int first_intr; 199 200 /* These need to be int as they are used in sysctl */ 201 int ntxq; /* # of tx queues */ 202 int first_txq; /* index of first tx queue */ 203 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 204 int nrxq; /* # of rx queues */ 205 int first_rxq; /* index of first rx queue */ 206 int nofldtxq; /* # of offload tx queues */ 207 int first_ofld_txq; /* index of first offload tx queue */ 208 int nofldrxq; /* # of offload rx queues */ 209 int first_ofld_rxq; /* index of first offload rx queue */ 210 int nnmtxq; 211 int first_nm_txq; 212 int nnmrxq; 213 int first_nm_rxq; 214 int tmr_idx; 215 int ofld_tmr_idx; 216 int pktc_idx; 217 int ofld_pktc_idx; 218 int qsize_rxq; 219 int qsize_txq; 220 221 struct timeval last_refreshed; 222 struct fw_vi_stats_vf stats; 223 224 struct callout tick; 225 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 226 227 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 228 }; 229 230 struct tx_ch_rl_params { 231 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 232 uint32_t maxrate; 233 }; 234 235 enum { 236 CLRL_USER = (1 << 0), /* allocated manually. */ 237 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 238 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 239 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 240 }; 241 242 struct tx_cl_rl_params { 243 int refcount; 244 uint8_t flags; 245 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 246 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 247 enum fw_sched_params_mode mode; /* aggr or per-flow */ 248 uint32_t maxrate; 249 uint16_t pktsize; 250 uint16_t burstsize; 251 }; 252 253 /* Tx scheduler parameters for a channel/port */ 254 struct tx_sched_params { 255 /* Channel Rate Limiter */ 256 struct tx_ch_rl_params ch_rl; 257 258 /* Class WRR */ 259 /* XXX */ 260 261 /* Class Rate Limiter (including the default pktsize and burstsize). */ 262 int pktsize; 263 int burstsize; 264 struct tx_cl_rl_params cl_rl[]; 265 }; 266 267 struct port_info { 268 device_t dev; 269 struct adapter *adapter; 270 271 struct vi_info *vi; 272 int nvi; 273 int up_vis; 274 int uld_vis; 275 276 struct tx_sched_params *sched_params; 277 278 struct mtx pi_lock; 279 char lockname[16]; 280 unsigned long flags; 281 282 uint8_t lport; /* associated offload logical port */ 283 int8_t mdio_addr; 284 uint8_t port_type; 285 uint8_t mod_type; 286 uint8_t port_id; 287 uint8_t tx_chan; 288 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 289 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 290 291 struct link_config link_cfg; 292 struct link_config old_link_cfg; 293 struct ifmedia media; 294 295 struct timeval last_refreshed; 296 struct port_stats stats; 297 u_int tnl_cong_drops; 298 u_int tx_parse_error; 299 u_long tx_tls_records; 300 u_long tx_tls_octets; 301 u_long rx_tls_records; 302 u_long rx_tls_octets; 303 304 struct callout tick; 305 }; 306 307 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 308 309 /* Where the cluster came from, how it has been carved up. */ 310 struct cluster_layout { 311 int8_t zidx; 312 int8_t hwidx; 313 uint16_t region1; /* mbufs laid out within this region */ 314 /* region2 is the DMA region */ 315 uint16_t region3; /* cluster_metadata within this region */ 316 }; 317 318 struct cluster_metadata { 319 u_int refcount; 320 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 321 }; 322 323 struct fl_sdesc { 324 caddr_t cl; 325 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 326 struct cluster_layout cll; 327 }; 328 329 struct tx_desc { 330 __be64 flit[8]; 331 }; 332 333 struct tx_sdesc { 334 struct mbuf *m; /* m_nextpkt linked chain of frames */ 335 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 336 }; 337 338 339 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 340 struct iq_desc { 341 struct rss_header rss; 342 uint8_t cpl[IQ_PAD]; 343 struct rsp_ctrl rsp; 344 }; 345 #undef IQ_PAD 346 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 347 348 enum { 349 /* iq flags */ 350 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 351 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 352 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 353 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 354 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 355 356 /* iq state */ 357 IQS_DISABLED = 0, 358 IQS_BUSY = 1, 359 IQS_IDLE = 2, 360 361 /* netmap related flags */ 362 NM_OFF = 0, 363 NM_ON = 1, 364 NM_BUSY = 2, 365 }; 366 367 enum { 368 CPL_COOKIE_RESERVED = 0, 369 CPL_COOKIE_FILTER, 370 CPL_COOKIE_DDP0, 371 CPL_COOKIE_DDP1, 372 CPL_COOKIE_TOM, 373 CPL_COOKIE_HASHFILTER, 374 CPL_COOKIE_ETHOFLD, 375 CPL_COOKIE_AVAILABLE3, 376 377 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 378 }; 379 380 struct sge_iq; 381 struct rss_header; 382 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 383 struct mbuf *); 384 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 385 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 386 387 /* 388 * Ingress Queue: T4 is producer, driver is consumer. 389 */ 390 struct sge_iq { 391 uint32_t flags; 392 volatile int state; 393 struct adapter *adapter; 394 struct iq_desc *desc; /* KVA of descriptor ring */ 395 int8_t intr_pktc_idx; /* packet count threshold index */ 396 uint8_t gen; /* generation bit */ 397 uint8_t intr_params; /* interrupt holdoff parameters */ 398 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 399 uint16_t qsize; /* size (# of entries) of the queue */ 400 uint16_t sidx; /* index of the entry with the status page */ 401 uint16_t cidx; /* consumer index */ 402 uint16_t cntxt_id; /* SGE context id for the iq */ 403 uint16_t abs_id; /* absolute SGE id for the iq */ 404 405 STAILQ_ENTRY(sge_iq) link; 406 407 bus_dma_tag_t desc_tag; 408 bus_dmamap_t desc_map; 409 bus_addr_t ba; /* bus address of descriptor ring */ 410 }; 411 412 enum { 413 EQ_CTRL = 1, 414 EQ_ETH = 2, 415 EQ_OFLD = 3, 416 417 /* eq flags */ 418 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 419 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 420 EQ_ENABLED = (1 << 3), /* open for business */ 421 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 422 }; 423 424 /* Listed in order of preference. Update t4_sysctls too if you change these */ 425 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 426 427 /* 428 * Egress Queue: driver is producer, T4 is consumer. 429 * 430 * Note: A free list is an egress queue (driver produces the buffers and T4 431 * consumes them) but it's special enough to have its own struct (see sge_fl). 432 */ 433 struct sge_eq { 434 unsigned int flags; /* MUST be first */ 435 unsigned int cntxt_id; /* SGE context id for the eq */ 436 unsigned int abs_id; /* absolute SGE id for the eq */ 437 struct mtx eq_lock; 438 439 struct tx_desc *desc; /* KVA of descriptor ring */ 440 uint8_t doorbells; 441 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 442 u_int udb_qid; /* relative qid within the doorbell page */ 443 uint16_t sidx; /* index of the entry with the status page */ 444 uint16_t cidx; /* consumer idx (desc idx) */ 445 uint16_t pidx; /* producer idx (desc idx) */ 446 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 447 uint16_t dbidx; /* pidx of the most recent doorbell */ 448 uint16_t iqid; /* iq that gets egr_update for the eq */ 449 uint8_t tx_chan; /* tx channel used by the eq */ 450 volatile u_int equiq; /* EQUIQ outstanding */ 451 452 bus_dma_tag_t desc_tag; 453 bus_dmamap_t desc_map; 454 bus_addr_t ba; /* bus address of descriptor ring */ 455 char lockname[16]; 456 }; 457 458 struct sw_zone_info { 459 uma_zone_t zone; /* zone that this cluster comes from */ 460 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 461 int type; /* EXT_xxx type of the cluster */ 462 int8_t head_hwidx; 463 int8_t tail_hwidx; 464 }; 465 466 struct hw_buf_info { 467 int8_t zidx; /* backpointer to zone; -ve means unused */ 468 int8_t next; /* next hwidx for this zone; -1 means no more */ 469 int size; 470 }; 471 472 enum { 473 NUM_MEMWIN = 3, 474 475 MEMWIN0_APERTURE = 2048, 476 MEMWIN0_BASE = 0x1b800, 477 478 MEMWIN1_APERTURE = 32768, 479 MEMWIN1_BASE = 0x28000, 480 481 MEMWIN2_APERTURE_T4 = 65536, 482 MEMWIN2_BASE_T4 = 0x30000, 483 484 MEMWIN2_APERTURE_T5 = 128 * 1024, 485 MEMWIN2_BASE_T5 = 0x60000, 486 }; 487 488 struct memwin { 489 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 490 uint32_t mw_base; /* constant after setup_memwin */ 491 uint32_t mw_aperture; /* ditto */ 492 uint32_t mw_curpos; /* protected by mw_lock */ 493 }; 494 495 enum { 496 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 497 FL_DOOMED = (1 << 1), /* about to be destroyed */ 498 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 499 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 500 }; 501 502 #define FL_RUNNING_LOW(fl) \ 503 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 504 #define FL_NOT_RUNNING_LOW(fl) \ 505 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 506 507 struct sge_fl { 508 struct mtx fl_lock; 509 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 510 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 511 struct cluster_layout cll_def; /* default refill zone, layout */ 512 uint16_t lowat; /* # of buffers <= this means fl needs help */ 513 int flags; 514 uint16_t buf_boundary; 515 516 /* The 16b idx all deal with hw descriptors */ 517 uint16_t dbidx; /* hw pidx after last doorbell */ 518 uint16_t sidx; /* index of status page */ 519 volatile uint16_t hw_cidx; 520 521 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 522 uint32_t cidx; /* consumer index */ 523 uint32_t pidx; /* producer index */ 524 525 uint32_t dbval; 526 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 527 volatile uint32_t *udb; 528 529 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 530 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 531 uint64_t cl_allocated; /* # of clusters allocated */ 532 uint64_t cl_recycled; /* # of clusters recycled */ 533 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 534 535 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 536 struct mbuf *m0; 537 struct mbuf **pnext; 538 u_int remaining; 539 540 uint16_t qsize; /* # of hw descriptors (status page included) */ 541 uint16_t cntxt_id; /* SGE context id for the freelist */ 542 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 543 bus_dma_tag_t desc_tag; 544 bus_dmamap_t desc_map; 545 char lockname[16]; 546 bus_addr_t ba; /* bus address of descriptor ring */ 547 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 548 }; 549 550 struct mp_ring; 551 552 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 553 struct sge_txq { 554 struct sge_eq eq; /* MUST be first */ 555 556 struct ifnet *ifp; /* the interface this txq belongs to */ 557 struct mp_ring *r; /* tx software ring */ 558 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 559 struct sglist *gl; 560 __be32 cpl_ctrl0; /* for convenience */ 561 int tc_idx; /* traffic class */ 562 563 struct task tx_reclaim_task; 564 /* stats for common events first */ 565 566 uint64_t txcsum; /* # of times hardware assisted with checksum */ 567 uint64_t tso_wrs; /* # of TSO work requests */ 568 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 569 uint64_t imm_wrs; /* # of work requests with immediate data */ 570 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 571 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 572 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 573 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 574 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 575 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 576 577 /* stats for not-that-common events */ 578 } __aligned(CACHE_LINE_SIZE); 579 580 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 581 struct sge_rxq { 582 struct sge_iq iq; /* MUST be first */ 583 struct sge_fl fl; /* MUST follow iq */ 584 585 struct ifnet *ifp; /* the interface this rxq belongs to */ 586 #if defined(INET) || defined(INET6) 587 struct lro_ctrl lro; /* LRO state */ 588 #endif 589 590 /* stats for common events first */ 591 592 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 593 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 594 595 /* stats for not-that-common events */ 596 597 } __aligned(CACHE_LINE_SIZE); 598 599 static inline struct sge_rxq * 600 iq_to_rxq(struct sge_iq *iq) 601 { 602 603 return (__containerof(iq, struct sge_rxq, iq)); 604 } 605 606 607 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 608 struct sge_ofld_rxq { 609 struct sge_iq iq; /* MUST be first */ 610 struct sge_fl fl; /* MUST follow iq */ 611 } __aligned(CACHE_LINE_SIZE); 612 613 static inline struct sge_ofld_rxq * 614 iq_to_ofld_rxq(struct sge_iq *iq) 615 { 616 617 return (__containerof(iq, struct sge_ofld_rxq, iq)); 618 } 619 620 struct wrqe { 621 STAILQ_ENTRY(wrqe) link; 622 struct sge_wrq *wrq; 623 int wr_len; 624 char wr[] __aligned(16); 625 }; 626 627 struct wrq_cookie { 628 TAILQ_ENTRY(wrq_cookie) link; 629 int ndesc; 630 int pidx; 631 }; 632 633 /* 634 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 635 * and offload tx queues are of this type. 636 */ 637 struct sge_wrq { 638 struct sge_eq eq; /* MUST be first */ 639 640 struct adapter *adapter; 641 struct task wrq_tx_task; 642 643 /* Tx desc reserved but WR not "committed" yet. */ 644 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 645 646 /* List of WRs ready to go out as soon as descriptors are available. */ 647 STAILQ_HEAD(, wrqe) wr_list; 648 u_int nwr_pending; 649 u_int ndesc_needed; 650 651 /* stats for common events first */ 652 653 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 654 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 655 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 656 657 /* stats for not-that-common events */ 658 659 /* 660 * Scratch space for work requests that wrap around after reaching the 661 * status page, and some information about the last WR that used it. 662 */ 663 uint16_t ss_pidx; 664 uint16_t ss_len; 665 uint8_t ss[SGE_MAX_WR_LEN]; 666 667 } __aligned(CACHE_LINE_SIZE); 668 669 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 670 struct sge_nm_rxq { 671 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 672 struct vi_info *vi; 673 674 struct iq_desc *iq_desc; 675 uint16_t iq_abs_id; 676 uint16_t iq_cntxt_id; 677 uint16_t iq_cidx; 678 uint16_t iq_sidx; 679 uint8_t iq_gen; 680 681 __be64 *fl_desc; 682 uint16_t fl_cntxt_id; 683 uint32_t fl_cidx; 684 uint32_t fl_pidx; 685 uint32_t fl_sidx; 686 uint32_t fl_db_val; 687 u_int fl_hwidx:4; 688 689 u_int fl_db_saved; 690 u_int nid; /* netmap ring # for this queue */ 691 692 /* infrequently used items after this */ 693 694 bus_dma_tag_t iq_desc_tag; 695 bus_dmamap_t iq_desc_map; 696 bus_addr_t iq_ba; 697 int intr_idx; 698 699 bus_dma_tag_t fl_desc_tag; 700 bus_dmamap_t fl_desc_map; 701 bus_addr_t fl_ba; 702 } __aligned(CACHE_LINE_SIZE); 703 704 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 705 struct sge_nm_txq { 706 struct tx_desc *desc; 707 uint16_t cidx; 708 uint16_t pidx; 709 uint16_t sidx; 710 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 711 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 712 uint16_t dbidx; /* pidx of the most recent doorbell */ 713 uint8_t doorbells; 714 volatile uint32_t *udb; 715 u_int udb_qid; 716 u_int cntxt_id; 717 __be32 cpl_ctrl0; /* for convenience */ 718 u_int nid; /* netmap ring # for this queue */ 719 720 /* infrequently used items after this */ 721 722 bus_dma_tag_t desc_tag; 723 bus_dmamap_t desc_map; 724 bus_addr_t ba; 725 int iqidx; 726 } __aligned(CACHE_LINE_SIZE); 727 728 struct sge { 729 int nrxq; /* total # of Ethernet rx queues */ 730 int ntxq; /* total # of Ethernet tx queues */ 731 int nofldrxq; /* total # of TOE rx queues */ 732 int nofldtxq; /* total # of TOE tx queues */ 733 int nnmrxq; /* total # of netmap rx queues */ 734 int nnmtxq; /* total # of netmap tx queues */ 735 int niq; /* total # of ingress queues */ 736 int neq; /* total # of egress queues */ 737 738 struct sge_iq fwq; /* Firmware event queue */ 739 struct sge_wrq *ctrlq; /* Control queues */ 740 struct sge_txq *txq; /* NIC tx queues */ 741 struct sge_rxq *rxq; /* NIC rx queues */ 742 struct sge_wrq *ofld_txq; /* TOE tx queues */ 743 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 744 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 745 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 746 747 uint16_t iq_start; /* first cntxt_id */ 748 uint16_t iq_base; /* first abs_id */ 749 int eq_start; /* first cntxt_id */ 750 int eq_base; /* first abs_id */ 751 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 752 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 753 754 int8_t safe_hwidx1; /* may not have room for metadata */ 755 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 756 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 757 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 758 }; 759 760 struct devnames { 761 const char *nexus_name; 762 const char *ifnet_name; 763 const char *vi_ifnet_name; 764 const char *pf03_drv_name; 765 const char *vf_nexus_name; 766 const char *vf_ifnet_name; 767 }; 768 769 struct adapter { 770 SLIST_ENTRY(adapter) link; 771 device_t dev; 772 struct cdev *cdev; 773 const struct devnames *names; 774 775 /* PCIe register resources */ 776 int regs_rid; 777 struct resource *regs_res; 778 int msix_rid; 779 struct resource *msix_res; 780 bus_space_handle_t bh; 781 bus_space_tag_t bt; 782 bus_size_t mmio_len; 783 int udbs_rid; 784 struct resource *udbs_res; 785 volatile uint8_t *udbs_base; 786 787 unsigned int pf; 788 unsigned int mbox; 789 unsigned int vpd_busy; 790 unsigned int vpd_flag; 791 792 /* Interrupt information */ 793 int intr_type; 794 int intr_count; 795 struct irq { 796 struct resource *res; 797 int rid; 798 void *tag; 799 struct sge_rxq *rxq; 800 struct sge_nm_rxq *nm_rxq; 801 } __aligned(CACHE_LINE_SIZE) *irq; 802 int sge_gts_reg; 803 int sge_kdoorbell_reg; 804 805 bus_dma_tag_t dmat; /* Parent DMA tag */ 806 807 struct sge sge; 808 int lro_timeout; 809 int sc_do_rxcopy; 810 811 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 812 struct port_info *port[MAX_NPORTS]; 813 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 814 815 void *tom_softc; /* (struct tom_data *) */ 816 struct tom_tunables tt; 817 struct t4_offload_policy *policy; 818 struct rwlock policy_lock; 819 820 void *iwarp_softc; /* (struct c4iw_dev *) */ 821 struct iw_tunables iwt; 822 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 823 void *ccr_softc; /* (struct ccr_softc *) */ 824 struct l2t_data *l2t; /* L2 table */ 825 struct smt_data *smt; /* Source MAC Table */ 826 struct tid_info tids; 827 828 uint8_t doorbells; 829 int offload_map; /* ports with IFCAP_TOE enabled */ 830 int active_ulds; /* ULDs activated on this adapter */ 831 int flags; 832 int debug_flags; 833 834 char ifp_lockname[16]; 835 struct mtx ifp_lock; 836 struct ifnet *ifp; /* tracer ifp */ 837 struct ifmedia media; 838 int traceq; /* iq used by all tracers, -1 if none */ 839 int tracer_valid; /* bitmap of valid tracers */ 840 int tracer_enabled; /* bitmap of enabled tracers */ 841 842 char fw_version[16]; 843 char tp_version[16]; 844 char er_version[16]; 845 char bs_version[16]; 846 char cfg_file[32]; 847 u_int cfcsum; 848 struct adapter_params params; 849 const struct chip_params *chip_params; 850 struct t4_virt_res vres; 851 852 uint16_t nbmcaps; 853 uint16_t linkcaps; 854 uint16_t switchcaps; 855 uint16_t niccaps; 856 uint16_t toecaps; 857 uint16_t rdmacaps; 858 uint16_t cryptocaps; 859 uint16_t iscsicaps; 860 uint16_t fcoecaps; 861 862 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 863 864 struct mtx sc_lock; 865 char lockname[16]; 866 867 /* Starving free lists */ 868 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 869 TAILQ_HEAD(, sge_fl) sfl; 870 struct callout sfl_callout; 871 872 struct mtx reg_lock; /* for indirect register access */ 873 874 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 875 876 struct mtx tc_lock; 877 struct task tc_task; 878 879 const char *last_op; 880 const void *last_op_thr; 881 int last_op_flags; 882 }; 883 884 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 885 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 886 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 887 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 888 889 #define ASSERT_SYNCHRONIZED_OP(sc) \ 890 KASSERT(IS_BUSY(sc) && \ 891 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 892 ("%s: operation not synchronized.", __func__)) 893 894 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 895 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 896 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 897 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 898 899 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 900 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 901 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 902 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 903 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 904 905 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 906 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 907 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 908 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 909 910 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 911 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 912 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 913 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 914 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 915 916 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 917 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 918 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 919 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 920 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 921 922 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 923 do { \ 924 if (sc->debug_flags & DF_DUMP_MBOX) { \ 925 log(LOG_NOTICE, \ 926 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 927 "%016llx %016llx %016llx %016llx\n", \ 928 device_get_nameunit(sc->dev), mbox, \ 929 (unsigned long long)t4_read_reg64(sc, data_reg), \ 930 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 931 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 932 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 933 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 934 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 935 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 936 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 937 } \ 938 } while (0) 939 940 #define for_each_txq(vi, iter, q) \ 941 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 942 iter < vi->ntxq; ++iter, ++q) 943 #define for_each_rxq(vi, iter, q) \ 944 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 945 iter < vi->nrxq; ++iter, ++q) 946 #define for_each_ofld_txq(vi, iter, q) \ 947 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 948 iter < vi->nofldtxq; ++iter, ++q) 949 #define for_each_ofld_rxq(vi, iter, q) \ 950 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 951 iter < vi->nofldrxq; ++iter, ++q) 952 #define for_each_nm_txq(vi, iter, q) \ 953 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 954 iter < vi->nnmtxq; ++iter, ++q) 955 #define for_each_nm_rxq(vi, iter, q) \ 956 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 957 iter < vi->nnmrxq; ++iter, ++q) 958 #define for_each_vi(_pi, _iter, _vi) \ 959 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 960 ++(_iter), ++(_vi)) 961 962 #define IDXINCR(idx, incr, wrap) do { \ 963 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 964 } while (0) 965 #define IDXDIFF(head, tail, wrap) \ 966 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 967 968 /* One for errors, one for firmware events */ 969 #define T4_EXTRA_INTR 2 970 971 /* One for firmware events */ 972 #define T4VF_EXTRA_INTR 1 973 974 static inline int 975 forwarding_intr_to_fwq(struct adapter *sc) 976 { 977 978 return (sc->intr_count == 1); 979 } 980 981 static inline uint32_t 982 t4_read_reg(struct adapter *sc, uint32_t reg) 983 { 984 985 return bus_space_read_4(sc->bt, sc->bh, reg); 986 } 987 988 static inline void 989 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 990 { 991 992 bus_space_write_4(sc->bt, sc->bh, reg, val); 993 } 994 995 static inline uint64_t 996 t4_read_reg64(struct adapter *sc, uint32_t reg) 997 { 998 999 #ifdef __LP64__ 1000 return bus_space_read_8(sc->bt, sc->bh, reg); 1001 #else 1002 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1003 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1004 1005 #endif 1006 } 1007 1008 static inline void 1009 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1010 { 1011 1012 #ifdef __LP64__ 1013 bus_space_write_8(sc->bt, sc->bh, reg, val); 1014 #else 1015 bus_space_write_4(sc->bt, sc->bh, reg, val); 1016 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1017 #endif 1018 } 1019 1020 static inline void 1021 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1022 { 1023 1024 *val = pci_read_config(sc->dev, reg, 1); 1025 } 1026 1027 static inline void 1028 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1029 { 1030 1031 pci_write_config(sc->dev, reg, val, 1); 1032 } 1033 1034 static inline void 1035 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1036 { 1037 1038 *val = pci_read_config(sc->dev, reg, 2); 1039 } 1040 1041 static inline void 1042 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1043 { 1044 1045 pci_write_config(sc->dev, reg, val, 2); 1046 } 1047 1048 static inline void 1049 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1050 { 1051 1052 *val = pci_read_config(sc->dev, reg, 4); 1053 } 1054 1055 static inline void 1056 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1057 { 1058 1059 pci_write_config(sc->dev, reg, val, 4); 1060 } 1061 1062 static inline struct port_info * 1063 adap2pinfo(struct adapter *sc, int idx) 1064 { 1065 1066 return (sc->port[idx]); 1067 } 1068 1069 static inline void 1070 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1071 { 1072 1073 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1074 } 1075 1076 static inline bool 1077 is_10G_port(const struct port_info *pi) 1078 { 1079 1080 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1081 } 1082 1083 static inline bool 1084 is_25G_port(const struct port_info *pi) 1085 { 1086 1087 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1088 } 1089 1090 static inline bool 1091 is_40G_port(const struct port_info *pi) 1092 { 1093 1094 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1095 } 1096 1097 static inline bool 1098 is_100G_port(const struct port_info *pi) 1099 { 1100 1101 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1102 } 1103 1104 static inline int 1105 port_top_speed(const struct port_info *pi) 1106 { 1107 1108 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1109 return (100); 1110 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1111 return (40); 1112 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1113 return (25); 1114 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1115 return (10); 1116 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1117 return (1); 1118 1119 return (0); 1120 } 1121 1122 static inline int 1123 tx_resume_threshold(struct sge_eq *eq) 1124 { 1125 1126 /* not quite the same as qsize / 4, but this will do. */ 1127 return (eq->sidx / 4); 1128 } 1129 1130 static inline int 1131 t4_use_ldst(struct adapter *sc) 1132 { 1133 1134 #ifdef notyet 1135 return (sc->flags & FW_OK || !sc->use_bd); 1136 #else 1137 return (0); 1138 #endif 1139 } 1140 1141 /* t4_main.c */ 1142 extern int t4_ntxq; 1143 extern int t4_nrxq; 1144 extern int t4_intr_types; 1145 extern int t4_tmr_idx; 1146 extern int t4_pktc_idx; 1147 extern unsigned int t4_qsize_rxq; 1148 extern unsigned int t4_qsize_txq; 1149 extern device_method_t cxgbe_methods[]; 1150 1151 int t4_os_find_pci_capability(struct adapter *, int); 1152 int t4_os_pci_save_state(struct adapter *); 1153 int t4_os_pci_restore_state(struct adapter *); 1154 void t4_os_portmod_changed(struct port_info *); 1155 void t4_os_link_changed(struct port_info *); 1156 void t4_iterate(void (*)(struct adapter *, void *), void *); 1157 void t4_init_devnames(struct adapter *); 1158 void t4_add_adapter(struct adapter *); 1159 void t4_aes_getdeckey(void *, const void *, unsigned int); 1160 int t4_detach_common(device_t); 1161 int t4_map_bars_0_and_4(struct adapter *); 1162 int t4_map_bar_2(struct adapter *); 1163 int t4_setup_intr_handlers(struct adapter *); 1164 void t4_sysctls(struct adapter *); 1165 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1166 void doom_vi(struct adapter *, struct vi_info *); 1167 void end_synchronized_op(struct adapter *, int); 1168 int update_mac_settings(struct ifnet *, int); 1169 int adapter_full_init(struct adapter *); 1170 int adapter_full_uninit(struct adapter *); 1171 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1172 int vi_full_init(struct vi_info *); 1173 int vi_full_uninit(struct vi_info *); 1174 void vi_sysctls(struct vi_info *); 1175 void vi_tick(void *); 1176 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1177 int alloc_atid_tab(struct tid_info *, int); 1178 void free_atid_tab(struct tid_info *); 1179 int alloc_atid(struct adapter *, void *); 1180 void *lookup_atid(struct adapter *, int); 1181 void free_atid(struct adapter *, int); 1182 void release_tid(struct adapter *, int, struct sge_wrq *); 1183 1184 #ifdef DEV_NETMAP 1185 /* t4_netmap.c */ 1186 struct sge_nm_rxq; 1187 void cxgbe_nm_attach(struct vi_info *); 1188 void cxgbe_nm_detach(struct vi_info *); 1189 void service_nm_rxq(struct sge_nm_rxq *); 1190 #endif 1191 1192 /* t4_sge.c */ 1193 void t4_sge_modload(void); 1194 void t4_sge_modunload(void); 1195 uint64_t t4_sge_extfree_refs(void); 1196 void t4_tweak_chip_settings(struct adapter *); 1197 int t4_read_chip_settings(struct adapter *); 1198 int t4_create_dma_tag(struct adapter *); 1199 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1200 struct sysctl_oid_list *); 1201 int t4_destroy_dma_tag(struct adapter *); 1202 int t4_setup_adapter_queues(struct adapter *); 1203 int t4_teardown_adapter_queues(struct adapter *); 1204 int t4_setup_vi_queues(struct vi_info *); 1205 int t4_teardown_vi_queues(struct vi_info *); 1206 void t4_intr_all(void *); 1207 void t4_intr(void *); 1208 #ifdef DEV_NETMAP 1209 void t4_nm_intr(void *); 1210 void t4_vi_intr(void *); 1211 #endif 1212 void t4_intr_err(void *); 1213 void t4_intr_evt(void *); 1214 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1215 void t4_update_fl_bufsize(struct ifnet *); 1216 int parse_pkt(struct adapter *, struct mbuf **); 1217 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1218 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1219 int tnl_cong(struct port_info *, int); 1220 void t4_register_an_handler(an_handler_t); 1221 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1222 void t4_register_cpl_handler(int, cpl_handler_t); 1223 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1224 #ifdef RATELIMIT 1225 int ethofld_transmit(struct ifnet *, struct mbuf *); 1226 void send_etid_flush_wr(struct cxgbe_snd_tag *); 1227 #endif 1228 1229 /* t4_tracer.c */ 1230 struct t4_tracer; 1231 void t4_tracer_modload(void); 1232 void t4_tracer_modunload(void); 1233 void t4_tracer_port_detach(struct adapter *); 1234 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1235 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1236 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1237 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1238 1239 /* t4_sched.c */ 1240 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1241 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1242 int t4_init_tx_sched(struct adapter *); 1243 int t4_free_tx_sched(struct adapter *); 1244 void t4_update_tx_sched(struct adapter *); 1245 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1246 void t4_release_cl_rl(struct adapter *, int, int); 1247 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1248 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1249 #ifdef RATELIMIT 1250 void t4_init_etid_table(struct adapter *); 1251 void t4_free_etid_table(struct adapter *); 1252 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int); 1253 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1254 struct m_snd_tag **); 1255 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1256 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1257 void cxgbe_snd_tag_free(struct m_snd_tag *); 1258 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *); 1259 #endif 1260 1261 /* t4_filter.c */ 1262 int get_filter_mode(struct adapter *, uint32_t *); 1263 int set_filter_mode(struct adapter *, uint32_t); 1264 int get_filter(struct adapter *, struct t4_filter *); 1265 int set_filter(struct adapter *, struct t4_filter *); 1266 int del_filter(struct adapter *, struct t4_filter *); 1267 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1268 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1269 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1270 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1271 void free_hftid_hash(struct tid_info *); 1272 1273 static inline struct wrqe * 1274 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1275 { 1276 int len = offsetof(struct wrqe, wr) + wr_len; 1277 struct wrqe *wr; 1278 1279 wr = malloc(len, M_CXGBE, M_NOWAIT); 1280 if (__predict_false(wr == NULL)) 1281 return (NULL); 1282 wr->wr_len = wr_len; 1283 wr->wrq = wrq; 1284 return (wr); 1285 } 1286 1287 static inline void * 1288 wrtod(struct wrqe *wr) 1289 { 1290 return (&wr->wr[0]); 1291 } 1292 1293 static inline void 1294 free_wrqe(struct wrqe *wr) 1295 { 1296 free(wr, M_CXGBE); 1297 } 1298 1299 static inline void 1300 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1301 { 1302 struct sge_wrq *wrq = wr->wrq; 1303 1304 TXQ_LOCK(wrq); 1305 t4_wrq_tx_locked(sc, wrq, wr); 1306 TXQ_UNLOCK(wrq); 1307 } 1308 1309 static inline int 1310 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1311 int len) 1312 { 1313 1314 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1315 } 1316 1317 static inline int 1318 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1319 const uint32_t *val, int len) 1320 { 1321 1322 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1323 } 1324 #endif 1325