1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 MALLOC_DECLARE(M_CXGBE); 61 #define CXGBE_UNIMPLEMENTED(s) \ 62 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 63 64 #if defined(__i386__) || defined(__amd64__) 65 static __inline void 66 prefetch(void *x) 67 { 68 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 69 } 70 #else 71 #define prefetch(x) 72 #endif 73 74 #ifndef SYSCTL_ADD_UQUAD 75 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 76 #define sysctl_handle_64 sysctl_handle_quad 77 #define CTLTYPE_U64 CTLTYPE_QUAD 78 #endif 79 80 #if (__FreeBSD_version >= 900030) || \ 81 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 82 #define SBUF_DRAIN 1 83 #endif 84 85 #ifdef __amd64__ 86 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 87 static __inline uint64_t 88 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 89 bus_size_t offset) 90 { 91 KASSERT(tag == X86_BUS_SPACE_MEM, 92 ("%s: can only handle mem space", __func__)); 93 94 return (*(volatile uint64_t *)(handle + offset)); 95 } 96 97 static __inline void 98 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 99 bus_size_t offset, uint64_t value) 100 { 101 KASSERT(tag == X86_BUS_SPACE_MEM, 102 ("%s: can only handle mem space", __func__)); 103 104 *(volatile uint64_t *)(bsh + offset) = value; 105 } 106 #else 107 static __inline uint64_t 108 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 109 bus_size_t offset) 110 { 111 return (uint64_t)bus_space_read_4(tag, handle, offset) + 112 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 113 } 114 115 static __inline void 116 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 117 bus_size_t offset, uint64_t value) 118 { 119 bus_space_write_4(tag, bsh, offset, value); 120 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 121 } 122 #endif 123 124 struct adapter; 125 typedef struct adapter adapter_t; 126 127 enum { 128 FW_IQ_QSIZE = 256, 129 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 130 131 RX_IQ_QSIZE = 1024, 132 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 133 134 EQ_ESIZE = 64, /* All egress queues use this entry size */ 135 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 136 137 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 138 #if MJUMPAGESIZE != MCLBYTES 139 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 140 #else 141 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 142 #endif 143 CL_METADATA_SIZE = CACHE_LINE_SIZE, 144 145 CTRL_EQ_QSIZE = 128, 146 147 TX_EQ_QSIZE = 1024, 148 TX_SGL_SEGS = 36, 149 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 150 }; 151 152 enum { 153 /* adapter intr_type */ 154 INTR_INTX = (1 << 0), 155 INTR_MSI = (1 << 1), 156 INTR_MSIX = (1 << 2) 157 }; 158 159 enum { 160 XGMAC_MTU = (1 << 0), 161 XGMAC_PROMISC = (1 << 1), 162 XGMAC_ALLMULTI = (1 << 2), 163 XGMAC_VLANEX = (1 << 3), 164 XGMAC_UCADDR = (1 << 4), 165 XGMAC_MCADDRS = (1 << 5), 166 167 XGMAC_ALL = 0xffff 168 }; 169 170 enum { 171 /* flags understood by begin_synchronized_op */ 172 HOLD_LOCK = (1 << 0), 173 SLEEP_OK = (1 << 1), 174 INTR_OK = (1 << 2), 175 176 /* flags understood by end_synchronized_op */ 177 LOCK_HELD = HOLD_LOCK, 178 }; 179 180 enum { 181 /* adapter flags */ 182 FULL_INIT_DONE = (1 << 0), 183 FW_OK = (1 << 1), 184 /* INTR_DIRECT = (1 << 2), No longer used. */ 185 MASTER_PF = (1 << 3), 186 ADAP_SYSCTL_CTX = (1 << 4), 187 TOM_INIT_DONE = (1 << 5), 188 BUF_PACKING_OK = (1 << 6), 189 190 CXGBE_BUSY = (1 << 9), 191 192 /* port flags */ 193 DOOMED = (1 << 0), 194 PORT_INIT_DONE = (1 << 1), 195 PORT_SYSCTL_CTX = (1 << 2), 196 HAS_TRACEQ = (1 << 3), 197 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 198 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 199 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */ 200 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ), 201 }; 202 203 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 204 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 205 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 206 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 207 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 208 209 struct port_info { 210 device_t dev; 211 struct adapter *adapter; 212 213 struct ifnet *ifp; 214 struct ifmedia media; 215 216 struct mtx pi_lock; 217 char lockname[16]; 218 unsigned long flags; 219 int if_flags; 220 221 uint16_t *rss; 222 uint16_t viid; 223 int16_t xact_addr_filt;/* index of exact MAC address filter */ 224 uint16_t rss_size; /* size of VI's RSS table slice */ 225 uint8_t lport; /* associated offload logical port */ 226 int8_t mdio_addr; 227 uint8_t port_type; 228 uint8_t mod_type; 229 uint8_t port_id; 230 uint8_t tx_chan; 231 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 232 233 /* These need to be int as they are used in sysctl */ 234 int ntxq; /* # of tx queues */ 235 int first_txq; /* index of first tx queue */ 236 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 237 int nrxq; /* # of rx queues */ 238 int first_rxq; /* index of first rx queue */ 239 #ifdef TCP_OFFLOAD 240 int nofldtxq; /* # of offload tx queues */ 241 int first_ofld_txq; /* index of first offload tx queue */ 242 int nofldrxq; /* # of offload rx queues */ 243 int first_ofld_rxq; /* index of first offload rx queue */ 244 #endif 245 #ifdef DEV_NETMAP 246 int nnmtxq; /* # of netmap tx queues */ 247 int first_nm_txq; /* index of first netmap tx queue */ 248 int nnmrxq; /* # of netmap rx queues */ 249 int first_nm_rxq; /* index of first netmap rx queue */ 250 251 struct ifnet *nm_ifp; 252 struct ifmedia nm_media; 253 int nmif_flags; 254 uint16_t nm_viid; 255 int16_t nm_xact_addr_filt; 256 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */ 257 #endif 258 int tmr_idx; 259 int pktc_idx; 260 int qsize_rxq; 261 int qsize_txq; 262 263 int linkdnrc; 264 struct link_config link_cfg; 265 struct port_stats stats; 266 267 eventhandler_tag vlan_c; 268 269 struct callout tick; 270 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 271 272 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 273 }; 274 275 /* Where the cluster came from, how it has been carved up. */ 276 struct cluster_layout { 277 int8_t zidx; 278 int8_t hwidx; 279 uint16_t region1; /* mbufs laid out within this region */ 280 /* region2 is the DMA region */ 281 uint16_t region3; /* cluster_metadata within this region */ 282 }; 283 284 struct cluster_metadata { 285 u_int refcount; 286 #ifdef INVARIANTS 287 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 288 #endif 289 }; 290 291 struct fl_sdesc { 292 caddr_t cl; 293 uint8_t nimbuf; /* # of inline mbufs with ref on the cluster */ 294 uint8_t nembuf; /* # of allocated mbufs with ref */ 295 struct cluster_layout cll; 296 }; 297 298 struct tx_desc { 299 __be64 flit[8]; 300 }; 301 302 struct tx_map { 303 struct mbuf *m; 304 bus_dmamap_t map; 305 }; 306 307 /* DMA maps used for tx */ 308 struct tx_maps { 309 struct tx_map *maps; 310 uint32_t map_total; /* # of DMA maps */ 311 uint32_t map_pidx; /* next map to be used */ 312 uint32_t map_cidx; /* reclaimed up to this index */ 313 uint32_t map_avail; /* # of available maps */ 314 }; 315 316 struct tx_sdesc { 317 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 318 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 319 }; 320 321 enum { 322 /* iq flags */ 323 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 324 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 325 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 326 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 327 328 /* iq state */ 329 IQS_DISABLED = 0, 330 IQS_BUSY = 1, 331 IQS_IDLE = 2, 332 }; 333 334 /* 335 * Ingress Queue: T4 is producer, driver is consumer. 336 */ 337 struct sge_iq { 338 bus_dma_tag_t desc_tag; 339 bus_dmamap_t desc_map; 340 bus_addr_t ba; /* bus address of descriptor ring */ 341 uint32_t flags; 342 uint16_t abs_id; /* absolute SGE id for the iq */ 343 int8_t intr_pktc_idx; /* packet count threshold index */ 344 int8_t pad0; 345 __be64 *desc; /* KVA of descriptor ring */ 346 347 volatile int state; 348 struct adapter *adapter; 349 const __be64 *cdesc; /* current descriptor */ 350 uint8_t gen; /* generation bit */ 351 uint8_t intr_params; /* interrupt holdoff parameters */ 352 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 353 uint8_t esize; /* size (bytes) of each entry in the queue */ 354 uint16_t qsize; /* size (# of entries) of the queue */ 355 uint16_t cidx; /* consumer index */ 356 uint16_t cntxt_id; /* SGE context id for the iq */ 357 358 STAILQ_ENTRY(sge_iq) link; 359 }; 360 361 enum { 362 EQ_CTRL = 1, 363 EQ_ETH = 2, 364 #ifdef TCP_OFFLOAD 365 EQ_OFLD = 3, 366 #endif 367 368 /* eq flags */ 369 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 370 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 371 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 372 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 373 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 374 }; 375 376 /* Listed in order of preference. Update t4_sysctls too if you change these */ 377 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 378 379 /* 380 * Egress Queue: driver is producer, T4 is consumer. 381 * 382 * Note: A free list is an egress queue (driver produces the buffers and T4 383 * consumes them) but it's special enough to have its own struct (see sge_fl). 384 */ 385 struct sge_eq { 386 unsigned int flags; /* MUST be first */ 387 unsigned int cntxt_id; /* SGE context id for the eq */ 388 bus_dma_tag_t desc_tag; 389 bus_dmamap_t desc_map; 390 char lockname[16]; 391 struct mtx eq_lock; 392 393 struct tx_desc *desc; /* KVA of descriptor ring */ 394 bus_addr_t ba; /* bus address of descriptor ring */ 395 struct sge_qstat *spg; /* status page, for convenience */ 396 uint16_t doorbells; 397 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 398 u_int udb_qid; /* relative qid within the doorbell page */ 399 uint16_t cap; /* max # of desc, for convenience */ 400 uint16_t avail; /* available descriptors, for convenience */ 401 uint16_t qsize; /* size (# of entries) of the queue */ 402 uint16_t cidx; /* consumer idx (desc idx) */ 403 uint16_t pidx; /* producer idx (desc idx) */ 404 uint16_t pending; /* # of descriptors used since last doorbell */ 405 uint16_t iqid; /* iq that gets egr_update for the eq */ 406 uint8_t tx_chan; /* tx channel used by the eq */ 407 struct task tx_task; 408 struct callout tx_callout; 409 410 /* stats */ 411 412 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 413 uint32_t unstalled; /* recovered from stall */ 414 }; 415 416 struct sw_zone_info { 417 uma_zone_t zone; /* zone that this cluster comes from */ 418 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 419 int type; /* EXT_xxx type of the cluster */ 420 int8_t head_hwidx; 421 int8_t tail_hwidx; 422 }; 423 424 struct hw_buf_info { 425 int8_t zidx; /* backpointer to zone; -ve means unused */ 426 int8_t next; /* next hwidx for this zone; -1 means no more */ 427 int size; 428 }; 429 430 enum { 431 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 432 FL_DOOMED = (1 << 1), /* about to be destroyed */ 433 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 434 }; 435 436 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 437 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 438 439 struct sge_fl { 440 bus_dma_tag_t desc_tag; 441 bus_dmamap_t desc_map; 442 struct cluster_layout cll_def; /* default refill zone, layout */ 443 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 444 struct mtx fl_lock; 445 char lockname[16]; 446 int flags; 447 448 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 449 bus_addr_t ba; /* bus address of descriptor ring */ 450 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 451 uint32_t cap; /* max # of buffers, for convenience */ 452 uint16_t qsize; /* size (# of entries) of the queue */ 453 uint16_t cntxt_id; /* SGE context id for the freelist */ 454 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 455 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 456 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 457 uint32_t needed; /* # of buffers needed to fill up fl. */ 458 uint32_t lowat; /* # of buffers <= this means fl needs help */ 459 uint32_t pending; /* # of bufs allocated since last doorbell */ 460 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 461 462 struct mbuf *m0; 463 struct mbuf **pnext; 464 u_int remaining; 465 466 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 467 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 468 uint64_t cl_allocated; /* # of clusters allocated */ 469 uint64_t cl_recycled; /* # of clusters recycled */ 470 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 471 }; 472 473 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 474 struct sge_txq { 475 struct sge_eq eq; /* MUST be first */ 476 477 struct ifnet *ifp; /* the interface this txq belongs to */ 478 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 479 struct buf_ring *br; /* tx buffer ring */ 480 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 481 struct mbuf *m; /* held up due to temporary resource shortage */ 482 483 struct tx_maps txmaps; 484 485 /* stats for common events first */ 486 487 uint64_t txcsum; /* # of times hardware assisted with checksum */ 488 uint64_t tso_wrs; /* # of TSO work requests */ 489 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 490 uint64_t imm_wrs; /* # of work requests with immediate data */ 491 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 492 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 493 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 494 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 495 496 /* stats for not-that-common events */ 497 498 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 499 uint32_t no_desc; /* out of hardware descriptors */ 500 } __aligned(CACHE_LINE_SIZE); 501 502 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 503 struct sge_rxq { 504 struct sge_iq iq; /* MUST be first */ 505 struct sge_fl fl; /* MUST follow iq */ 506 507 struct ifnet *ifp; /* the interface this rxq belongs to */ 508 #if defined(INET) || defined(INET6) 509 struct lro_ctrl lro; /* LRO state */ 510 #endif 511 512 /* stats for common events first */ 513 514 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 515 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 516 517 /* stats for not-that-common events */ 518 519 } __aligned(CACHE_LINE_SIZE); 520 521 static inline struct sge_rxq * 522 iq_to_rxq(struct sge_iq *iq) 523 { 524 525 return (__containerof(iq, struct sge_rxq, iq)); 526 } 527 528 529 #ifdef TCP_OFFLOAD 530 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 531 struct sge_ofld_rxq { 532 struct sge_iq iq; /* MUST be first */ 533 struct sge_fl fl; /* MUST follow iq */ 534 } __aligned(CACHE_LINE_SIZE); 535 536 static inline struct sge_ofld_rxq * 537 iq_to_ofld_rxq(struct sge_iq *iq) 538 { 539 540 return (__containerof(iq, struct sge_ofld_rxq, iq)); 541 } 542 #endif 543 544 struct wrqe { 545 STAILQ_ENTRY(wrqe) link; 546 struct sge_wrq *wrq; 547 int wr_len; 548 uint64_t wr[] __aligned(16); 549 }; 550 551 /* 552 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 553 * and offload tx queues are of this type. 554 */ 555 struct sge_wrq { 556 struct sge_eq eq; /* MUST be first */ 557 558 struct adapter *adapter; 559 560 /* List of WRs held up due to lack of tx descriptors */ 561 STAILQ_HEAD(, wrqe) wr_list; 562 563 /* stats for common events first */ 564 565 uint64_t tx_wrs; /* # of tx work requests */ 566 567 /* stats for not-that-common events */ 568 569 uint32_t no_desc; /* out of hardware descriptors */ 570 } __aligned(CACHE_LINE_SIZE); 571 572 573 #ifdef DEV_NETMAP 574 #define CPL_PAD (RX_IQ_ESIZE - sizeof(struct rsp_ctrl) - \ 575 sizeof(struct rss_header)) 576 struct nm_iq_desc { 577 struct rss_header rss; 578 union { 579 uint8_t cpl[CPL_PAD]; 580 struct cpl_fw6_msg fw6_msg; 581 struct cpl_rx_pkt rx_pkt; 582 } u; 583 struct rsp_ctrl rsp; 584 }; 585 CTASSERT(sizeof(struct nm_iq_desc) == RX_IQ_ESIZE); 586 587 struct sge_nm_rxq { 588 struct port_info *pi; 589 590 struct nm_iq_desc *iq_desc; 591 uint16_t iq_abs_id; 592 uint16_t iq_cntxt_id; 593 uint16_t iq_cidx; 594 uint16_t iq_sidx; 595 uint8_t iq_gen; 596 597 __be64 *fl_desc; 598 uint16_t fl_cntxt_id; 599 uint32_t fl_cidx; 600 uint32_t fl_pidx; 601 uint32_t fl_sidx; 602 uint32_t fl_db_val; 603 u_int fl_hwidx:4; 604 605 u_int nid; /* netmap ring # for this queue */ 606 607 /* infrequently used items after this */ 608 609 bus_dma_tag_t iq_desc_tag; 610 bus_dmamap_t iq_desc_map; 611 bus_addr_t iq_ba; 612 int intr_idx; 613 614 bus_dma_tag_t fl_desc_tag; 615 bus_dmamap_t fl_desc_map; 616 bus_addr_t fl_ba; 617 } __aligned(CACHE_LINE_SIZE); 618 619 struct sge_nm_txq { 620 struct tx_desc *desc; 621 uint16_t cidx; 622 uint16_t pidx; 623 uint16_t sidx; 624 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 625 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 626 uint16_t dbidx; /* pidx of the most recent doorbell */ 627 uint16_t doorbells; 628 volatile uint32_t *udb; 629 u_int udb_qid; 630 u_int cntxt_id; 631 __be32 cpl_ctrl0; /* for convenience */ 632 u_int nid; /* netmap ring # for this queue */ 633 634 /* infrequently used items after this */ 635 636 bus_dma_tag_t desc_tag; 637 bus_dmamap_t desc_map; 638 bus_addr_t ba; 639 int iqidx; 640 } __aligned(CACHE_LINE_SIZE); 641 #endif 642 643 struct sge { 644 int timer_val[SGE_NTIMERS]; 645 int counter_val[SGE_NCOUNTERS]; 646 int fl_starve_threshold; 647 int fl_starve_threshold2; 648 int eq_s_qpp; 649 int iq_s_qpp; 650 651 int nrxq; /* total # of Ethernet rx queues */ 652 int ntxq; /* total # of Ethernet tx tx queues */ 653 #ifdef TCP_OFFLOAD 654 int nofldrxq; /* total # of TOE rx queues */ 655 int nofldtxq; /* total # of TOE tx queues */ 656 #endif 657 #ifdef DEV_NETMAP 658 int nnmrxq; /* total # of netmap rx queues */ 659 int nnmtxq; /* total # of netmap tx queues */ 660 #endif 661 int niq; /* total # of ingress queues */ 662 int neq; /* total # of egress queues */ 663 664 struct sge_iq fwq; /* Firmware event queue */ 665 struct sge_wrq mgmtq; /* Management queue (control queue) */ 666 struct sge_wrq *ctrlq; /* Control queues */ 667 struct sge_txq *txq; /* NIC tx queues */ 668 struct sge_rxq *rxq; /* NIC rx queues */ 669 #ifdef TCP_OFFLOAD 670 struct sge_wrq *ofld_txq; /* TOE tx queues */ 671 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 672 #endif 673 #ifdef DEV_NETMAP 674 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 675 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 676 #endif 677 678 uint16_t iq_start; 679 int eq_start; 680 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 681 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 682 683 int pack_boundary; 684 int8_t safe_hwidx1; /* may not have room for metadata */ 685 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 686 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 687 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 688 }; 689 690 struct rss_header; 691 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 692 struct mbuf *); 693 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 694 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 695 696 struct adapter { 697 SLIST_ENTRY(adapter) link; 698 device_t dev; 699 struct cdev *cdev; 700 701 /* PCIe register resources */ 702 int regs_rid; 703 struct resource *regs_res; 704 int msix_rid; 705 struct resource *msix_res; 706 bus_space_handle_t bh; 707 bus_space_tag_t bt; 708 bus_size_t mmio_len; 709 int udbs_rid; 710 struct resource *udbs_res; 711 volatile uint8_t *udbs_base; 712 713 unsigned int pf; 714 unsigned int mbox; 715 716 /* Interrupt information */ 717 int intr_type; 718 int intr_count; 719 struct irq { 720 struct resource *res; 721 int rid; 722 void *tag; 723 } *irq; 724 725 bus_dma_tag_t dmat; /* Parent DMA tag */ 726 727 struct sge sge; 728 int lro_timeout; 729 730 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 731 struct port_info *port[MAX_NPORTS]; 732 uint8_t chan_map[NCHAN]; 733 734 #ifdef TCP_OFFLOAD 735 void *tom_softc; /* (struct tom_data *) */ 736 struct tom_tunables tt; 737 void *iwarp_softc; /* (struct c4iw_dev *) */ 738 #endif 739 struct l2t_data *l2t; /* L2 table */ 740 struct tid_info tids; 741 742 uint16_t doorbells; 743 int open_device_map; 744 #ifdef TCP_OFFLOAD 745 int offload_map; 746 #endif 747 int flags; 748 749 char ifp_lockname[16]; 750 struct mtx ifp_lock; 751 struct ifnet *ifp; /* tracer ifp */ 752 struct ifmedia media; 753 int traceq; /* iq used by all tracers, -1 if none */ 754 int tracer_valid; /* bitmap of valid tracers */ 755 int tracer_enabled; /* bitmap of enabled tracers */ 756 757 char fw_version[32]; 758 char cfg_file[32]; 759 u_int cfcsum; 760 struct adapter_params params; 761 struct t4_virt_res vres; 762 763 uint16_t linkcaps; 764 uint16_t niccaps; 765 uint16_t toecaps; 766 uint16_t rdmacaps; 767 uint16_t iscsicaps; 768 uint16_t fcoecaps; 769 770 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 771 772 struct mtx sc_lock; 773 char lockname[16]; 774 775 /* Starving free lists */ 776 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 777 TAILQ_HEAD(, sge_fl) sfl; 778 struct callout sfl_callout; 779 780 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 781 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 782 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 783 784 #ifdef INVARIANTS 785 const char *last_op; 786 const void *last_op_thr; 787 #endif 788 789 int sc_do_rxcopy; 790 }; 791 792 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 793 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 794 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 795 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 796 797 /* XXX: not bulletproof, but much better than nothing */ 798 #define ASSERT_SYNCHRONIZED_OP(sc) \ 799 KASSERT(IS_BUSY(sc) && \ 800 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 801 ("%s: operation not synchronized.", __func__)) 802 803 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 804 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 805 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 806 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 807 808 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 809 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 810 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 811 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 812 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 813 814 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 815 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 816 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 817 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 818 819 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 820 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 821 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 822 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 823 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 824 825 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 826 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 827 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 828 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 829 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 830 831 #define for_each_txq(pi, iter, q) \ 832 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 833 iter < pi->ntxq; ++iter, ++q) 834 #define for_each_rxq(pi, iter, q) \ 835 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 836 iter < pi->nrxq; ++iter, ++q) 837 #define for_each_ofld_txq(pi, iter, q) \ 838 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 839 iter < pi->nofldtxq; ++iter, ++q) 840 #define for_each_ofld_rxq(pi, iter, q) \ 841 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 842 iter < pi->nofldrxq; ++iter, ++q) 843 #define for_each_nm_txq(pi, iter, q) \ 844 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \ 845 iter < pi->nnmtxq; ++iter, ++q) 846 #define for_each_nm_rxq(pi, iter, q) \ 847 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \ 848 iter < pi->nnmrxq; ++iter, ++q) 849 850 /* One for errors, one for firmware events */ 851 #define T4_EXTRA_INTR 2 852 853 static inline uint32_t 854 t4_read_reg(struct adapter *sc, uint32_t reg) 855 { 856 857 return bus_space_read_4(sc->bt, sc->bh, reg); 858 } 859 860 static inline void 861 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 862 { 863 864 bus_space_write_4(sc->bt, sc->bh, reg, val); 865 } 866 867 static inline uint64_t 868 t4_read_reg64(struct adapter *sc, uint32_t reg) 869 { 870 871 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 872 } 873 874 static inline void 875 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 876 { 877 878 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 879 } 880 881 static inline void 882 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 883 { 884 885 *val = pci_read_config(sc->dev, reg, 1); 886 } 887 888 static inline void 889 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 890 { 891 892 pci_write_config(sc->dev, reg, val, 1); 893 } 894 895 static inline void 896 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 897 { 898 899 *val = pci_read_config(sc->dev, reg, 2); 900 } 901 902 static inline void 903 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 904 { 905 906 pci_write_config(sc->dev, reg, val, 2); 907 } 908 909 static inline void 910 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 911 { 912 913 *val = pci_read_config(sc->dev, reg, 4); 914 } 915 916 static inline void 917 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 918 { 919 920 pci_write_config(sc->dev, reg, val, 4); 921 } 922 923 static inline struct port_info * 924 adap2pinfo(struct adapter *sc, int idx) 925 { 926 927 return (sc->port[idx]); 928 } 929 930 static inline void 931 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 932 { 933 934 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 935 } 936 937 static inline bool 938 is_10G_port(const struct port_info *pi) 939 { 940 941 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 942 } 943 944 static inline bool 945 is_40G_port(const struct port_info *pi) 946 { 947 948 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 949 } 950 951 static inline int 952 tx_resume_threshold(struct sge_eq *eq) 953 { 954 955 return (eq->qsize / 4); 956 } 957 958 /* t4_main.c */ 959 void t4_tx_task(void *, int); 960 void t4_tx_callout(void *); 961 int t4_os_find_pci_capability(struct adapter *, int); 962 int t4_os_pci_save_state(struct adapter *); 963 int t4_os_pci_restore_state(struct adapter *); 964 void t4_os_portmod_changed(const struct adapter *, int); 965 void t4_os_link_changed(struct adapter *, int, int, int); 966 void t4_iterate(void (*)(struct adapter *, void *), void *); 967 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 968 int t4_register_an_handler(struct adapter *, an_handler_t); 969 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 970 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 971 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 972 void end_synchronized_op(struct adapter *, int); 973 int update_mac_settings(struct ifnet *, int); 974 int adapter_full_init(struct adapter *); 975 int adapter_full_uninit(struct adapter *); 976 int port_full_init(struct port_info *); 977 int port_full_uninit(struct port_info *); 978 979 #ifdef DEV_NETMAP 980 /* t4_netmap.c */ 981 int create_netmap_ifnet(struct port_info *); 982 int destroy_netmap_ifnet(struct port_info *); 983 void t4_nm_intr(void *); 984 #endif 985 986 /* t4_sge.c */ 987 void t4_sge_modload(void); 988 void t4_init_sge_cpl_handlers(struct adapter *); 989 void t4_tweak_chip_settings(struct adapter *); 990 int t4_read_chip_settings(struct adapter *); 991 int t4_create_dma_tag(struct adapter *); 992 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 993 struct sysctl_oid_list *); 994 int t4_destroy_dma_tag(struct adapter *); 995 int t4_setup_adapter_queues(struct adapter *); 996 int t4_teardown_adapter_queues(struct adapter *); 997 int t4_setup_port_queues(struct port_info *); 998 int t4_teardown_port_queues(struct port_info *); 999 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 1000 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 1001 void t4_intr_all(void *); 1002 void t4_intr(void *); 1003 void t4_intr_err(void *); 1004 void t4_intr_evt(void *); 1005 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1006 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 1007 void t4_update_fl_bufsize(struct ifnet *); 1008 int can_resume_tx(struct sge_eq *); 1009 1010 /* t4_tracer.c */ 1011 struct t4_tracer; 1012 void t4_tracer_modload(void); 1013 void t4_tracer_modunload(void); 1014 void t4_tracer_port_detach(struct adapter *); 1015 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1016 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1017 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1018 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1019 1020 static inline struct wrqe * 1021 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1022 { 1023 int len = offsetof(struct wrqe, wr) + wr_len; 1024 struct wrqe *wr; 1025 1026 wr = malloc(len, M_CXGBE, M_NOWAIT); 1027 if (__predict_false(wr == NULL)) 1028 return (NULL); 1029 wr->wr_len = wr_len; 1030 wr->wrq = wrq; 1031 return (wr); 1032 } 1033 1034 static inline void * 1035 wrtod(struct wrqe *wr) 1036 { 1037 return (&wr->wr[0]); 1038 } 1039 1040 static inline void 1041 free_wrqe(struct wrqe *wr) 1042 { 1043 free(wr, M_CXGBE); 1044 } 1045 1046 static inline void 1047 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1048 { 1049 struct sge_wrq *wrq = wr->wrq; 1050 1051 TXQ_LOCK(wrq); 1052 t4_wrq_tx_locked(sc, wrq, wr); 1053 TXQ_UNLOCK(wrq); 1054 } 1055 1056 #endif 1057