1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "t4_ioctl.h" 58 #include "common/t4_msg.h" 59 #include "firmware/t4fw_interface.h" 60 61 #define KTR_CXGBE KTR_SPARE3 62 MALLOC_DECLARE(M_CXGBE); 63 #define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66 #if defined(__i386__) || defined(__amd64__) 67 static __inline void 68 prefetch(void *x) 69 { 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71 } 72 #else 73 #define prefetch(x) 74 #endif 75 76 #ifndef SYSCTL_ADD_UQUAD 77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78 #define sysctl_handle_64 sysctl_handle_quad 79 #define CTLTYPE_U64 CTLTYPE_QUAD 80 #endif 81 82 #if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84 #define SBUF_DRAIN 1 85 #endif 86 87 #ifdef __amd64__ 88 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 89 static __inline uint64_t 90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 91 bus_size_t offset) 92 { 93 KASSERT(tag == X86_BUS_SPACE_MEM, 94 ("%s: can only handle mem space", __func__)); 95 96 return (*(volatile uint64_t *)(handle + offset)); 97 } 98 99 static __inline void 100 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 101 bus_size_t offset, uint64_t value) 102 { 103 KASSERT(tag == X86_BUS_SPACE_MEM, 104 ("%s: can only handle mem space", __func__)); 105 106 *(volatile uint64_t *)(bsh + offset) = value; 107 } 108 #else 109 static __inline uint64_t 110 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 111 bus_size_t offset) 112 { 113 return (uint64_t)bus_space_read_4(tag, handle, offset) + 114 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 115 } 116 117 static __inline void 118 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 119 bus_size_t offset, uint64_t value) 120 { 121 bus_space_write_4(tag, bsh, offset, value); 122 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 123 } 124 #endif 125 126 struct adapter; 127 typedef struct adapter adapter_t; 128 129 enum { 130 /* 131 * All ingress queues use this entry size. Note that the firmware event 132 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 133 * be at least 64. 134 */ 135 IQ_ESIZE = 64, 136 137 /* Default queue sizes for all kinds of ingress queues */ 138 FW_IQ_QSIZE = 256, 139 RX_IQ_QSIZE = 1024, 140 141 /* All egress queues use this entry size */ 142 EQ_ESIZE = 64, 143 144 /* Default queue sizes for all kinds of egress queues */ 145 CTRL_EQ_QSIZE = 128, 146 TX_EQ_QSIZE = 1024, 147 148 #if MJUMPAGESIZE != MCLBYTES 149 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 150 #else 151 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 152 #endif 153 CL_METADATA_SIZE = CACHE_LINE_SIZE, 154 155 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 156 TX_SGL_SEGS = 39, 157 TX_SGL_SEGS_TSO = 38, 158 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 159 }; 160 161 enum { 162 /* adapter intr_type */ 163 INTR_INTX = (1 << 0), 164 INTR_MSI = (1 << 1), 165 INTR_MSIX = (1 << 2) 166 }; 167 168 enum { 169 XGMAC_MTU = (1 << 0), 170 XGMAC_PROMISC = (1 << 1), 171 XGMAC_ALLMULTI = (1 << 2), 172 XGMAC_VLANEX = (1 << 3), 173 XGMAC_UCADDR = (1 << 4), 174 XGMAC_MCADDRS = (1 << 5), 175 176 XGMAC_ALL = 0xffff 177 }; 178 179 enum { 180 /* flags understood by begin_synchronized_op */ 181 HOLD_LOCK = (1 << 0), 182 SLEEP_OK = (1 << 1), 183 INTR_OK = (1 << 2), 184 185 /* flags understood by end_synchronized_op */ 186 LOCK_HELD = HOLD_LOCK, 187 }; 188 189 enum { 190 /* adapter flags */ 191 FULL_INIT_DONE = (1 << 0), 192 FW_OK = (1 << 1), 193 /* INTR_DIRECT = (1 << 2), No longer used. */ 194 MASTER_PF = (1 << 3), 195 ADAP_SYSCTL_CTX = (1 << 4), 196 /* TOM_INIT_DONE= (1 << 5), No longer used */ 197 BUF_PACKING_OK = (1 << 6), 198 199 CXGBE_BUSY = (1 << 9), 200 201 /* port flags */ 202 HAS_TRACEQ = (1 << 3), 203 204 /* VI flags */ 205 DOOMED = (1 << 0), 206 VI_INIT_DONE = (1 << 1), 207 VI_SYSCTL_CTX = (1 << 2), 208 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 209 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 210 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 211 VI_NETMAP = (1 << 6), 212 213 /* adapter debug_flags */ 214 DF_DUMP_MBOX = (1 << 0), 215 }; 216 217 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 218 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 219 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 220 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 221 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 222 223 struct vi_info { 224 device_t dev; 225 struct port_info *pi; 226 227 struct ifnet *ifp; 228 struct ifmedia media; 229 230 unsigned long flags; 231 int if_flags; 232 233 uint16_t *rss; 234 uint16_t viid; 235 int16_t xact_addr_filt;/* index of exact MAC address filter */ 236 uint16_t rss_size; /* size of VI's RSS table slice */ 237 uint16_t rss_base; /* start of VI's RSS table slice */ 238 239 eventhandler_tag vlan_c; 240 241 int nintr; 242 int first_intr; 243 244 /* These need to be int as they are used in sysctl */ 245 int ntxq; /* # of tx queues */ 246 int first_txq; /* index of first tx queue */ 247 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 248 int nrxq; /* # of rx queues */ 249 int first_rxq; /* index of first rx queue */ 250 int nofldtxq; /* # of offload tx queues */ 251 int first_ofld_txq; /* index of first offload tx queue */ 252 int nofldrxq; /* # of offload rx queues */ 253 int first_ofld_rxq; /* index of first offload rx queue */ 254 int tmr_idx; 255 int pktc_idx; 256 int qsize_rxq; 257 int qsize_txq; 258 259 struct timeval last_refreshed; 260 struct fw_vi_stats_vf stats; 261 262 struct callout tick; 263 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 264 265 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 266 }; 267 268 enum { 269 /* tx_sched_class flags */ 270 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */ 271 }; 272 273 struct tx_sched_class { 274 int refcount; 275 int flags; 276 struct t4_sched_class_params params; 277 }; 278 279 struct port_info { 280 device_t dev; 281 struct adapter *adapter; 282 283 struct vi_info *vi; 284 int nvi; 285 int up_vis; 286 int uld_vis; 287 288 struct tx_sched_class *tc; /* traffic classes for this channel */ 289 290 struct mtx pi_lock; 291 char lockname[16]; 292 unsigned long flags; 293 294 uint8_t lport; /* associated offload logical port */ 295 int8_t mdio_addr; 296 uint8_t port_type; 297 uint8_t mod_type; 298 uint8_t port_id; 299 uint8_t tx_chan; 300 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 301 302 int linkdnrc; 303 struct link_config link_cfg; 304 305 struct timeval last_refreshed; 306 struct port_stats stats; 307 u_int tnl_cong_drops; 308 u_int tx_parse_error; 309 310 struct callout tick; 311 }; 312 313 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 314 315 /* Where the cluster came from, how it has been carved up. */ 316 struct cluster_layout { 317 int8_t zidx; 318 int8_t hwidx; 319 uint16_t region1; /* mbufs laid out within this region */ 320 /* region2 is the DMA region */ 321 uint16_t region3; /* cluster_metadata within this region */ 322 }; 323 324 struct cluster_metadata { 325 u_int refcount; 326 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 327 }; 328 329 struct fl_sdesc { 330 caddr_t cl; 331 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 332 struct cluster_layout cll; 333 }; 334 335 struct tx_desc { 336 __be64 flit[8]; 337 }; 338 339 struct tx_sdesc { 340 struct mbuf *m; /* m_nextpkt linked chain of frames */ 341 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 342 }; 343 344 345 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 346 struct iq_desc { 347 struct rss_header rss; 348 uint8_t cpl[IQ_PAD]; 349 struct rsp_ctrl rsp; 350 }; 351 #undef IQ_PAD 352 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 353 354 enum { 355 /* iq flags */ 356 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 357 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 358 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 359 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 360 361 /* iq state */ 362 IQS_DISABLED = 0, 363 IQS_BUSY = 1, 364 IQS_IDLE = 2, 365 }; 366 367 /* 368 * Ingress Queue: T4 is producer, driver is consumer. 369 */ 370 struct sge_iq { 371 uint32_t flags; 372 volatile int state; 373 struct adapter *adapter; 374 struct iq_desc *desc; /* KVA of descriptor ring */ 375 int8_t intr_pktc_idx; /* packet count threshold index */ 376 uint8_t gen; /* generation bit */ 377 uint8_t intr_params; /* interrupt holdoff parameters */ 378 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 379 uint16_t qsize; /* size (# of entries) of the queue */ 380 uint16_t sidx; /* index of the entry with the status page */ 381 uint16_t cidx; /* consumer index */ 382 uint16_t cntxt_id; /* SGE context id for the iq */ 383 uint16_t abs_id; /* absolute SGE id for the iq */ 384 385 STAILQ_ENTRY(sge_iq) link; 386 387 bus_dma_tag_t desc_tag; 388 bus_dmamap_t desc_map; 389 bus_addr_t ba; /* bus address of descriptor ring */ 390 }; 391 392 enum { 393 EQ_CTRL = 1, 394 EQ_ETH = 2, 395 EQ_OFLD = 3, 396 397 /* eq flags */ 398 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 399 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 400 EQ_ENABLED = (1 << 3), /* open for business */ 401 }; 402 403 /* Listed in order of preference. Update t4_sysctls too if you change these */ 404 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 405 406 /* 407 * Egress Queue: driver is producer, T4 is consumer. 408 * 409 * Note: A free list is an egress queue (driver produces the buffers and T4 410 * consumes them) but it's special enough to have its own struct (see sge_fl). 411 */ 412 struct sge_eq { 413 unsigned int flags; /* MUST be first */ 414 unsigned int cntxt_id; /* SGE context id for the eq */ 415 struct mtx eq_lock; 416 417 struct tx_desc *desc; /* KVA of descriptor ring */ 418 uint16_t doorbells; 419 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 420 u_int udb_qid; /* relative qid within the doorbell page */ 421 uint16_t sidx; /* index of the entry with the status page */ 422 uint16_t cidx; /* consumer idx (desc idx) */ 423 uint16_t pidx; /* producer idx (desc idx) */ 424 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 425 uint16_t dbidx; /* pidx of the most recent doorbell */ 426 uint16_t iqid; /* iq that gets egr_update for the eq */ 427 uint8_t tx_chan; /* tx channel used by the eq */ 428 volatile u_int equiq; /* EQUIQ outstanding */ 429 430 bus_dma_tag_t desc_tag; 431 bus_dmamap_t desc_map; 432 bus_addr_t ba; /* bus address of descriptor ring */ 433 char lockname[16]; 434 }; 435 436 struct sw_zone_info { 437 uma_zone_t zone; /* zone that this cluster comes from */ 438 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 439 int type; /* EXT_xxx type of the cluster */ 440 int8_t head_hwidx; 441 int8_t tail_hwidx; 442 }; 443 444 struct hw_buf_info { 445 int8_t zidx; /* backpointer to zone; -ve means unused */ 446 int8_t next; /* next hwidx for this zone; -1 means no more */ 447 int size; 448 }; 449 450 enum { 451 NUM_MEMWIN = 3, 452 453 MEMWIN0_APERTURE = 2048, 454 MEMWIN0_BASE = 0x1b800, 455 456 MEMWIN1_APERTURE = 32768, 457 MEMWIN1_BASE = 0x28000, 458 459 MEMWIN2_APERTURE_T4 = 65536, 460 MEMWIN2_BASE_T4 = 0x30000, 461 462 MEMWIN2_APERTURE_T5 = 128 * 1024, 463 MEMWIN2_BASE_T5 = 0x60000, 464 }; 465 466 struct memwin { 467 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 468 uint32_t mw_base; /* constant after setup_memwin */ 469 uint32_t mw_aperture; /* ditto */ 470 uint32_t mw_curpos; /* protected by mw_lock */ 471 }; 472 473 enum { 474 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 475 FL_DOOMED = (1 << 1), /* about to be destroyed */ 476 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 477 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 478 }; 479 480 #define FL_RUNNING_LOW(fl) \ 481 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 482 #define FL_NOT_RUNNING_LOW(fl) \ 483 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 484 485 struct sge_fl { 486 struct mtx fl_lock; 487 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 488 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 489 struct cluster_layout cll_def; /* default refill zone, layout */ 490 uint16_t lowat; /* # of buffers <= this means fl needs help */ 491 int flags; 492 uint16_t buf_boundary; 493 494 /* The 16b idx all deal with hw descriptors */ 495 uint16_t dbidx; /* hw pidx after last doorbell */ 496 uint16_t sidx; /* index of status page */ 497 volatile uint16_t hw_cidx; 498 499 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 500 uint32_t cidx; /* consumer index */ 501 uint32_t pidx; /* producer index */ 502 503 uint32_t dbval; 504 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 505 volatile uint32_t *udb; 506 507 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 508 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 509 uint64_t cl_allocated; /* # of clusters allocated */ 510 uint64_t cl_recycled; /* # of clusters recycled */ 511 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 512 513 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 514 struct mbuf *m0; 515 struct mbuf **pnext; 516 u_int remaining; 517 518 uint16_t qsize; /* # of hw descriptors (status page included) */ 519 uint16_t cntxt_id; /* SGE context id for the freelist */ 520 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 521 bus_dma_tag_t desc_tag; 522 bus_dmamap_t desc_map; 523 char lockname[16]; 524 bus_addr_t ba; /* bus address of descriptor ring */ 525 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 526 }; 527 528 struct mp_ring; 529 530 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 531 struct sge_txq { 532 struct sge_eq eq; /* MUST be first */ 533 534 struct ifnet *ifp; /* the interface this txq belongs to */ 535 struct mp_ring *r; /* tx software ring */ 536 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 537 struct sglist *gl; 538 __be32 cpl_ctrl0; /* for convenience */ 539 int tc_idx; /* traffic class */ 540 541 struct task tx_reclaim_task; 542 /* stats for common events first */ 543 544 uint64_t txcsum; /* # of times hardware assisted with checksum */ 545 uint64_t tso_wrs; /* # of TSO work requests */ 546 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 547 uint64_t imm_wrs; /* # of work requests with immediate data */ 548 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 549 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 550 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 551 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 552 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 553 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 554 555 /* stats for not-that-common events */ 556 } __aligned(CACHE_LINE_SIZE); 557 558 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 559 struct sge_rxq { 560 struct sge_iq iq; /* MUST be first */ 561 struct sge_fl fl; /* MUST follow iq */ 562 563 struct ifnet *ifp; /* the interface this rxq belongs to */ 564 #if defined(INET) || defined(INET6) 565 struct lro_ctrl lro; /* LRO state */ 566 #endif 567 568 /* stats for common events first */ 569 570 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 571 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 572 573 /* stats for not-that-common events */ 574 575 } __aligned(CACHE_LINE_SIZE); 576 577 static inline struct sge_rxq * 578 iq_to_rxq(struct sge_iq *iq) 579 { 580 581 return (__containerof(iq, struct sge_rxq, iq)); 582 } 583 584 585 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 586 struct sge_ofld_rxq { 587 struct sge_iq iq; /* MUST be first */ 588 struct sge_fl fl; /* MUST follow iq */ 589 } __aligned(CACHE_LINE_SIZE); 590 591 static inline struct sge_ofld_rxq * 592 iq_to_ofld_rxq(struct sge_iq *iq) 593 { 594 595 return (__containerof(iq, struct sge_ofld_rxq, iq)); 596 } 597 598 struct wrqe { 599 STAILQ_ENTRY(wrqe) link; 600 struct sge_wrq *wrq; 601 int wr_len; 602 char wr[] __aligned(16); 603 }; 604 605 struct wrq_cookie { 606 TAILQ_ENTRY(wrq_cookie) link; 607 int ndesc; 608 int pidx; 609 }; 610 611 /* 612 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 613 * and offload tx queues are of this type. 614 */ 615 struct sge_wrq { 616 struct sge_eq eq; /* MUST be first */ 617 618 struct adapter *adapter; 619 struct task wrq_tx_task; 620 621 /* Tx desc reserved but WR not "committed" yet. */ 622 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 623 624 /* List of WRs ready to go out as soon as descriptors are available. */ 625 STAILQ_HEAD(, wrqe) wr_list; 626 u_int nwr_pending; 627 u_int ndesc_needed; 628 629 /* stats for common events first */ 630 631 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 632 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 633 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 634 635 /* stats for not-that-common events */ 636 637 /* 638 * Scratch space for work requests that wrap around after reaching the 639 * status page, and some information about the last WR that used it. 640 */ 641 uint16_t ss_pidx; 642 uint16_t ss_len; 643 uint8_t ss[SGE_MAX_WR_LEN]; 644 645 } __aligned(CACHE_LINE_SIZE); 646 647 648 struct sge_nm_rxq { 649 struct vi_info *vi; 650 651 struct iq_desc *iq_desc; 652 uint16_t iq_abs_id; 653 uint16_t iq_cntxt_id; 654 uint16_t iq_cidx; 655 uint16_t iq_sidx; 656 uint8_t iq_gen; 657 658 __be64 *fl_desc; 659 uint16_t fl_cntxt_id; 660 uint32_t fl_cidx; 661 uint32_t fl_pidx; 662 uint32_t fl_sidx; 663 uint32_t fl_db_val; 664 u_int fl_hwidx:4; 665 666 u_int nid; /* netmap ring # for this queue */ 667 668 /* infrequently used items after this */ 669 670 bus_dma_tag_t iq_desc_tag; 671 bus_dmamap_t iq_desc_map; 672 bus_addr_t iq_ba; 673 int intr_idx; 674 675 bus_dma_tag_t fl_desc_tag; 676 bus_dmamap_t fl_desc_map; 677 bus_addr_t fl_ba; 678 } __aligned(CACHE_LINE_SIZE); 679 680 struct sge_nm_txq { 681 struct tx_desc *desc; 682 uint16_t cidx; 683 uint16_t pidx; 684 uint16_t sidx; 685 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 686 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 687 uint16_t dbidx; /* pidx of the most recent doorbell */ 688 uint16_t doorbells; 689 volatile uint32_t *udb; 690 u_int udb_qid; 691 u_int cntxt_id; 692 __be32 cpl_ctrl0; /* for convenience */ 693 u_int nid; /* netmap ring # for this queue */ 694 695 /* infrequently used items after this */ 696 697 bus_dma_tag_t desc_tag; 698 bus_dmamap_t desc_map; 699 bus_addr_t ba; 700 int iqidx; 701 } __aligned(CACHE_LINE_SIZE); 702 703 struct sge { 704 int nrxq; /* total # of Ethernet rx queues */ 705 int ntxq; /* total # of Ethernet tx tx queues */ 706 int nofldrxq; /* total # of TOE rx queues */ 707 int nofldtxq; /* total # of TOE tx queues */ 708 int nnmrxq; /* total # of netmap rx queues */ 709 int nnmtxq; /* total # of netmap tx queues */ 710 int niq; /* total # of ingress queues */ 711 int neq; /* total # of egress queues */ 712 713 struct sge_iq fwq; /* Firmware event queue */ 714 struct sge_wrq mgmtq; /* Management queue (control queue) */ 715 struct sge_wrq *ctrlq; /* Control queues */ 716 struct sge_txq *txq; /* NIC tx queues */ 717 struct sge_rxq *rxq; /* NIC rx queues */ 718 struct sge_wrq *ofld_txq; /* TOE tx queues */ 719 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 720 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 721 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 722 723 uint16_t iq_start; 724 int eq_start; 725 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 726 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 727 728 int8_t safe_hwidx1; /* may not have room for metadata */ 729 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 730 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 731 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 732 }; 733 734 struct rss_header; 735 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 736 struct mbuf *); 737 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 738 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 739 740 struct adapter { 741 SLIST_ENTRY(adapter) link; 742 device_t dev; 743 struct cdev *cdev; 744 745 /* PCIe register resources */ 746 int regs_rid; 747 struct resource *regs_res; 748 int msix_rid; 749 struct resource *msix_res; 750 bus_space_handle_t bh; 751 bus_space_tag_t bt; 752 bus_size_t mmio_len; 753 int udbs_rid; 754 struct resource *udbs_res; 755 volatile uint8_t *udbs_base; 756 757 unsigned int pf; 758 unsigned int mbox; 759 unsigned int vpd_busy; 760 unsigned int vpd_flag; 761 762 /* Interrupt information */ 763 int intr_type; 764 int intr_count; 765 struct irq { 766 struct resource *res; 767 int rid; 768 void *tag; 769 } *irq; 770 771 bus_dma_tag_t dmat; /* Parent DMA tag */ 772 773 struct sge sge; 774 int lro_timeout; 775 776 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 777 struct port_info *port[MAX_NPORTS]; 778 uint8_t chan_map[MAX_NCHAN]; 779 780 void *tom_softc; /* (struct tom_data *) */ 781 struct tom_tunables tt; 782 void *iwarp_softc; /* (struct c4iw_dev *) */ 783 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 784 struct l2t_data *l2t; /* L2 table */ 785 struct tid_info tids; 786 787 uint16_t doorbells; 788 int offload_map; /* ports with IFCAP_TOE enabled */ 789 int active_ulds; /* ULDs activated on this adapter */ 790 int flags; 791 int debug_flags; 792 793 char ifp_lockname[16]; 794 struct mtx ifp_lock; 795 struct ifnet *ifp; /* tracer ifp */ 796 struct ifmedia media; 797 int traceq; /* iq used by all tracers, -1 if none */ 798 int tracer_valid; /* bitmap of valid tracers */ 799 int tracer_enabled; /* bitmap of enabled tracers */ 800 801 char fw_version[16]; 802 char tp_version[16]; 803 char exprom_version[16]; 804 char cfg_file[32]; 805 u_int cfcsum; 806 struct adapter_params params; 807 const struct chip_params *chip_params; 808 struct t4_virt_res vres; 809 810 uint16_t nbmcaps; 811 uint16_t linkcaps; 812 uint16_t switchcaps; 813 uint16_t niccaps; 814 uint16_t toecaps; 815 uint16_t rdmacaps; 816 uint16_t tlscaps; 817 uint16_t iscsicaps; 818 uint16_t fcoecaps; 819 820 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 821 822 struct mtx sc_lock; 823 char lockname[16]; 824 825 /* Starving free lists */ 826 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 827 TAILQ_HEAD(, sge_fl) sfl; 828 struct callout sfl_callout; 829 830 struct mtx reg_lock; /* for indirect register access */ 831 832 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 833 834 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 835 fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */ 836 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 837 838 const char *last_op; 839 const void *last_op_thr; 840 int last_op_flags; 841 842 int sc_do_rxcopy; 843 }; 844 845 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 846 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 847 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 848 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 849 850 #define ASSERT_SYNCHRONIZED_OP(sc) \ 851 KASSERT(IS_BUSY(sc) && \ 852 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 853 ("%s: operation not synchronized.", __func__)) 854 855 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 856 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 857 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 858 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 859 860 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 861 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 862 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 863 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 864 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 865 866 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 867 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 868 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 869 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 870 871 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 872 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 873 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 874 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 875 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 876 877 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 878 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 879 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 880 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 881 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 882 883 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 884 do { \ 885 if (sc->debug_flags & DF_DUMP_MBOX) { \ 886 log(LOG_NOTICE, \ 887 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 888 "%016llx %016llx %016llx %016llx\n", \ 889 device_get_nameunit(sc->dev), mbox, \ 890 (unsigned long long)t4_read_reg64(sc, data_reg), \ 891 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 892 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 893 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 894 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 895 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 896 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 897 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 898 } \ 899 } while (0) 900 901 #define for_each_txq(vi, iter, q) \ 902 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 903 iter < vi->ntxq; ++iter, ++q) 904 #define for_each_rxq(vi, iter, q) \ 905 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 906 iter < vi->nrxq; ++iter, ++q) 907 #define for_each_ofld_txq(vi, iter, q) \ 908 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 909 iter < vi->nofldtxq; ++iter, ++q) 910 #define for_each_ofld_rxq(vi, iter, q) \ 911 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 912 iter < vi->nofldrxq; ++iter, ++q) 913 #define for_each_nm_txq(vi, iter, q) \ 914 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_txq], iter = 0; \ 915 iter < vi->ntxq; ++iter, ++q) 916 #define for_each_nm_rxq(vi, iter, q) \ 917 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_rxq], iter = 0; \ 918 iter < vi->nrxq; ++iter, ++q) 919 #define for_each_vi(_pi, _iter, _vi) \ 920 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 921 ++(_iter), ++(_vi)) 922 923 #define IDXINCR(idx, incr, wrap) do { \ 924 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 925 } while (0) 926 #define IDXDIFF(head, tail, wrap) \ 927 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 928 929 /* One for errors, one for firmware events */ 930 #define T4_EXTRA_INTR 2 931 932 static inline uint32_t 933 t4_read_reg(struct adapter *sc, uint32_t reg) 934 { 935 936 return bus_space_read_4(sc->bt, sc->bh, reg); 937 } 938 939 static inline void 940 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 941 { 942 943 bus_space_write_4(sc->bt, sc->bh, reg, val); 944 } 945 946 static inline uint64_t 947 t4_read_reg64(struct adapter *sc, uint32_t reg) 948 { 949 950 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 951 } 952 953 static inline void 954 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 955 { 956 957 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 958 } 959 960 static inline void 961 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 962 { 963 964 *val = pci_read_config(sc->dev, reg, 1); 965 } 966 967 static inline void 968 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 969 { 970 971 pci_write_config(sc->dev, reg, val, 1); 972 } 973 974 static inline void 975 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 976 { 977 978 *val = pci_read_config(sc->dev, reg, 2); 979 } 980 981 static inline void 982 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 983 { 984 985 pci_write_config(sc->dev, reg, val, 2); 986 } 987 988 static inline void 989 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 990 { 991 992 *val = pci_read_config(sc->dev, reg, 4); 993 } 994 995 static inline void 996 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 997 { 998 999 pci_write_config(sc->dev, reg, val, 4); 1000 } 1001 1002 static inline struct port_info * 1003 adap2pinfo(struct adapter *sc, int idx) 1004 { 1005 1006 return (sc->port[idx]); 1007 } 1008 1009 static inline void 1010 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1011 { 1012 1013 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1014 } 1015 1016 static inline bool 1017 is_10G_port(const struct port_info *pi) 1018 { 1019 1020 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1021 } 1022 1023 static inline bool 1024 is_40G_port(const struct port_info *pi) 1025 { 1026 1027 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1028 } 1029 1030 static inline int 1031 port_top_speed(const struct port_info *pi) 1032 { 1033 1034 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1035 return (100); 1036 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1037 return (40); 1038 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1039 return (10); 1040 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1041 return (1); 1042 1043 return (0); 1044 } 1045 1046 static inline int 1047 tx_resume_threshold(struct sge_eq *eq) 1048 { 1049 1050 /* not quite the same as qsize / 4, but this will do. */ 1051 return (eq->sidx / 4); 1052 } 1053 1054 static inline int 1055 t4_use_ldst(struct adapter *sc) 1056 { 1057 1058 #ifdef notyet 1059 return (sc->flags & FW_OK || !sc->use_bd); 1060 #else 1061 return (0); 1062 #endif 1063 } 1064 1065 /* t4_main.c */ 1066 int t4_os_find_pci_capability(struct adapter *, int); 1067 int t4_os_pci_save_state(struct adapter *); 1068 int t4_os_pci_restore_state(struct adapter *); 1069 void t4_os_portmod_changed(const struct adapter *, int); 1070 void t4_os_link_changed(struct adapter *, int, int, int); 1071 void t4_iterate(void (*)(struct adapter *, void *), void *); 1072 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 1073 int t4_register_an_handler(struct adapter *, an_handler_t); 1074 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 1075 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1076 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1077 void doom_vi(struct adapter *, struct vi_info *); 1078 void end_synchronized_op(struct adapter *, int); 1079 int update_mac_settings(struct ifnet *, int); 1080 int adapter_full_init(struct adapter *); 1081 int adapter_full_uninit(struct adapter *); 1082 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1083 int vi_full_init(struct vi_info *); 1084 int vi_full_uninit(struct vi_info *); 1085 void vi_sysctls(struct vi_info *); 1086 void vi_tick(void *); 1087 1088 #ifdef DEV_NETMAP 1089 /* t4_netmap.c */ 1090 int create_netmap_ifnet(struct port_info *); 1091 int destroy_netmap_ifnet(struct port_info *); 1092 void t4_nm_intr(void *); 1093 #endif 1094 1095 /* t4_sge.c */ 1096 void t4_sge_modload(void); 1097 void t4_sge_modunload(void); 1098 uint64_t t4_sge_extfree_refs(void); 1099 void t4_init_sge_cpl_handlers(struct adapter *); 1100 void t4_tweak_chip_settings(struct adapter *); 1101 int t4_read_chip_settings(struct adapter *); 1102 int t4_create_dma_tag(struct adapter *); 1103 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1104 struct sysctl_oid_list *); 1105 int t4_destroy_dma_tag(struct adapter *); 1106 int t4_setup_adapter_queues(struct adapter *); 1107 int t4_teardown_adapter_queues(struct adapter *); 1108 int t4_setup_vi_queues(struct vi_info *); 1109 int t4_teardown_vi_queues(struct vi_info *); 1110 void t4_intr_all(void *); 1111 void t4_intr(void *); 1112 void t4_intr_err(void *); 1113 void t4_intr_evt(void *); 1114 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1115 void t4_update_fl_bufsize(struct ifnet *); 1116 int parse_pkt(struct mbuf **); 1117 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1118 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1119 int tnl_cong(struct port_info *, int); 1120 1121 /* t4_tracer.c */ 1122 struct t4_tracer; 1123 void t4_tracer_modload(void); 1124 void t4_tracer_modunload(void); 1125 void t4_tracer_port_detach(struct adapter *); 1126 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1127 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1128 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1129 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1130 1131 static inline struct wrqe * 1132 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1133 { 1134 int len = offsetof(struct wrqe, wr) + wr_len; 1135 struct wrqe *wr; 1136 1137 wr = malloc(len, M_CXGBE, M_NOWAIT); 1138 if (__predict_false(wr == NULL)) 1139 return (NULL); 1140 wr->wr_len = wr_len; 1141 wr->wrq = wrq; 1142 return (wr); 1143 } 1144 1145 static inline void * 1146 wrtod(struct wrqe *wr) 1147 { 1148 return (&wr->wr[0]); 1149 } 1150 1151 static inline void 1152 free_wrqe(struct wrqe *wr) 1153 { 1154 free(wr, M_CXGBE); 1155 } 1156 1157 static inline void 1158 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1159 { 1160 struct sge_wrq *wrq = wr->wrq; 1161 1162 TXQ_LOCK(wrq); 1163 t4_wrq_tx_locked(sc, wrq, wr); 1164 TXQ_UNLOCK(wrq); 1165 } 1166 1167 #endif 1168