1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/tcp_lro.h> 48 49 #include "offload.h" 50 #include "firmware/t4fw_interface.h" 51 52 #define T4_CFGNAME "t4fw_cfg" 53 #define T4_FWNAME "t4fw" 54 55 MALLOC_DECLARE(M_CXGBE); 56 #define CXGBE_UNIMPLEMENTED(s) \ 57 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 58 59 #if defined(__i386__) || defined(__amd64__) 60 static __inline void 61 prefetch(void *x) 62 { 63 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 64 } 65 #else 66 #define prefetch(x) 67 #endif 68 69 #ifdef __amd64__ 70 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 71 static __inline uint64_t 72 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 73 bus_size_t offset) 74 { 75 KASSERT(tag == X86_BUS_SPACE_MEM, 76 ("%s: can only handle mem space", __func__)); 77 78 return (*(volatile uint64_t *)(handle + offset)); 79 } 80 81 static __inline void 82 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 83 bus_size_t offset, uint64_t value) 84 { 85 KASSERT(tag == X86_BUS_SPACE_MEM, 86 ("%s: can only handle mem space", __func__)); 87 88 *(volatile uint64_t *)(bsh + offset) = value; 89 } 90 #else 91 static __inline uint64_t 92 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 93 bus_size_t offset) 94 { 95 return (uint64_t)bus_space_read_4(tag, handle, offset) + 96 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 97 } 98 99 static __inline void 100 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 101 bus_size_t offset, uint64_t value) 102 { 103 bus_space_write_4(tag, bsh, offset, value); 104 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 105 } 106 #endif 107 108 struct adapter; 109 typedef struct adapter adapter_t; 110 111 enum { 112 FW_IQ_QSIZE = 256, 113 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 114 115 RX_IQ_QSIZE = 1024, 116 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 117 118 EQ_ESIZE = 64, /* All egress queues use this entry size */ 119 120 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 121 #if MJUMPAGESIZE != MCLBYTES 122 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 123 #else 124 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 125 #endif 126 127 CTRL_EQ_QSIZE = 128, 128 129 TX_EQ_QSIZE = 1024, 130 TX_SGL_SEGS = 36, 131 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 132 }; 133 134 enum { 135 /* adapter intr_type */ 136 INTR_INTX = (1 << 0), 137 INTR_MSI = (1 << 1), 138 INTR_MSIX = (1 << 2) 139 }; 140 141 enum { 142 /* adapter flags */ 143 FULL_INIT_DONE = (1 << 0), 144 FW_OK = (1 << 1), 145 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 146 MASTER_PF = (1 << 3), 147 ADAP_SYSCTL_CTX = (1 << 4), 148 149 CXGBE_BUSY = (1 << 9), 150 151 /* port flags */ 152 DOOMED = (1 << 0), 153 PORT_INIT_DONE = (1 << 1), 154 PORT_SYSCTL_CTX = (1 << 2), 155 }; 156 157 #define IS_DOOMED(pi) (pi->flags & DOOMED) 158 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 159 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 160 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 161 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 162 163 struct port_info { 164 device_t dev; 165 struct adapter *adapter; 166 167 struct ifnet *ifp; 168 struct ifmedia media; 169 170 struct mtx pi_lock; 171 char lockname[16]; 172 unsigned long flags; 173 int if_flags; 174 175 uint16_t viid; 176 int16_t xact_addr_filt;/* index of exact MAC address filter */ 177 uint16_t rss_size; /* size of VI's RSS table slice */ 178 uint8_t lport; /* associated offload logical port */ 179 int8_t mdio_addr; 180 uint8_t port_type; 181 uint8_t mod_type; 182 uint8_t port_id; 183 uint8_t tx_chan; 184 185 /* These need to be int as they are used in sysctl */ 186 int ntxq; /* # of tx queues */ 187 int first_txq; /* index of first tx queue */ 188 int nrxq; /* # of rx queues */ 189 int first_rxq; /* index of first rx queue */ 190 #ifndef TCP_OFFLOAD_DISABLE 191 int nofldtxq; /* # of offload tx queues */ 192 int first_ofld_txq; /* index of first offload tx queue */ 193 int nofldrxq; /* # of offload rx queues */ 194 int first_ofld_rxq; /* index of first offload rx queue */ 195 #endif 196 int tmr_idx; 197 int pktc_idx; 198 int qsize_rxq; 199 int qsize_txq; 200 201 struct link_config link_cfg; 202 struct port_stats stats; 203 204 struct callout tick; 205 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 206 207 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 208 }; 209 210 struct fl_sdesc { 211 struct mbuf *m; 212 bus_dmamap_t map; 213 caddr_t cl; 214 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 215 #ifdef INVARIANTS 216 __be64 ba_tag; 217 #endif 218 }; 219 220 struct tx_desc { 221 __be64 flit[8]; 222 }; 223 224 struct tx_map { 225 struct mbuf *m; 226 bus_dmamap_t map; 227 }; 228 229 /* DMA maps used for tx */ 230 struct tx_maps { 231 struct tx_map *maps; 232 uint32_t map_total; /* # of DMA maps */ 233 uint32_t map_pidx; /* next map to be used */ 234 uint32_t map_cidx; /* reclaimed up to this index */ 235 uint32_t map_avail; /* # of available maps */ 236 }; 237 238 struct tx_sdesc { 239 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 240 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 241 }; 242 243 enum { 244 /* iq flags */ 245 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 246 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 247 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 248 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 249 250 /* iq state */ 251 IQS_DISABLED = 0, 252 IQS_BUSY = 1, 253 IQS_IDLE = 2, 254 }; 255 256 /* 257 * Ingress Queue: T4 is producer, driver is consumer. 258 */ 259 struct sge_iq { 260 bus_dma_tag_t desc_tag; 261 bus_dmamap_t desc_map; 262 bus_addr_t ba; /* bus address of descriptor ring */ 263 char lockname[16]; 264 uint32_t flags; 265 uint16_t abs_id; /* absolute SGE id for the iq */ 266 int8_t intr_pktc_idx; /* packet count threshold index */ 267 int8_t pad0; 268 __be64 *desc; /* KVA of descriptor ring */ 269 270 volatile int state; 271 struct adapter *adapter; 272 const __be64 *cdesc; /* current descriptor */ 273 uint8_t gen; /* generation bit */ 274 uint8_t intr_params; /* interrupt holdoff parameters */ 275 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 276 uint8_t esize; /* size (bytes) of each entry in the queue */ 277 uint16_t qsize; /* size (# of entries) of the queue */ 278 uint16_t cidx; /* consumer index */ 279 uint16_t cntxt_id; /* SGE context id for the iq */ 280 281 STAILQ_ENTRY(sge_iq) link; 282 }; 283 284 enum { 285 EQ_CTRL = 1, 286 EQ_ETH = 2, 287 #ifndef TCP_OFFLOAD_DISABLE 288 EQ_OFLD = 3, 289 #endif 290 291 /* eq flags */ 292 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 293 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 294 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 295 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 296 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 297 }; 298 299 /* 300 * Egress Queue: driver is producer, T4 is consumer. 301 * 302 * Note: A free list is an egress queue (driver produces the buffers and T4 303 * consumes them) but it's special enough to have its own struct (see sge_fl). 304 */ 305 struct sge_eq { 306 unsigned int flags; /* MUST be first */ 307 unsigned int cntxt_id; /* SGE context id for the eq */ 308 bus_dma_tag_t desc_tag; 309 bus_dmamap_t desc_map; 310 char lockname[16]; 311 struct mtx eq_lock; 312 313 struct tx_desc *desc; /* KVA of descriptor ring */ 314 bus_addr_t ba; /* bus address of descriptor ring */ 315 struct sge_qstat *spg; /* status page, for convenience */ 316 uint16_t cap; /* max # of desc, for convenience */ 317 uint16_t avail; /* available descriptors, for convenience */ 318 uint16_t qsize; /* size (# of entries) of the queue */ 319 uint16_t cidx; /* consumer idx (desc idx) */ 320 uint16_t pidx; /* producer idx (desc idx) */ 321 uint16_t pending; /* # of descriptors used since last doorbell */ 322 uint16_t iqid; /* iq that gets egr_update for the eq */ 323 uint8_t tx_chan; /* tx channel used by the eq */ 324 struct task tx_task; 325 struct callout tx_callout; 326 327 /* stats */ 328 329 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 330 uint32_t unstalled; /* recovered from stall */ 331 }; 332 333 enum { 334 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 335 FL_DOOMED = (1 << 1), /* about to be destroyed */ 336 }; 337 338 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 339 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 340 341 struct sge_fl { 342 bus_dma_tag_t desc_tag; 343 bus_dmamap_t desc_map; 344 bus_dma_tag_t tag[FL_BUF_SIZES]; 345 uint8_t tag_idx; 346 struct mtx fl_lock; 347 char lockname[16]; 348 int flags; 349 350 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 351 bus_addr_t ba; /* bus address of descriptor ring */ 352 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 353 uint32_t cap; /* max # of buffers, for convenience */ 354 uint16_t qsize; /* size (# of entries) of the queue */ 355 uint16_t cntxt_id; /* SGE context id for the freelist */ 356 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 357 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 358 uint32_t needed; /* # of buffers needed to fill up fl. */ 359 uint32_t lowat; /* # of buffers <= this means fl needs help */ 360 uint32_t pending; /* # of bufs allocated since last doorbell */ 361 unsigned int dmamap_failed; 362 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 363 }; 364 365 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 366 struct sge_txq { 367 struct sge_eq eq; /* MUST be first */ 368 369 struct ifnet *ifp; /* the interface this txq belongs to */ 370 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 371 struct buf_ring *br; /* tx buffer ring */ 372 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 373 struct mbuf *m; /* held up due to temporary resource shortage */ 374 375 struct tx_maps txmaps; 376 377 /* stats for common events first */ 378 379 uint64_t txcsum; /* # of times hardware assisted with checksum */ 380 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 381 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 382 uint64_t imm_wrs; /* # of work requests with immediate data */ 383 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 384 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 385 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 386 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 387 388 /* stats for not-that-common events */ 389 390 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 391 uint32_t no_desc; /* out of hardware descriptors */ 392 } __aligned(CACHE_LINE_SIZE); 393 394 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 395 struct sge_rxq { 396 struct sge_iq iq; /* MUST be first */ 397 struct sge_fl fl; /* MUST follow iq */ 398 399 struct ifnet *ifp; /* the interface this rxq belongs to */ 400 #ifdef INET 401 struct lro_ctrl lro; /* LRO state */ 402 #endif 403 404 /* stats for common events first */ 405 406 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 407 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 408 409 /* stats for not-that-common events */ 410 411 } __aligned(CACHE_LINE_SIZE); 412 413 #ifndef TCP_OFFLOAD_DISABLE 414 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 415 struct sge_ofld_rxq { 416 struct sge_iq iq; /* MUST be first */ 417 struct sge_fl fl; /* MUST follow iq */ 418 } __aligned(CACHE_LINE_SIZE); 419 #endif 420 421 /* 422 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 423 * and offload tx queues are of this type. 424 */ 425 struct sge_wrq { 426 struct sge_eq eq; /* MUST be first */ 427 428 struct adapter *adapter; 429 struct mbuf *head; /* held up due to lack of descriptors */ 430 struct mbuf *tail; /* valid only if head is valid */ 431 432 /* stats for common events first */ 433 434 uint64_t tx_wrs; /* # of tx work requests */ 435 436 /* stats for not-that-common events */ 437 438 uint32_t no_desc; /* out of hardware descriptors */ 439 } __aligned(CACHE_LINE_SIZE); 440 441 struct sge { 442 int timer_val[SGE_NTIMERS]; 443 int counter_val[SGE_NCOUNTERS]; 444 int fl_starve_threshold; 445 446 int nrxq; /* total # of Ethernet rx queues */ 447 int ntxq; /* total # of Ethernet tx tx queues */ 448 #ifndef TCP_OFFLOAD_DISABLE 449 int nofldrxq; /* total # of TOE rx queues */ 450 int nofldtxq; /* total # of TOE tx queues */ 451 #endif 452 int niq; /* total # of ingress queues */ 453 int neq; /* total # of egress queues */ 454 455 struct sge_iq fwq; /* Firmware event queue */ 456 struct sge_wrq mgmtq; /* Management queue (control queue) */ 457 struct sge_wrq *ctrlq; /* Control queues */ 458 struct sge_txq *txq; /* NIC tx queues */ 459 struct sge_rxq *rxq; /* NIC rx queues */ 460 #ifndef TCP_OFFLOAD_DISABLE 461 struct sge_wrq *ofld_txq; /* TOE tx queues */ 462 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 463 #endif 464 465 uint16_t iq_start; 466 int eq_start; 467 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 468 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 469 }; 470 471 struct rss_header; 472 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 473 struct mbuf *); 474 475 struct adapter { 476 SLIST_ENTRY(adapter) link; 477 device_t dev; 478 struct cdev *cdev; 479 480 /* PCIe register resources */ 481 int regs_rid; 482 struct resource *regs_res; 483 int msix_rid; 484 struct resource *msix_res; 485 bus_space_handle_t bh; 486 bus_space_tag_t bt; 487 bus_size_t mmio_len; 488 489 unsigned int pf; 490 unsigned int mbox; 491 492 /* Interrupt information */ 493 int intr_type; 494 int intr_count; 495 struct irq { 496 struct resource *res; 497 int rid; 498 void *tag; 499 } *irq; 500 501 bus_dma_tag_t dmat; /* Parent DMA tag */ 502 503 struct sge sge; 504 505 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 506 struct port_info *port[MAX_NPORTS]; 507 uint8_t chan_map[NCHAN]; 508 uint32_t filter_mode; 509 510 #ifndef TCP_OFFLOAD_DISABLE 511 struct uld_softc tom; 512 struct tom_tunables tt; 513 #endif 514 struct l2t_data *l2t; /* L2 table */ 515 struct tid_info tids; 516 517 int open_device_map; 518 #ifndef TCP_OFFLOAD_DISABLE 519 int offload_map; 520 #endif 521 int flags; 522 523 char fw_version[32]; 524 unsigned int cfcsum; 525 struct adapter_params params; 526 struct t4_virt_res vres; 527 528 uint16_t linkcaps; 529 uint16_t niccaps; 530 uint16_t toecaps; 531 uint16_t rdmacaps; 532 uint16_t iscsicaps; 533 uint16_t fcoecaps; 534 535 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 536 537 struct mtx sc_lock; 538 char lockname[16]; 539 540 /* Starving free lists */ 541 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 542 TAILQ_HEAD(, sge_fl) sfl; 543 struct callout sfl_callout; 544 545 cpl_handler_t cpl_handler[256] __aligned(CACHE_LINE_SIZE); 546 }; 547 548 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 549 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 550 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 551 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 552 553 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 554 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 555 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 556 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 557 558 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 559 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 560 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 561 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 562 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 563 564 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 565 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 566 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 567 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 568 569 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 570 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 571 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 572 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 573 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 574 575 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 576 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 577 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 578 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 579 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 580 581 #define for_each_txq(pi, iter, txq) \ 582 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 583 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 584 #define for_each_rxq(pi, iter, rxq) \ 585 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 586 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 587 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 588 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 589 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 590 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 591 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 592 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 593 594 /* One for errors, one for firmware events */ 595 #define T4_EXTRA_INTR 2 596 597 static inline uint32_t 598 t4_read_reg(struct adapter *sc, uint32_t reg) 599 { 600 return bus_space_read_4(sc->bt, sc->bh, reg); 601 } 602 603 static inline void 604 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 605 { 606 bus_space_write_4(sc->bt, sc->bh, reg, val); 607 } 608 609 static inline uint64_t 610 t4_read_reg64(struct adapter *sc, uint32_t reg) 611 { 612 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 613 } 614 615 static inline void 616 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 617 { 618 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 619 } 620 621 static inline void 622 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 623 { 624 *val = pci_read_config(sc->dev, reg, 1); 625 } 626 627 static inline void 628 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 629 { 630 pci_write_config(sc->dev, reg, val, 1); 631 } 632 633 static inline void 634 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 635 { 636 *val = pci_read_config(sc->dev, reg, 2); 637 } 638 639 static inline void 640 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 641 { 642 pci_write_config(sc->dev, reg, val, 2); 643 } 644 645 static inline void 646 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 647 { 648 *val = pci_read_config(sc->dev, reg, 4); 649 } 650 651 static inline void 652 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 653 { 654 pci_write_config(sc->dev, reg, val, 4); 655 } 656 657 static inline struct port_info * 658 adap2pinfo(struct adapter *sc, int idx) 659 { 660 return (sc->port[idx]); 661 } 662 663 static inline void 664 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 665 { 666 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 667 } 668 669 static inline bool is_10G_port(const struct port_info *pi) 670 { 671 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 672 } 673 674 static inline int tx_resume_threshold(struct sge_eq *eq) 675 { 676 return (eq->qsize / 4); 677 } 678 679 /* t4_main.c */ 680 void t4_tx_task(void *, int); 681 void t4_tx_callout(void *); 682 int t4_os_find_pci_capability(struct adapter *, int); 683 int t4_os_pci_save_state(struct adapter *); 684 int t4_os_pci_restore_state(struct adapter *); 685 void t4_os_portmod_changed(const struct adapter *, int); 686 void t4_os_link_changed(struct adapter *, int, int); 687 void t4_iterate(void (*)(struct adapter *, void *), void *); 688 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 689 690 /* t4_sge.c */ 691 void t4_sge_modload(void); 692 int t4_sge_init(struct adapter *); 693 int t4_create_dma_tag(struct adapter *); 694 int t4_destroy_dma_tag(struct adapter *); 695 int t4_setup_adapter_queues(struct adapter *); 696 int t4_teardown_adapter_queues(struct adapter *); 697 int t4_setup_port_queues(struct port_info *); 698 int t4_teardown_port_queues(struct port_info *); 699 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 700 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 701 void t4_intr_all(void *); 702 void t4_intr(void *); 703 void t4_intr_err(void *); 704 void t4_intr_evt(void *); 705 int t4_mgmt_tx(struct adapter *, struct mbuf *); 706 int t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct mbuf *); 707 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 708 void t4_update_fl_bufsize(struct ifnet *); 709 int can_resume_tx(struct sge_eq *); 710 711 static inline int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, struct mbuf *m) 712 { 713 int rc; 714 715 TXQ_LOCK(wrq); 716 rc = t4_wrq_tx_locked(sc, wrq, m); 717 TXQ_UNLOCK(wrq); 718 return (rc); 719 } 720 721 722 #endif 723