1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/in.h> 48 #include <netinet/tcp_lro.h> 49 50 #include "offload.h" 51 #include "firmware/t4fw_interface.h" 52 53 #define T4_CFGNAME "t4fw_cfg" 54 #define T4_FWNAME "t4fw" 55 56 MALLOC_DECLARE(M_CXGBE); 57 #define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60 #if defined(__i386__) || defined(__amd64__) 61 static __inline void 62 prefetch(void *x) 63 { 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65 } 66 #else 67 #define prefetch(x) 68 #endif 69 70 #ifndef SYSCTL_ADD_UQUAD 71 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72 #define sysctl_handle_64 sysctl_handle_quad 73 #define CTLTYPE_U64 CTLTYPE_QUAD 74 #endif 75 76 #if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78 #define SBUF_DRAIN 1 79 #endif 80 81 #ifdef __amd64__ 82 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 83 static __inline uint64_t 84 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 85 bus_size_t offset) 86 { 87 KASSERT(tag == X86_BUS_SPACE_MEM, 88 ("%s: can only handle mem space", __func__)); 89 90 return (*(volatile uint64_t *)(handle + offset)); 91 } 92 93 static __inline void 94 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 95 bus_size_t offset, uint64_t value) 96 { 97 KASSERT(tag == X86_BUS_SPACE_MEM, 98 ("%s: can only handle mem space", __func__)); 99 100 *(volatile uint64_t *)(bsh + offset) = value; 101 } 102 #else 103 static __inline uint64_t 104 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 105 bus_size_t offset) 106 { 107 return (uint64_t)bus_space_read_4(tag, handle, offset) + 108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 109 } 110 111 static __inline void 112 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 113 bus_size_t offset, uint64_t value) 114 { 115 bus_space_write_4(tag, bsh, offset, value); 116 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 117 } 118 #endif 119 120 struct adapter; 121 typedef struct adapter adapter_t; 122 123 enum { 124 FW_IQ_QSIZE = 256, 125 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 126 127 RX_IQ_QSIZE = 1024, 128 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 129 130 EQ_ESIZE = 64, /* All egress queues use this entry size */ 131 132 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 133 #if MJUMPAGESIZE != MCLBYTES 134 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 135 #else 136 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 137 #endif 138 139 CTRL_EQ_QSIZE = 128, 140 141 TX_EQ_QSIZE = 1024, 142 TX_SGL_SEGS = 36, 143 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 144 }; 145 146 enum { 147 /* adapter intr_type */ 148 INTR_INTX = (1 << 0), 149 INTR_MSI = (1 << 1), 150 INTR_MSIX = (1 << 2) 151 }; 152 153 enum { 154 /* adapter flags */ 155 FULL_INIT_DONE = (1 << 0), 156 FW_OK = (1 << 1), 157 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 158 MASTER_PF = (1 << 3), 159 ADAP_SYSCTL_CTX = (1 << 4), 160 161 CXGBE_BUSY = (1 << 9), 162 163 /* port flags */ 164 DOOMED = (1 << 0), 165 PORT_INIT_DONE = (1 << 1), 166 PORT_SYSCTL_CTX = (1 << 2), 167 }; 168 169 #define IS_DOOMED(pi) (pi->flags & DOOMED) 170 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) 171 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 172 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) 173 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) 174 175 struct port_info { 176 device_t dev; 177 struct adapter *adapter; 178 179 struct ifnet *ifp; 180 struct ifmedia media; 181 182 struct mtx pi_lock; 183 char lockname[16]; 184 unsigned long flags; 185 int if_flags; 186 187 uint16_t viid; 188 int16_t xact_addr_filt;/* index of exact MAC address filter */ 189 uint16_t rss_size; /* size of VI's RSS table slice */ 190 uint8_t lport; /* associated offload logical port */ 191 int8_t mdio_addr; 192 uint8_t port_type; 193 uint8_t mod_type; 194 uint8_t port_id; 195 uint8_t tx_chan; 196 197 /* These need to be int as they are used in sysctl */ 198 int ntxq; /* # of tx queues */ 199 int first_txq; /* index of first tx queue */ 200 int nrxq; /* # of rx queues */ 201 int first_rxq; /* index of first rx queue */ 202 #ifndef TCP_OFFLOAD_DISABLE 203 int nofldtxq; /* # of offload tx queues */ 204 int first_ofld_txq; /* index of first offload tx queue */ 205 int nofldrxq; /* # of offload rx queues */ 206 int first_ofld_rxq; /* index of first offload rx queue */ 207 #endif 208 int tmr_idx; 209 int pktc_idx; 210 int qsize_rxq; 211 int qsize_txq; 212 213 struct link_config link_cfg; 214 struct port_stats stats; 215 216 struct callout tick; 217 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 218 219 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 220 }; 221 222 struct fl_sdesc { 223 struct mbuf *m; 224 bus_dmamap_t map; 225 caddr_t cl; 226 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 227 #ifdef INVARIANTS 228 __be64 ba_tag; 229 #endif 230 }; 231 232 struct tx_desc { 233 __be64 flit[8]; 234 }; 235 236 struct tx_map { 237 struct mbuf *m; 238 bus_dmamap_t map; 239 }; 240 241 /* DMA maps used for tx */ 242 struct tx_maps { 243 struct tx_map *maps; 244 uint32_t map_total; /* # of DMA maps */ 245 uint32_t map_pidx; /* next map to be used */ 246 uint32_t map_cidx; /* reclaimed up to this index */ 247 uint32_t map_avail; /* # of available maps */ 248 }; 249 250 struct tx_sdesc { 251 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 252 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 253 }; 254 255 enum { 256 /* iq flags */ 257 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 258 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 259 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 260 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 261 262 /* iq state */ 263 IQS_DISABLED = 0, 264 IQS_BUSY = 1, 265 IQS_IDLE = 2, 266 }; 267 268 /* 269 * Ingress Queue: T4 is producer, driver is consumer. 270 */ 271 struct sge_iq { 272 bus_dma_tag_t desc_tag; 273 bus_dmamap_t desc_map; 274 bus_addr_t ba; /* bus address of descriptor ring */ 275 char lockname[16]; 276 uint32_t flags; 277 uint16_t abs_id; /* absolute SGE id for the iq */ 278 int8_t intr_pktc_idx; /* packet count threshold index */ 279 int8_t pad0; 280 __be64 *desc; /* KVA of descriptor ring */ 281 282 volatile int state; 283 struct adapter *adapter; 284 const __be64 *cdesc; /* current descriptor */ 285 uint8_t gen; /* generation bit */ 286 uint8_t intr_params; /* interrupt holdoff parameters */ 287 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 288 uint8_t esize; /* size (bytes) of each entry in the queue */ 289 uint16_t qsize; /* size (# of entries) of the queue */ 290 uint16_t cidx; /* consumer index */ 291 uint16_t cntxt_id; /* SGE context id for the iq */ 292 293 STAILQ_ENTRY(sge_iq) link; 294 }; 295 296 enum { 297 EQ_CTRL = 1, 298 EQ_ETH = 2, 299 #ifndef TCP_OFFLOAD_DISABLE 300 EQ_OFLD = 3, 301 #endif 302 303 /* eq flags */ 304 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 305 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 306 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 307 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 308 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 309 }; 310 311 /* 312 * Egress Queue: driver is producer, T4 is consumer. 313 * 314 * Note: A free list is an egress queue (driver produces the buffers and T4 315 * consumes them) but it's special enough to have its own struct (see sge_fl). 316 */ 317 struct sge_eq { 318 unsigned int flags; /* MUST be first */ 319 unsigned int cntxt_id; /* SGE context id for the eq */ 320 bus_dma_tag_t desc_tag; 321 bus_dmamap_t desc_map; 322 char lockname[16]; 323 struct mtx eq_lock; 324 325 struct tx_desc *desc; /* KVA of descriptor ring */ 326 bus_addr_t ba; /* bus address of descriptor ring */ 327 struct sge_qstat *spg; /* status page, for convenience */ 328 uint16_t cap; /* max # of desc, for convenience */ 329 uint16_t avail; /* available descriptors, for convenience */ 330 uint16_t qsize; /* size (# of entries) of the queue */ 331 uint16_t cidx; /* consumer idx (desc idx) */ 332 uint16_t pidx; /* producer idx (desc idx) */ 333 uint16_t pending; /* # of descriptors used since last doorbell */ 334 uint16_t iqid; /* iq that gets egr_update for the eq */ 335 uint8_t tx_chan; /* tx channel used by the eq */ 336 struct task tx_task; 337 struct callout tx_callout; 338 339 /* stats */ 340 341 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 342 uint32_t unstalled; /* recovered from stall */ 343 }; 344 345 enum { 346 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 347 FL_DOOMED = (1 << 1), /* about to be destroyed */ 348 }; 349 350 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 351 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 352 353 struct sge_fl { 354 bus_dma_tag_t desc_tag; 355 bus_dmamap_t desc_map; 356 bus_dma_tag_t tag[FL_BUF_SIZES]; 357 uint8_t tag_idx; 358 struct mtx fl_lock; 359 char lockname[16]; 360 int flags; 361 362 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 363 bus_addr_t ba; /* bus address of descriptor ring */ 364 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 365 uint32_t cap; /* max # of buffers, for convenience */ 366 uint16_t qsize; /* size (# of entries) of the queue */ 367 uint16_t cntxt_id; /* SGE context id for the freelist */ 368 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 369 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 370 uint32_t needed; /* # of buffers needed to fill up fl. */ 371 uint32_t lowat; /* # of buffers <= this means fl needs help */ 372 uint32_t pending; /* # of bufs allocated since last doorbell */ 373 unsigned int dmamap_failed; 374 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 375 }; 376 377 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 378 struct sge_txq { 379 struct sge_eq eq; /* MUST be first */ 380 381 struct ifnet *ifp; /* the interface this txq belongs to */ 382 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 383 struct buf_ring *br; /* tx buffer ring */ 384 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 385 struct mbuf *m; /* held up due to temporary resource shortage */ 386 387 struct tx_maps txmaps; 388 389 /* stats for common events first */ 390 391 uint64_t txcsum; /* # of times hardware assisted with checksum */ 392 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 393 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 394 uint64_t imm_wrs; /* # of work requests with immediate data */ 395 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 396 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 397 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 398 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 399 400 /* stats for not-that-common events */ 401 402 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 403 uint32_t no_desc; /* out of hardware descriptors */ 404 } __aligned(CACHE_LINE_SIZE); 405 406 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 407 struct sge_rxq { 408 struct sge_iq iq; /* MUST be first */ 409 struct sge_fl fl; /* MUST follow iq */ 410 411 struct ifnet *ifp; /* the interface this rxq belongs to */ 412 #ifdef INET 413 struct lro_ctrl lro; /* LRO state */ 414 #endif 415 416 /* stats for common events first */ 417 418 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 419 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 420 421 /* stats for not-that-common events */ 422 423 } __aligned(CACHE_LINE_SIZE); 424 425 #ifndef TCP_OFFLOAD_DISABLE 426 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 427 struct sge_ofld_rxq { 428 struct sge_iq iq; /* MUST be first */ 429 struct sge_fl fl; /* MUST follow iq */ 430 } __aligned(CACHE_LINE_SIZE); 431 #endif 432 433 /* 434 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 435 * and offload tx queues are of this type. 436 */ 437 struct sge_wrq { 438 struct sge_eq eq; /* MUST be first */ 439 440 struct adapter *adapter; 441 struct mbuf *head; /* held up due to lack of descriptors */ 442 struct mbuf *tail; /* valid only if head is valid */ 443 444 /* stats for common events first */ 445 446 uint64_t tx_wrs; /* # of tx work requests */ 447 448 /* stats for not-that-common events */ 449 450 uint32_t no_desc; /* out of hardware descriptors */ 451 } __aligned(CACHE_LINE_SIZE); 452 453 struct sge { 454 int timer_val[SGE_NTIMERS]; 455 int counter_val[SGE_NCOUNTERS]; 456 int fl_starve_threshold; 457 458 int nrxq; /* total # of Ethernet rx queues */ 459 int ntxq; /* total # of Ethernet tx tx queues */ 460 #ifndef TCP_OFFLOAD_DISABLE 461 int nofldrxq; /* total # of TOE rx queues */ 462 int nofldtxq; /* total # of TOE tx queues */ 463 #endif 464 int niq; /* total # of ingress queues */ 465 int neq; /* total # of egress queues */ 466 467 struct sge_iq fwq; /* Firmware event queue */ 468 struct sge_wrq mgmtq; /* Management queue (control queue) */ 469 struct sge_wrq *ctrlq; /* Control queues */ 470 struct sge_txq *txq; /* NIC tx queues */ 471 struct sge_rxq *rxq; /* NIC rx queues */ 472 #ifndef TCP_OFFLOAD_DISABLE 473 struct sge_wrq *ofld_txq; /* TOE tx queues */ 474 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 475 #endif 476 477 uint16_t iq_start; 478 int eq_start; 479 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 480 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 481 }; 482 483 struct rss_header; 484 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 485 struct mbuf *); 486 487 struct adapter { 488 SLIST_ENTRY(adapter) link; 489 device_t dev; 490 struct cdev *cdev; 491 492 /* PCIe register resources */ 493 int regs_rid; 494 struct resource *regs_res; 495 int msix_rid; 496 struct resource *msix_res; 497 bus_space_handle_t bh; 498 bus_space_tag_t bt; 499 bus_size_t mmio_len; 500 501 unsigned int pf; 502 unsigned int mbox; 503 504 /* Interrupt information */ 505 int intr_type; 506 int intr_count; 507 struct irq { 508 struct resource *res; 509 int rid; 510 void *tag; 511 } *irq; 512 513 bus_dma_tag_t dmat; /* Parent DMA tag */ 514 515 struct sge sge; 516 517 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 518 struct port_info *port[MAX_NPORTS]; 519 uint8_t chan_map[NCHAN]; 520 uint32_t filter_mode; 521 522 #ifndef TCP_OFFLOAD_DISABLE 523 struct uld_softc tom; 524 struct tom_tunables tt; 525 #endif 526 struct l2t_data *l2t; /* L2 table */ 527 struct tid_info tids; 528 529 int open_device_map; 530 #ifndef TCP_OFFLOAD_DISABLE 531 int offload_map; 532 #endif 533 int flags; 534 535 char fw_version[32]; 536 unsigned int cfcsum; 537 struct adapter_params params; 538 struct t4_virt_res vres; 539 540 uint16_t linkcaps; 541 uint16_t niccaps; 542 uint16_t toecaps; 543 uint16_t rdmacaps; 544 uint16_t iscsicaps; 545 uint16_t fcoecaps; 546 547 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 548 549 struct mtx sc_lock; 550 char lockname[16]; 551 552 /* Starving free lists */ 553 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 554 TAILQ_HEAD(, sge_fl) sfl; 555 struct callout sfl_callout; 556 557 cpl_handler_t cpl_handler[256] __aligned(CACHE_LINE_SIZE); 558 }; 559 560 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 561 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 562 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 563 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 564 565 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 566 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 567 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 568 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 569 570 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 571 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 572 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 573 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 574 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 575 576 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 577 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 578 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 579 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 580 581 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 582 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 583 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 584 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 585 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 586 587 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 588 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 589 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 590 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 591 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 592 593 #define for_each_txq(pi, iter, txq) \ 594 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 595 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 596 #define for_each_rxq(pi, iter, rxq) \ 597 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 598 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 599 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 600 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 601 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 602 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 603 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 604 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 605 606 /* One for errors, one for firmware events */ 607 #define T4_EXTRA_INTR 2 608 609 static inline uint32_t 610 t4_read_reg(struct adapter *sc, uint32_t reg) 611 { 612 return bus_space_read_4(sc->bt, sc->bh, reg); 613 } 614 615 static inline void 616 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 617 { 618 bus_space_write_4(sc->bt, sc->bh, reg, val); 619 } 620 621 static inline uint64_t 622 t4_read_reg64(struct adapter *sc, uint32_t reg) 623 { 624 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 625 } 626 627 static inline void 628 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 629 { 630 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 631 } 632 633 static inline void 634 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 635 { 636 *val = pci_read_config(sc->dev, reg, 1); 637 } 638 639 static inline void 640 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 641 { 642 pci_write_config(sc->dev, reg, val, 1); 643 } 644 645 static inline void 646 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 647 { 648 *val = pci_read_config(sc->dev, reg, 2); 649 } 650 651 static inline void 652 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 653 { 654 pci_write_config(sc->dev, reg, val, 2); 655 } 656 657 static inline void 658 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 659 { 660 *val = pci_read_config(sc->dev, reg, 4); 661 } 662 663 static inline void 664 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 665 { 666 pci_write_config(sc->dev, reg, val, 4); 667 } 668 669 static inline struct port_info * 670 adap2pinfo(struct adapter *sc, int idx) 671 { 672 return (sc->port[idx]); 673 } 674 675 static inline void 676 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 677 { 678 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 679 } 680 681 static inline bool is_10G_port(const struct port_info *pi) 682 { 683 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 684 } 685 686 static inline int tx_resume_threshold(struct sge_eq *eq) 687 { 688 return (eq->qsize / 4); 689 } 690 691 /* t4_main.c */ 692 void t4_tx_task(void *, int); 693 void t4_tx_callout(void *); 694 int t4_os_find_pci_capability(struct adapter *, int); 695 int t4_os_pci_save_state(struct adapter *); 696 int t4_os_pci_restore_state(struct adapter *); 697 void t4_os_portmod_changed(const struct adapter *, int); 698 void t4_os_link_changed(struct adapter *, int, int); 699 void t4_iterate(void (*)(struct adapter *, void *), void *); 700 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 701 702 /* t4_sge.c */ 703 void t4_sge_modload(void); 704 int t4_sge_init(struct adapter *); 705 int t4_create_dma_tag(struct adapter *); 706 int t4_destroy_dma_tag(struct adapter *); 707 int t4_setup_adapter_queues(struct adapter *); 708 int t4_teardown_adapter_queues(struct adapter *); 709 int t4_setup_port_queues(struct port_info *); 710 int t4_teardown_port_queues(struct port_info *); 711 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 712 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 713 void t4_intr_all(void *); 714 void t4_intr(void *); 715 void t4_intr_err(void *); 716 void t4_intr_evt(void *); 717 int t4_mgmt_tx(struct adapter *, struct mbuf *); 718 int t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct mbuf *); 719 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 720 void t4_update_fl_bufsize(struct ifnet *); 721 int can_resume_tx(struct sge_eq *); 722 723 static inline int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, struct mbuf *m) 724 { 725 int rc; 726 727 TXQ_LOCK(wrq); 728 rc = t4_wrq_tx_locked(sc, wrq, m); 729 TXQ_UNLOCK(wrq); 730 return (rc); 731 } 732 733 734 #endif 735