xref: /freebsd/sys/dev/cxgbe/adapter.h (revision 273c26a3c3bea87a241d6879abd4f991db180bf0)
1 /*-
2  * Copyright (c) 2011 Chelsio Communications, Inc.
3  * All rights reserved.
4  * Written by: Navdeep Parhar <np@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  *
29  */
30 
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33 
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
41 #include <sys/sx.h>
42 #include <vm/uma.h>
43 
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
55 
56 #include "offload.h"
57 #include "t4_ioctl.h"
58 #include "common/t4_msg.h"
59 #include "firmware/t4fw_interface.h"
60 
61 #define KTR_CXGBE	KTR_SPARE3
62 MALLOC_DECLARE(M_CXGBE);
63 #define CXGBE_UNIMPLEMENTED(s) \
64     panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
65 
66 #if defined(__i386__) || defined(__amd64__)
67 static __inline void
68 prefetch(void *x)
69 {
70 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
71 }
72 #else
73 #define prefetch(x)
74 #endif
75 
76 #ifndef SYSCTL_ADD_UQUAD
77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
78 #define sysctl_handle_64 sysctl_handle_quad
79 #define CTLTYPE_U64 CTLTYPE_QUAD
80 #endif
81 
82 #if (__FreeBSD_version >= 900030) || \
83     ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
84 #define SBUF_DRAIN 1
85 #endif
86 
87 #ifdef __amd64__
88 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
89 static __inline uint64_t
90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
91     bus_size_t offset)
92 {
93 	KASSERT(tag == X86_BUS_SPACE_MEM,
94 	    ("%s: can only handle mem space", __func__));
95 
96 	return (*(volatile uint64_t *)(handle + offset));
97 }
98 
99 static __inline void
100 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
101     bus_size_t offset, uint64_t value)
102 {
103 	KASSERT(tag == X86_BUS_SPACE_MEM,
104 	    ("%s: can only handle mem space", __func__));
105 
106 	*(volatile uint64_t *)(bsh + offset) = value;
107 }
108 #else
109 static __inline uint64_t
110 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
111     bus_size_t offset)
112 {
113 	return (uint64_t)bus_space_read_4(tag, handle, offset) +
114 	    ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
115 }
116 
117 static __inline void
118 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
119     bus_size_t offset, uint64_t value)
120 {
121 	bus_space_write_4(tag, bsh, offset, value);
122 	bus_space_write_4(tag, bsh, offset + 4, value >> 32);
123 }
124 #endif
125 
126 struct adapter;
127 typedef struct adapter adapter_t;
128 
129 enum {
130 	/*
131 	 * All ingress queues use this entry size.  Note that the firmware event
132 	 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
133 	 * be at least 64.
134 	 */
135 	IQ_ESIZE = 64,
136 
137 	/* Default queue sizes for all kinds of ingress queues */
138 	FW_IQ_QSIZE = 256,
139 	RX_IQ_QSIZE = 1024,
140 
141 	/* All egress queues use this entry size */
142 	EQ_ESIZE = 64,
143 
144 	/* Default queue sizes for all kinds of egress queues */
145 	CTRL_EQ_QSIZE = 128,
146 	TX_EQ_QSIZE = 1024,
147 
148 #if MJUMPAGESIZE != MCLBYTES
149 	SW_ZONE_SIZES = 4,	/* cluster, jumbop, jumbo9k, jumbo16k */
150 #else
151 	SW_ZONE_SIZES = 3,	/* cluster, jumbo9k, jumbo16k */
152 #endif
153 	CL_METADATA_SIZE = CACHE_LINE_SIZE,
154 
155 	SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
156 	TX_SGL_SEGS = 39,
157 	TX_SGL_SEGS_TSO = 38,
158 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
159 };
160 
161 enum {
162 	/* adapter intr_type */
163 	INTR_INTX	= (1 << 0),
164 	INTR_MSI 	= (1 << 1),
165 	INTR_MSIX	= (1 << 2)
166 };
167 
168 enum {
169 	XGMAC_MTU	= (1 << 0),
170 	XGMAC_PROMISC	= (1 << 1),
171 	XGMAC_ALLMULTI	= (1 << 2),
172 	XGMAC_VLANEX	= (1 << 3),
173 	XGMAC_UCADDR	= (1 << 4),
174 	XGMAC_MCADDRS	= (1 << 5),
175 
176 	XGMAC_ALL	= 0xffff
177 };
178 
179 enum {
180 	/* flags understood by begin_synchronized_op */
181 	HOLD_LOCK	= (1 << 0),
182 	SLEEP_OK	= (1 << 1),
183 	INTR_OK		= (1 << 2),
184 
185 	/* flags understood by end_synchronized_op */
186 	LOCK_HELD	= HOLD_LOCK,
187 };
188 
189 enum {
190 	/* adapter flags */
191 	FULL_INIT_DONE	= (1 << 0),
192 	FW_OK		= (1 << 1),
193 	/* INTR_DIRECT	= (1 << 2),	No longer used. */
194 	MASTER_PF	= (1 << 3),
195 	ADAP_SYSCTL_CTX	= (1 << 4),
196 	/* TOM_INIT_DONE= (1 << 5),	No longer used */
197 	BUF_PACKING_OK	= (1 << 6),
198 	IS_VF		= (1 << 7),
199 
200 	CXGBE_BUSY	= (1 << 9),
201 
202 	/* port flags */
203 	HAS_TRACEQ	= (1 << 3),
204 
205 	/* VI flags */
206 	DOOMED		= (1 << 0),
207 	VI_INIT_DONE	= (1 << 1),
208 	VI_SYSCTL_CTX	= (1 << 2),
209 	INTR_RXQ	= (1 << 4),	/* All NIC rxq's take interrupts */
210 	INTR_OFLD_RXQ	= (1 << 5),	/* All TOE rxq's take interrupts */
211 	INTR_ALL	= (INTR_RXQ | INTR_OFLD_RXQ),
212 
213 	/* adapter debug_flags */
214 	DF_DUMP_MBOX	= (1 << 0),
215 };
216 
217 #define IS_DOOMED(vi)	((vi)->flags & DOOMED)
218 #define SET_DOOMED(vi)	do {(vi)->flags |= DOOMED;} while (0)
219 #define IS_BUSY(sc)	((sc)->flags & CXGBE_BUSY)
220 #define SET_BUSY(sc)	do {(sc)->flags |= CXGBE_BUSY;} while (0)
221 #define CLR_BUSY(sc)	do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
222 
223 struct vi_info {
224 	device_t dev;
225 	struct port_info *pi;
226 
227 	struct ifnet *ifp;
228 	struct ifmedia media;
229 
230 	unsigned long flags;
231 	int if_flags;
232 
233 	uint16_t *rss, *nm_rss;
234 	int smt_idx;		/* for convenience */
235 	uint16_t viid;
236 	int16_t  xact_addr_filt;/* index of exact MAC address filter */
237 	uint16_t rss_size;	/* size of VI's RSS table slice */
238 	uint16_t rss_base;	/* start of VI's RSS table slice */
239 
240 	eventhandler_tag vlan_c;
241 
242 	int nintr;
243 	int first_intr;
244 
245 	/* These need to be int as they are used in sysctl */
246 	int ntxq;	/* # of tx queues */
247 	int first_txq;	/* index of first tx queue */
248 	int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
249 	int nrxq;	/* # of rx queues */
250 	int first_rxq;	/* index of first rx queue */
251 	int nofldtxq;		/* # of offload tx queues */
252 	int first_ofld_txq;	/* index of first offload tx queue */
253 	int nofldrxq;		/* # of offload rx queues */
254 	int first_ofld_rxq;	/* index of first offload rx queue */
255 	int nnmtxq;
256 	int first_nm_txq;
257 	int nnmrxq;
258 	int first_nm_rxq;
259 	int tmr_idx;
260 	int pktc_idx;
261 	int qsize_rxq;
262 	int qsize_txq;
263 
264 	struct timeval last_refreshed;
265 	struct fw_vi_stats_vf stats;
266 
267 	struct callout tick;
268 	struct sysctl_ctx_list ctx;	/* from ifconfig up to driver detach */
269 
270 	uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
271 };
272 
273 enum {
274 	/* tx_sched_class flags */
275 	TX_SC_OK	= (1 << 0),	/* Set up in hardware, active. */
276 };
277 
278 struct tx_sched_class {
279 	int refcount;
280 	int flags;
281 	struct t4_sched_class_params params;
282 };
283 
284 struct port_info {
285 	device_t dev;
286 	struct adapter *adapter;
287 
288 	struct vi_info *vi;
289 	int nvi;
290 	int up_vis;
291 	int uld_vis;
292 
293 	struct tx_sched_class *tc;	/* traffic classes for this channel */
294 
295 	struct mtx pi_lock;
296 	char lockname[16];
297 	unsigned long flags;
298 
299 	uint8_t  lport;		/* associated offload logical port */
300 	int8_t   mdio_addr;
301 	uint8_t  port_type;
302 	uint8_t  mod_type;
303 	uint8_t  port_id;
304 	uint8_t  tx_chan;
305 	uint8_t  rx_chan_map;	/* rx MPS channel bitmap */
306 
307 	int linkdnrc;
308 	struct link_config link_cfg;
309 
310 	struct timeval last_refreshed;
311  	struct port_stats stats;
312 	u_int tnl_cong_drops;
313 	u_int tx_parse_error;
314 
315 	struct callout tick;
316 };
317 
318 #define	IS_MAIN_VI(vi)		((vi) == &((vi)->pi->vi[0]))
319 
320 /* Where the cluster came from, how it has been carved up. */
321 struct cluster_layout {
322 	int8_t zidx;
323 	int8_t hwidx;
324 	uint16_t region1;	/* mbufs laid out within this region */
325 				/* region2 is the DMA region */
326 	uint16_t region3;	/* cluster_metadata within this region */
327 };
328 
329 struct cluster_metadata {
330 	u_int refcount;
331 	struct fl_sdesc *sd;	/* For debug only.  Could easily be stale */
332 };
333 
334 struct fl_sdesc {
335 	caddr_t cl;
336 	uint16_t nmbuf;	/* # of driver originated mbufs with ref on cluster */
337 	struct cluster_layout cll;
338 };
339 
340 struct tx_desc {
341 	__be64 flit[8];
342 };
343 
344 struct tx_sdesc {
345 	struct mbuf *m;		/* m_nextpkt linked chain of frames */
346 	uint8_t desc_used;	/* # of hardware descriptors used by the WR */
347 };
348 
349 
350 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
351 struct iq_desc {
352 	struct rss_header rss;
353 	uint8_t cpl[IQ_PAD];
354 	struct rsp_ctrl rsp;
355 };
356 #undef IQ_PAD
357 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
358 
359 enum {
360 	/* iq flags */
361 	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
362 	IQ_HAS_FL	= (1 << 1),	/* iq associated with a freelist */
363 	IQ_INTR		= (1 << 2),	/* iq takes direct interrupt */
364 	IQ_LRO_ENABLED	= (1 << 3),	/* iq is an eth rxq with LRO enabled */
365 
366 	/* iq state */
367 	IQS_DISABLED	= 0,
368 	IQS_BUSY	= 1,
369 	IQS_IDLE	= 2,
370 
371 	/* netmap related flags */
372 	NM_OFF	= 0,
373 	NM_ON	= 1,
374 	NM_BUSY	= 2,
375 };
376 
377 struct sge_iq;
378 struct rss_header;
379 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
380     struct mbuf *);
381 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
382 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
383 
384 /*
385  * Ingress Queue: T4 is producer, driver is consumer.
386  */
387 struct sge_iq {
388 	uint32_t flags;
389 	volatile int state;
390 	struct adapter *adapter;
391 	cpl_handler_t set_tcb_rpl;
392 	cpl_handler_t l2t_write_rpl;
393 	struct iq_desc  *desc;	/* KVA of descriptor ring */
394 	int8_t   intr_pktc_idx;	/* packet count threshold index */
395 	uint8_t  gen;		/* generation bit */
396 	uint8_t  intr_params;	/* interrupt holdoff parameters */
397 	uint8_t  intr_next;	/* XXX: holdoff for next interrupt */
398 	uint16_t qsize;		/* size (# of entries) of the queue */
399 	uint16_t sidx;		/* index of the entry with the status page */
400 	uint16_t cidx;		/* consumer index */
401 	uint16_t cntxt_id;	/* SGE context id for the iq */
402 	uint16_t abs_id;	/* absolute SGE id for the iq */
403 
404 	STAILQ_ENTRY(sge_iq) link;
405 
406 	bus_dma_tag_t desc_tag;
407 	bus_dmamap_t desc_map;
408 	bus_addr_t ba;		/* bus address of descriptor ring */
409 };
410 
411 enum {
412 	EQ_CTRL		= 1,
413 	EQ_ETH		= 2,
414 	EQ_OFLD		= 3,
415 
416 	/* eq flags */
417 	EQ_TYPEMASK	= 0x3,		/* 2 lsbits hold the type (see above) */
418 	EQ_ALLOCATED	= (1 << 2),	/* firmware resources allocated */
419 	EQ_ENABLED	= (1 << 3),	/* open for business */
420 };
421 
422 /* Listed in order of preference.  Update t4_sysctls too if you change these */
423 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
424 
425 /*
426  * Egress Queue: driver is producer, T4 is consumer.
427  *
428  * Note: A free list is an egress queue (driver produces the buffers and T4
429  * consumes them) but it's special enough to have its own struct (see sge_fl).
430  */
431 struct sge_eq {
432 	unsigned int flags;	/* MUST be first */
433 	unsigned int cntxt_id;	/* SGE context id for the eq */
434 	unsigned int abs_id;	/* absolute SGE id for the eq */
435 	struct mtx eq_lock;
436 
437 	struct tx_desc *desc;	/* KVA of descriptor ring */
438 	uint16_t doorbells;
439 	volatile uint32_t *udb;	/* KVA of doorbell (lies within BAR2) */
440 	u_int udb_qid;		/* relative qid within the doorbell page */
441 	uint16_t sidx;		/* index of the entry with the status page */
442 	uint16_t cidx;		/* consumer idx (desc idx) */
443 	uint16_t pidx;		/* producer idx (desc idx) */
444 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
445 	uint16_t dbidx;		/* pidx of the most recent doorbell */
446 	uint16_t iqid;		/* iq that gets egr_update for the eq */
447 	uint8_t tx_chan;	/* tx channel used by the eq */
448 	volatile u_int equiq;	/* EQUIQ outstanding */
449 
450 	bus_dma_tag_t desc_tag;
451 	bus_dmamap_t desc_map;
452 	bus_addr_t ba;		/* bus address of descriptor ring */
453 	char lockname[16];
454 };
455 
456 struct sw_zone_info {
457 	uma_zone_t zone;	/* zone that this cluster comes from */
458 	int size;		/* size of cluster: 2K, 4K, 9K, 16K, etc. */
459 	int type;		/* EXT_xxx type of the cluster */
460 	int8_t head_hwidx;
461 	int8_t tail_hwidx;
462 };
463 
464 struct hw_buf_info {
465 	int8_t zidx;		/* backpointer to zone; -ve means unused */
466 	int8_t next;		/* next hwidx for this zone; -1 means no more */
467 	int size;
468 };
469 
470 enum {
471 	NUM_MEMWIN = 3,
472 
473 	MEMWIN0_APERTURE = 2048,
474 	MEMWIN0_BASE     = 0x1b800,
475 
476 	MEMWIN1_APERTURE = 32768,
477 	MEMWIN1_BASE     = 0x28000,
478 
479 	MEMWIN2_APERTURE_T4 = 65536,
480 	MEMWIN2_BASE_T4     = 0x30000,
481 
482 	MEMWIN2_APERTURE_T5 = 128 * 1024,
483 	MEMWIN2_BASE_T5     = 0x60000,
484 };
485 
486 struct memwin {
487 	struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
488 	uint32_t mw_base;	/* constant after setup_memwin */
489 	uint32_t mw_aperture;	/* ditto */
490 	uint32_t mw_curpos;	/* protected by mw_lock */
491 };
492 
493 enum {
494 	FL_STARVING	= (1 << 0), /* on the adapter's list of starving fl's */
495 	FL_DOOMED	= (1 << 1), /* about to be destroyed */
496 	FL_BUF_PACKING	= (1 << 2), /* buffer packing enabled */
497 	FL_BUF_RESUME	= (1 << 3), /* resume from the middle of the frame */
498 };
499 
500 #define FL_RUNNING_LOW(fl) \
501     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
502 #define FL_NOT_RUNNING_LOW(fl) \
503     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
504 
505 struct sge_fl {
506 	struct mtx fl_lock;
507 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
508 	struct fl_sdesc *sdesc;	/* KVA of software descriptor ring */
509 	struct cluster_layout cll_def;	/* default refill zone, layout */
510 	uint16_t lowat;		/* # of buffers <= this means fl needs help */
511 	int flags;
512 	uint16_t buf_boundary;
513 
514 	/* The 16b idx all deal with hw descriptors */
515 	uint16_t dbidx;		/* hw pidx after last doorbell */
516 	uint16_t sidx;		/* index of status page */
517 	volatile uint16_t hw_cidx;
518 
519 	/* The 32b idx are all buffer idx, not hardware descriptor idx */
520 	uint32_t cidx;		/* consumer index */
521 	uint32_t pidx;		/* producer index */
522 
523 	uint32_t dbval;
524 	u_int rx_offset;	/* offset in fl buf (when buffer packing) */
525 	volatile uint32_t *udb;
526 
527 	uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
528 	uint64_t mbuf_inlined;	/* # of mbuf created within clusters */
529 	uint64_t cl_allocated;	/* # of clusters allocated */
530 	uint64_t cl_recycled;	/* # of clusters recycled */
531 	uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
532 
533 	/* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
534 	struct mbuf *m0;
535 	struct mbuf **pnext;
536 	u_int remaining;
537 
538 	uint16_t qsize;		/* # of hw descriptors (status page included) */
539 	uint16_t cntxt_id;	/* SGE context id for the freelist */
540 	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
541 	bus_dma_tag_t desc_tag;
542 	bus_dmamap_t desc_map;
543 	char lockname[16];
544 	bus_addr_t ba;		/* bus address of descriptor ring */
545 	struct cluster_layout cll_alt;	/* alternate refill zone, layout */
546 };
547 
548 struct mp_ring;
549 
550 /* txq: SGE egress queue + what's needed for Ethernet NIC */
551 struct sge_txq {
552 	struct sge_eq eq;	/* MUST be first */
553 
554 	struct ifnet *ifp;	/* the interface this txq belongs to */
555 	struct mp_ring *r;	/* tx software ring */
556 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
557 	struct sglist *gl;
558 	__be32 cpl_ctrl0;	/* for convenience */
559 	int tc_idx;		/* traffic class */
560 
561 	struct task tx_reclaim_task;
562 	/* stats for common events first */
563 
564 	uint64_t txcsum;	/* # of times hardware assisted with checksum */
565 	uint64_t tso_wrs;	/* # of TSO work requests */
566 	uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
567 	uint64_t imm_wrs;	/* # of work requests with immediate data */
568 	uint64_t sgl_wrs;	/* # of work requests with direct SGL */
569 	uint64_t txpkt_wrs;	/* # of txpkt work requests (not coalesced) */
570 	uint64_t txpkts0_wrs;	/* # of type0 coalesced tx work requests */
571 	uint64_t txpkts1_wrs;	/* # of type1 coalesced tx work requests */
572 	uint64_t txpkts0_pkts;	/* # of frames in type0 coalesced tx WRs */
573 	uint64_t txpkts1_pkts;	/* # of frames in type1 coalesced tx WRs */
574 
575 	/* stats for not-that-common events */
576 } __aligned(CACHE_LINE_SIZE);
577 
578 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
579 struct sge_rxq {
580 	struct sge_iq iq;	/* MUST be first */
581 	struct sge_fl fl;	/* MUST follow iq */
582 
583 	struct ifnet *ifp;	/* the interface this rxq belongs to */
584 #if defined(INET) || defined(INET6)
585 	struct lro_ctrl lro;	/* LRO state */
586 #endif
587 
588 	/* stats for common events first */
589 
590 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
591 	uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
592 
593 	/* stats for not-that-common events */
594 
595 } __aligned(CACHE_LINE_SIZE);
596 
597 static inline struct sge_rxq *
598 iq_to_rxq(struct sge_iq *iq)
599 {
600 
601 	return (__containerof(iq, struct sge_rxq, iq));
602 }
603 
604 
605 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
606 struct sge_ofld_rxq {
607 	struct sge_iq iq;	/* MUST be first */
608 	struct sge_fl fl;	/* MUST follow iq */
609 } __aligned(CACHE_LINE_SIZE);
610 
611 static inline struct sge_ofld_rxq *
612 iq_to_ofld_rxq(struct sge_iq *iq)
613 {
614 
615 	return (__containerof(iq, struct sge_ofld_rxq, iq));
616 }
617 
618 struct wrqe {
619 	STAILQ_ENTRY(wrqe) link;
620 	struct sge_wrq *wrq;
621 	int wr_len;
622 	char wr[] __aligned(16);
623 };
624 
625 struct wrq_cookie {
626 	TAILQ_ENTRY(wrq_cookie) link;
627 	int ndesc;
628 	int pidx;
629 };
630 
631 /*
632  * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
633  * and offload tx queues are of this type.
634  */
635 struct sge_wrq {
636 	struct sge_eq eq;	/* MUST be first */
637 
638 	struct adapter *adapter;
639 	struct task wrq_tx_task;
640 
641 	/* Tx desc reserved but WR not "committed" yet. */
642 	TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
643 
644 	/* List of WRs ready to go out as soon as descriptors are available. */
645 	STAILQ_HEAD(, wrqe) wr_list;
646 	u_int nwr_pending;
647 	u_int ndesc_needed;
648 
649 	/* stats for common events first */
650 
651 	uint64_t tx_wrs_direct;	/* # of WRs written directly to desc ring. */
652 	uint64_t tx_wrs_ss;	/* # of WRs copied from scratch space. */
653 	uint64_t tx_wrs_copied;	/* # of WRs queued and copied to desc ring. */
654 
655 	/* stats for not-that-common events */
656 
657 	/*
658 	 * Scratch space for work requests that wrap around after reaching the
659 	 * status page, and some information about the last WR that used it.
660 	 */
661 	uint16_t ss_pidx;
662 	uint16_t ss_len;
663 	uint8_t ss[SGE_MAX_WR_LEN];
664 
665 } __aligned(CACHE_LINE_SIZE);
666 
667 
668 struct sge_nm_rxq {
669 	struct vi_info *vi;
670 
671 	struct iq_desc *iq_desc;
672 	uint16_t iq_abs_id;
673 	uint16_t iq_cntxt_id;
674 	uint16_t iq_cidx;
675 	uint16_t iq_sidx;
676 	uint8_t iq_gen;
677 
678 	__be64  *fl_desc;
679 	uint16_t fl_cntxt_id;
680 	uint32_t fl_cidx;
681 	uint32_t fl_pidx;
682 	uint32_t fl_sidx;
683 	uint32_t fl_db_val;
684 	u_int fl_hwidx:4;
685 
686 	u_int nid;		/* netmap ring # for this queue */
687 
688 	/* infrequently used items after this */
689 
690 	bus_dma_tag_t iq_desc_tag;
691 	bus_dmamap_t iq_desc_map;
692 	bus_addr_t iq_ba;
693 	int intr_idx;
694 
695 	bus_dma_tag_t fl_desc_tag;
696 	bus_dmamap_t fl_desc_map;
697 	bus_addr_t fl_ba;
698 } __aligned(CACHE_LINE_SIZE);
699 
700 struct sge_nm_txq {
701 	struct tx_desc *desc;
702 	uint16_t cidx;
703 	uint16_t pidx;
704 	uint16_t sidx;
705 	uint16_t equiqidx;	/* EQUIQ last requested at this pidx */
706 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
707 	uint16_t dbidx;		/* pidx of the most recent doorbell */
708 	uint16_t doorbells;
709 	volatile uint32_t *udb;
710 	u_int udb_qid;
711 	u_int cntxt_id;
712 	__be32 cpl_ctrl0;	/* for convenience */
713 	u_int nid;		/* netmap ring # for this queue */
714 
715 	/* infrequently used items after this */
716 
717 	bus_dma_tag_t desc_tag;
718 	bus_dmamap_t desc_map;
719 	bus_addr_t ba;
720 	int iqidx;
721 } __aligned(CACHE_LINE_SIZE);
722 
723 struct sge {
724 	int nrxq;	/* total # of Ethernet rx queues */
725 	int ntxq;	/* total # of Ethernet tx tx queues */
726 	int nofldrxq;	/* total # of TOE rx queues */
727 	int nofldtxq;	/* total # of TOE tx queues */
728 	int nnmrxq;	/* total # of netmap rx queues */
729 	int nnmtxq;	/* total # of netmap tx queues */
730 	int niq;	/* total # of ingress queues */
731 	int neq;	/* total # of egress queues */
732 
733 	struct sge_iq fwq;	/* Firmware event queue */
734 	struct sge_wrq mgmtq;	/* Management queue (control queue) */
735 	struct sge_wrq *ctrlq;	/* Control queues */
736 	struct sge_txq *txq;	/* NIC tx queues */
737 	struct sge_rxq *rxq;	/* NIC rx queues */
738 	struct sge_wrq *ofld_txq;	/* TOE tx queues */
739 	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
740 	struct sge_nm_txq *nm_txq;	/* netmap tx queues */
741 	struct sge_nm_rxq *nm_rxq;	/* netmap rx queues */
742 
743 	uint16_t iq_start;	/* first cntxt_id */
744 	uint16_t iq_base;	/* first abs_id */
745 	int eq_start;		/* first cntxt_id */
746 	int eq_base;		/* first abs_id */
747 	struct sge_iq **iqmap;	/* iq->cntxt_id to iq mapping */
748 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
749 
750 	int8_t safe_hwidx1;	/* may not have room for metadata */
751 	int8_t safe_hwidx2;	/* with room for metadata and maybe more */
752 	struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
753 	struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
754 };
755 
756 struct devnames {
757 	const char *nexus_name;
758 	const char *ifnet_name;
759 	const char *vi_ifnet_name;
760 	const char *pf03_drv_name;
761 	const char *vf_nexus_name;
762 	const char *vf_ifnet_name;
763 };
764 
765 struct adapter {
766 	SLIST_ENTRY(adapter) link;
767 	device_t dev;
768 	struct cdev *cdev;
769 	const struct devnames *names;
770 
771 	/* PCIe register resources */
772 	int regs_rid;
773 	struct resource *regs_res;
774 	int msix_rid;
775 	struct resource *msix_res;
776 	bus_space_handle_t bh;
777 	bus_space_tag_t bt;
778 	bus_size_t mmio_len;
779 	int udbs_rid;
780 	struct resource *udbs_res;
781 	volatile uint8_t *udbs_base;
782 
783 	unsigned int pf;
784 	unsigned int mbox;
785 	unsigned int vpd_busy;
786 	unsigned int vpd_flag;
787 
788 	/* Interrupt information */
789 	int intr_type;
790 	int intr_count;
791 	struct irq {
792 		struct resource *res;
793 		int rid;
794 		volatile int nm_state;	/* NM_OFF, NM_ON, or NM_BUSY */
795 		void *tag;
796 		struct sge_rxq *rxq;
797 		struct sge_nm_rxq *nm_rxq;
798 	} __aligned(CACHE_LINE_SIZE) *irq;
799 	int sge_gts_reg;
800 	int sge_kdoorbell_reg;
801 
802 	bus_dma_tag_t dmat;	/* Parent DMA tag */
803 
804 	struct sge sge;
805 	int lro_timeout;
806 	int sc_do_rxcopy;
807 
808 	struct taskqueue *tq[MAX_NCHAN];	/* General purpose taskqueues */
809 	struct port_info *port[MAX_NPORTS];
810 	uint8_t chan_map[MAX_NCHAN];
811 
812 	void *tom_softc;	/* (struct tom_data *) */
813 	struct tom_tunables tt;
814 	void *iwarp_softc;	/* (struct c4iw_dev *) */
815 	void *iscsi_ulp_softc;	/* (struct cxgbei_data *) */
816 	struct l2t_data *l2t;	/* L2 table */
817 	struct tid_info tids;
818 
819 	uint16_t doorbells;
820 	int offload_map;	/* ports with IFCAP_TOE enabled */
821 	int active_ulds;	/* ULDs activated on this adapter */
822 	int flags;
823 	int debug_flags;
824 
825 	char ifp_lockname[16];
826 	struct mtx ifp_lock;
827 	struct ifnet *ifp;	/* tracer ifp */
828 	struct ifmedia media;
829 	int traceq;		/* iq used by all tracers, -1 if none */
830 	int tracer_valid;	/* bitmap of valid tracers */
831 	int tracer_enabled;	/* bitmap of enabled tracers */
832 
833 	char fw_version[16];
834 	char tp_version[16];
835 	char er_version[16];
836 	char bs_version[16];
837 	char cfg_file[32];
838 	u_int cfcsum;
839 	struct adapter_params params;
840 	const struct chip_params *chip_params;
841 	struct t4_virt_res vres;
842 
843 	uint16_t nbmcaps;
844 	uint16_t linkcaps;
845 	uint16_t switchcaps;
846 	uint16_t niccaps;
847 	uint16_t toecaps;
848 	uint16_t rdmacaps;
849 	uint16_t cryptocaps;
850 	uint16_t iscsicaps;
851 	uint16_t fcoecaps;
852 
853 	struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
854 
855 	struct mtx sc_lock;
856 	char lockname[16];
857 
858 	/* Starving free lists */
859 	struct mtx sfl_lock;	/* same cache-line as sc_lock? but that's ok */
860 	TAILQ_HEAD(, sge_fl) sfl;
861 	struct callout sfl_callout;
862 
863 	struct mtx reg_lock;	/* for indirect register access */
864 
865 	struct memwin memwin[NUM_MEMWIN];	/* memory windows */
866 
867 	const char *last_op;
868 	const void *last_op_thr;
869 	int last_op_flags;
870 };
871 
872 #define ADAPTER_LOCK(sc)		mtx_lock(&(sc)->sc_lock)
873 #define ADAPTER_UNLOCK(sc)		mtx_unlock(&(sc)->sc_lock)
874 #define ADAPTER_LOCK_ASSERT_OWNED(sc)	mtx_assert(&(sc)->sc_lock, MA_OWNED)
875 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
876 
877 #define ASSERT_SYNCHRONIZED_OP(sc)	\
878     KASSERT(IS_BUSY(sc) && \
879 	(mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
880 	("%s: operation not synchronized.", __func__))
881 
882 #define PORT_LOCK(pi)			mtx_lock(&(pi)->pi_lock)
883 #define PORT_UNLOCK(pi)			mtx_unlock(&(pi)->pi_lock)
884 #define PORT_LOCK_ASSERT_OWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_OWNED)
885 #define PORT_LOCK_ASSERT_NOTOWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
886 
887 #define FL_LOCK(fl)			mtx_lock(&(fl)->fl_lock)
888 #define FL_TRYLOCK(fl)			mtx_trylock(&(fl)->fl_lock)
889 #define FL_UNLOCK(fl)			mtx_unlock(&(fl)->fl_lock)
890 #define FL_LOCK_ASSERT_OWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_OWNED)
891 #define FL_LOCK_ASSERT_NOTOWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
892 
893 #define RXQ_FL_LOCK(rxq)		FL_LOCK(&(rxq)->fl)
894 #define RXQ_FL_UNLOCK(rxq)		FL_UNLOCK(&(rxq)->fl)
895 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq)	FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
896 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
897 
898 #define EQ_LOCK(eq)			mtx_lock(&(eq)->eq_lock)
899 #define EQ_TRYLOCK(eq)			mtx_trylock(&(eq)->eq_lock)
900 #define EQ_UNLOCK(eq)			mtx_unlock(&(eq)->eq_lock)
901 #define EQ_LOCK_ASSERT_OWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_OWNED)
902 #define EQ_LOCK_ASSERT_NOTOWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
903 
904 #define TXQ_LOCK(txq)			EQ_LOCK(&(txq)->eq)
905 #define TXQ_TRYLOCK(txq)		EQ_TRYLOCK(&(txq)->eq)
906 #define TXQ_UNLOCK(txq)			EQ_UNLOCK(&(txq)->eq)
907 #define TXQ_LOCK_ASSERT_OWNED(txq)	EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
908 #define TXQ_LOCK_ASSERT_NOTOWNED(txq)	EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
909 
910 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
911 	do { \
912 		if (sc->debug_flags & DF_DUMP_MBOX) { \
913 			log(LOG_NOTICE, \
914 			    "%s mbox %u: %016llx %016llx %016llx %016llx " \
915 			    "%016llx %016llx %016llx %016llx\n", \
916 			    device_get_nameunit(sc->dev), mbox, \
917 			    (unsigned long long)t4_read_reg64(sc, data_reg), \
918 			    (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
919 			    (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
920 			    (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
921 			    (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
922 			    (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
923 			    (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
924 			    (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
925 		} \
926 	} while (0)
927 
928 #define for_each_txq(vi, iter, q) \
929 	for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
930 	    iter < vi->ntxq; ++iter, ++q)
931 #define for_each_rxq(vi, iter, q) \
932 	for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
933 	    iter < vi->nrxq; ++iter, ++q)
934 #define for_each_ofld_txq(vi, iter, q) \
935 	for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
936 	    iter < vi->nofldtxq; ++iter, ++q)
937 #define for_each_ofld_rxq(vi, iter, q) \
938 	for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
939 	    iter < vi->nofldrxq; ++iter, ++q)
940 #define for_each_nm_txq(vi, iter, q) \
941 	for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
942 	    iter < vi->nnmtxq; ++iter, ++q)
943 #define for_each_nm_rxq(vi, iter, q) \
944 	for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
945 	    iter < vi->nnmrxq; ++iter, ++q)
946 #define for_each_vi(_pi, _iter, _vi) \
947 	for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
948 	     ++(_iter), ++(_vi))
949 
950 #define IDXINCR(idx, incr, wrap) do { \
951 	idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
952 } while (0)
953 #define IDXDIFF(head, tail, wrap) \
954 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
955 
956 /* One for errors, one for firmware events */
957 #define T4_EXTRA_INTR 2
958 
959 /* One for firmware events */
960 #define T4VF_EXTRA_INTR 1
961 
962 static inline uint32_t
963 t4_read_reg(struct adapter *sc, uint32_t reg)
964 {
965 
966 	return bus_space_read_4(sc->bt, sc->bh, reg);
967 }
968 
969 static inline void
970 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
971 {
972 
973 	bus_space_write_4(sc->bt, sc->bh, reg, val);
974 }
975 
976 static inline uint64_t
977 t4_read_reg64(struct adapter *sc, uint32_t reg)
978 {
979 
980 	return t4_bus_space_read_8(sc->bt, sc->bh, reg);
981 }
982 
983 static inline void
984 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
985 {
986 
987 	t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
988 }
989 
990 static inline void
991 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
992 {
993 
994 	*val = pci_read_config(sc->dev, reg, 1);
995 }
996 
997 static inline void
998 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
999 {
1000 
1001 	pci_write_config(sc->dev, reg, val, 1);
1002 }
1003 
1004 static inline void
1005 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1006 {
1007 
1008 	*val = pci_read_config(sc->dev, reg, 2);
1009 }
1010 
1011 static inline void
1012 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1013 {
1014 
1015 	pci_write_config(sc->dev, reg, val, 2);
1016 }
1017 
1018 static inline void
1019 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1020 {
1021 
1022 	*val = pci_read_config(sc->dev, reg, 4);
1023 }
1024 
1025 static inline void
1026 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1027 {
1028 
1029 	pci_write_config(sc->dev, reg, val, 4);
1030 }
1031 
1032 static inline struct port_info *
1033 adap2pinfo(struct adapter *sc, int idx)
1034 {
1035 
1036 	return (sc->port[idx]);
1037 }
1038 
1039 static inline void
1040 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
1041 {
1042 
1043 	bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN);
1044 }
1045 
1046 static inline bool
1047 is_10G_port(const struct port_info *pi)
1048 {
1049 
1050 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1051 }
1052 
1053 static inline bool
1054 is_25G_port(const struct port_info *pi)
1055 {
1056 
1057 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1058 }
1059 
1060 static inline bool
1061 is_40G_port(const struct port_info *pi)
1062 {
1063 
1064 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1065 }
1066 
1067 static inline bool
1068 is_100G_port(const struct port_info *pi)
1069 {
1070 
1071 	return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1072 }
1073 
1074 static inline int
1075 port_top_speed(const struct port_info *pi)
1076 {
1077 
1078 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1079 		return (100);
1080 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1081 		return (40);
1082 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1083 		return (25);
1084 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1085 		return (10);
1086 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1087 		return (1);
1088 
1089 	return (0);
1090 }
1091 
1092 static inline int
1093 tx_resume_threshold(struct sge_eq *eq)
1094 {
1095 
1096 	/* not quite the same as qsize / 4, but this will do. */
1097 	return (eq->sidx / 4);
1098 }
1099 
1100 static inline int
1101 t4_use_ldst(struct adapter *sc)
1102 {
1103 
1104 #ifdef notyet
1105 	return (sc->flags & FW_OK || !sc->use_bd);
1106 #else
1107 	return (0);
1108 #endif
1109 }
1110 
1111 /* t4_main.c */
1112 extern int t4_ntxq10g;
1113 extern int t4_nrxq10g;
1114 extern int t4_ntxq1g;
1115 extern int t4_nrxq1g;
1116 extern int t4_intr_types;
1117 extern int t4_tmr_idx_10g;
1118 extern int t4_pktc_idx_10g;
1119 extern int t4_tmr_idx_1g;
1120 extern int t4_pktc_idx_1g;
1121 extern unsigned int t4_qsize_rxq;
1122 extern unsigned int t4_qsize_txq;
1123 extern device_method_t cxgbe_methods[];
1124 
1125 int t4_os_find_pci_capability(struct adapter *, int);
1126 int t4_os_pci_save_state(struct adapter *);
1127 int t4_os_pci_restore_state(struct adapter *);
1128 void t4_os_portmod_changed(const struct adapter *, int);
1129 void t4_os_link_changed(struct adapter *, int, int, int);
1130 void t4_iterate(void (*)(struct adapter *, void *), void *);
1131 void t4_init_devnames(struct adapter *);
1132 void t4_add_adapter(struct adapter *);
1133 int t4_detach_common(device_t);
1134 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1135 int t4_map_bars_0_and_4(struct adapter *);
1136 int t4_map_bar_2(struct adapter *);
1137 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1138 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1139 int t4_setup_intr_handlers(struct adapter *);
1140 void t4_sysctls(struct adapter *);
1141 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1142 void doom_vi(struct adapter *, struct vi_info *);
1143 void end_synchronized_op(struct adapter *, int);
1144 int update_mac_settings(struct ifnet *, int);
1145 int adapter_full_init(struct adapter *);
1146 int adapter_full_uninit(struct adapter *);
1147 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1148 int vi_full_init(struct vi_info *);
1149 int vi_full_uninit(struct vi_info *);
1150 void vi_sysctls(struct vi_info *);
1151 void vi_tick(void *);
1152 
1153 #ifdef DEV_NETMAP
1154 /* t4_netmap.c */
1155 void cxgbe_nm_attach(struct vi_info *);
1156 void cxgbe_nm_detach(struct vi_info *);
1157 void t4_nm_intr(void *);
1158 #endif
1159 
1160 /* t4_sge.c */
1161 void t4_sge_modload(void);
1162 void t4_sge_modunload(void);
1163 uint64_t t4_sge_extfree_refs(void);
1164 void t4_tweak_chip_settings(struct adapter *);
1165 int t4_read_chip_settings(struct adapter *);
1166 int t4_create_dma_tag(struct adapter *);
1167 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1168     struct sysctl_oid_list *);
1169 int t4_destroy_dma_tag(struct adapter *);
1170 int t4_setup_adapter_queues(struct adapter *);
1171 int t4_teardown_adapter_queues(struct adapter *);
1172 int t4_setup_vi_queues(struct vi_info *);
1173 int t4_teardown_vi_queues(struct vi_info *);
1174 void t4_intr_all(void *);
1175 void t4_intr(void *);
1176 void t4_vi_intr(void *);
1177 void t4_intr_err(void *);
1178 void t4_intr_evt(void *);
1179 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1180 void t4_update_fl_bufsize(struct ifnet *);
1181 int parse_pkt(struct adapter *, struct mbuf **);
1182 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1183 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1184 int tnl_cong(struct port_info *, int);
1185 int t4_register_an_handler(an_handler_t);
1186 int t4_register_fw_msg_handler(int, fw_msg_handler_t);
1187 int t4_register_cpl_handler(int, cpl_handler_t);
1188 
1189 /* t4_tracer.c */
1190 struct t4_tracer;
1191 void t4_tracer_modload(void);
1192 void t4_tracer_modunload(void);
1193 void t4_tracer_port_detach(struct adapter *);
1194 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1195 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1196 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1197 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1198 
1199 static inline struct wrqe *
1200 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1201 {
1202 	int len = offsetof(struct wrqe, wr) + wr_len;
1203 	struct wrqe *wr;
1204 
1205 	wr = malloc(len, M_CXGBE, M_NOWAIT);
1206 	if (__predict_false(wr == NULL))
1207 		return (NULL);
1208 	wr->wr_len = wr_len;
1209 	wr->wrq = wrq;
1210 	return (wr);
1211 }
1212 
1213 static inline void *
1214 wrtod(struct wrqe *wr)
1215 {
1216 	return (&wr->wr[0]);
1217 }
1218 
1219 static inline void
1220 free_wrqe(struct wrqe *wr)
1221 {
1222 	free(wr, M_CXGBE);
1223 }
1224 
1225 static inline void
1226 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1227 {
1228 	struct sge_wrq *wrq = wr->wrq;
1229 
1230 	TXQ_LOCK(wrq);
1231 	t4_wrq_tx_locked(sc, wrq, wr);
1232 	TXQ_UNLOCK(wrq);
1233 }
1234 
1235 #endif
1236