1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_media.h> 58 #include <net/pfil.h> 59 #include <netinet/in.h> 60 #include <netinet/tcp_lro.h> 61 62 #include "offload.h" 63 #include "t4_ioctl.h" 64 #include "common/t4_msg.h" 65 #include "firmware/t4fw_interface.h" 66 67 #define KTR_CXGBE KTR_SPARE3 68 MALLOC_DECLARE(M_CXGBE); 69 #define CXGBE_UNIMPLEMENTED(s) \ 70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 71 72 /* 73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 74 * LIST_HEAD when building iw_cxgbe. 75 */ 76 #define CXGBE_LIST_HEAD(name, type) \ 77 struct name { \ 78 struct type *lh_first; /* first element */ \ 79 } 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags. synch_op or adapter_lock. */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 BUF_PACKING_OK = (1 << 6), 163 IS_VF = (1 << 7), 164 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 165 CXGBE_BUSY = (1 << 9), 166 167 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 168 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 169 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 170 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 171 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 172 173 /* port flags */ 174 HAS_TRACEQ = (1 << 3), 175 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 176 177 /* VI flags */ 178 DOOMED = (1 << 0), 179 VI_INIT_DONE = (1 << 1), 180 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 181 TX_USES_VM_WR = (1 << 3), 182 VI_SKIP_STATS = (1 << 4), 183 184 /* adapter debug_flags */ 185 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 186 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 187 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 188 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 189 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 190 }; 191 192 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 193 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 194 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 195 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 196 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 197 198 struct vi_info { 199 device_t dev; 200 struct port_info *pi; 201 struct adapter *adapter; 202 203 struct ifnet *ifp; 204 struct pfil_head *pfil; 205 206 unsigned long flags; 207 int if_flags; 208 209 uint16_t *rss, *nm_rss; 210 uint16_t viid; /* opaque VI identifier */ 211 uint16_t smt_idx; 212 uint16_t vin; 213 uint8_t vfvld; 214 int16_t xact_addr_filt;/* index of exact MAC address filter */ 215 uint16_t rss_size; /* size of VI's RSS table slice */ 216 uint16_t rss_base; /* start of VI's RSS table slice */ 217 int hashen; 218 219 int nintr; 220 int first_intr; 221 222 /* These need to be int as they are used in sysctl */ 223 int ntxq; /* # of tx queues */ 224 int first_txq; /* index of first tx queue */ 225 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 226 int nrxq; /* # of rx queues */ 227 int first_rxq; /* index of first rx queue */ 228 int nofldtxq; /* # of offload tx queues */ 229 int first_ofld_txq; /* index of first offload tx queue */ 230 int nofldrxq; /* # of offload rx queues */ 231 int first_ofld_rxq; /* index of first offload rx queue */ 232 int nnmtxq; 233 int first_nm_txq; 234 int nnmrxq; 235 int first_nm_rxq; 236 int tmr_idx; 237 int ofld_tmr_idx; 238 int pktc_idx; 239 int ofld_pktc_idx; 240 int qsize_rxq; 241 int qsize_txq; 242 243 struct timeval last_refreshed; 244 struct fw_vi_stats_vf stats; 245 struct mtx tick_mtx; 246 struct callout tick; 247 248 struct sysctl_ctx_list ctx; 249 struct sysctl_oid *rxq_oid; 250 struct sysctl_oid *txq_oid; 251 struct sysctl_oid *nm_rxq_oid; 252 struct sysctl_oid *nm_txq_oid; 253 struct sysctl_oid *ofld_rxq_oid; 254 struct sysctl_oid *ofld_txq_oid; 255 256 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 257 u_int txq_rr; 258 u_int rxq_rr; 259 }; 260 261 struct tx_ch_rl_params { 262 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 263 uint32_t maxrate; 264 }; 265 266 /* CLRL state */ 267 enum clrl_state { 268 CS_UNINITIALIZED = 0, 269 CS_PARAMS_SET, /* sw parameters have been set. */ 270 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 271 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 272 CS_HW_CONFIGURED /* configured in the hardware. */ 273 }; 274 275 /* CLRL flags */ 276 enum { 277 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 278 }; 279 280 struct tx_cl_rl_params { 281 enum clrl_state state; 282 int refcount; 283 uint8_t flags; 284 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 285 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 286 enum fw_sched_params_mode mode; /* aggr or per-flow */ 287 uint32_t maxrate; 288 uint16_t pktsize; 289 uint16_t burstsize; 290 }; 291 292 /* Tx scheduler parameters for a channel/port */ 293 struct tx_sched_params { 294 /* Channel Rate Limiter */ 295 struct tx_ch_rl_params ch_rl; 296 297 /* Class WRR */ 298 /* XXX */ 299 300 /* Class Rate Limiter (including the default pktsize and burstsize). */ 301 int pktsize; 302 int burstsize; 303 struct tx_cl_rl_params cl_rl[]; 304 }; 305 306 struct port_info { 307 device_t dev; 308 struct adapter *adapter; 309 310 struct vi_info *vi; 311 int nvi; 312 int up_vis; 313 int uld_vis; 314 bool vxlan_tcam_entry; 315 316 struct tx_sched_params *sched_params; 317 318 struct mtx pi_lock; 319 char lockname[16]; 320 unsigned long flags; 321 322 uint8_t lport; /* associated offload logical port */ 323 int8_t mdio_addr; 324 uint8_t port_type; 325 uint8_t mod_type; 326 uint8_t port_id; 327 uint8_t tx_chan; 328 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 329 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 330 uint8_t rx_c_chan; /* rx TP c-channel */ 331 332 struct link_config link_cfg; 333 struct ifmedia media; 334 335 struct port_stats stats; 336 u_int tnl_cong_drops; 337 u_int tx_parse_error; 338 int fcs_reg; 339 uint64_t fcs_base; 340 341 struct sysctl_ctx_list ctx; 342 }; 343 344 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 345 346 struct cluster_metadata { 347 uma_zone_t zone; 348 caddr_t cl; 349 u_int refcount; 350 }; 351 352 struct fl_sdesc { 353 caddr_t cl; 354 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 355 int16_t moff; /* offset of metadata from cl */ 356 uint8_t zidx; 357 }; 358 359 struct tx_desc { 360 __be64 flit[8]; 361 }; 362 363 struct tx_sdesc { 364 struct mbuf *m; /* m_nextpkt linked chain of frames */ 365 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 366 }; 367 368 369 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 370 struct iq_desc { 371 struct rss_header rss; 372 uint8_t cpl[IQ_PAD]; 373 struct rsp_ctrl rsp; 374 }; 375 #undef IQ_PAD 376 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 377 378 enum { 379 /* iq flags */ 380 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 381 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 382 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 383 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 384 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 385 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 386 387 /* iq state */ 388 IQS_DISABLED = 0, 389 IQS_BUSY = 1, 390 IQS_IDLE = 2, 391 392 /* netmap related flags */ 393 NM_OFF = 0, 394 NM_ON = 1, 395 NM_BUSY = 2, 396 }; 397 398 enum { 399 CPL_COOKIE_RESERVED = 0, 400 CPL_COOKIE_FILTER, 401 CPL_COOKIE_DDP0, 402 CPL_COOKIE_DDP1, 403 CPL_COOKIE_TOM, 404 CPL_COOKIE_HASHFILTER, 405 CPL_COOKIE_ETHOFLD, 406 CPL_COOKIE_KERN_TLS, 407 408 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 409 }; 410 411 struct sge_iq; 412 struct rss_header; 413 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 414 struct mbuf *); 415 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 416 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 417 418 /* 419 * Ingress Queue: T4 is producer, driver is consumer. 420 */ 421 struct sge_iq { 422 uint32_t flags; 423 volatile int state; 424 struct adapter *adapter; 425 struct iq_desc *desc; /* KVA of descriptor ring */ 426 int8_t intr_pktc_idx; /* packet count threshold index */ 427 uint8_t gen; /* generation bit */ 428 uint8_t intr_params; /* interrupt holdoff parameters */ 429 int8_t cong; /* congestion settings */ 430 uint16_t qsize; /* size (# of entries) of the queue */ 431 uint16_t sidx; /* index of the entry with the status page */ 432 uint16_t cidx; /* consumer index */ 433 uint16_t cntxt_id; /* SGE context id for the iq */ 434 uint16_t abs_id; /* absolute SGE id for the iq */ 435 int16_t intr_idx; /* interrupt used by the queue */ 436 437 STAILQ_ENTRY(sge_iq) link; 438 439 bus_dma_tag_t desc_tag; 440 bus_dmamap_t desc_map; 441 bus_addr_t ba; /* bus address of descriptor ring */ 442 }; 443 444 enum { 445 /* eq type */ 446 EQ_CTRL = 1, 447 EQ_ETH = 2, 448 EQ_OFLD = 3, 449 450 /* eq flags */ 451 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 452 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 453 EQ_ENABLED = (1 << 3), /* open for business */ 454 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 455 }; 456 457 /* Listed in order of preference. Update t4_sysctls too if you change these */ 458 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 459 460 /* 461 * Egress Queue: driver is producer, T4 is consumer. 462 * 463 * Note: A free list is an egress queue (driver produces the buffers and T4 464 * consumes them) but it's special enough to have its own struct (see sge_fl). 465 */ 466 struct sge_eq { 467 unsigned int flags; /* MUST be first */ 468 unsigned int cntxt_id; /* SGE context id for the eq */ 469 unsigned int abs_id; /* absolute SGE id for the eq */ 470 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 471 uint8_t doorbells; 472 uint8_t tx_chan; /* tx channel used by the eq */ 473 struct mtx eq_lock; 474 475 struct tx_desc *desc; /* KVA of descriptor ring */ 476 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 477 u_int udb_qid; /* relative qid within the doorbell page */ 478 uint16_t sidx; /* index of the entry with the status page */ 479 uint16_t cidx; /* consumer idx (desc idx) */ 480 uint16_t pidx; /* producer idx (desc idx) */ 481 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 482 uint16_t dbidx; /* pidx of the most recent doorbell */ 483 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 484 volatile u_int equiq; /* EQUIQ outstanding */ 485 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 486 487 bus_dma_tag_t desc_tag; 488 bus_dmamap_t desc_map; 489 bus_addr_t ba; /* bus address of descriptor ring */ 490 char lockname[16]; 491 }; 492 493 struct rx_buf_info { 494 uma_zone_t zone; /* zone that this cluster comes from */ 495 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 496 * hwsize[hwidx1] = size1. No spare. */ 497 uint16_t size2; /* hwsize[hwidx2] = size2. 498 * spare in cluster = size1 - size2. */ 499 int8_t hwidx1; /* SGE bufsize idx for size1 */ 500 int8_t hwidx2; /* SGE bufsize idx for size2 */ 501 uint8_t type; /* EXT_xxx type of the cluster */ 502 }; 503 504 enum { 505 NUM_MEMWIN = 3, 506 507 MEMWIN0_APERTURE = 2048, 508 MEMWIN0_BASE = 0x1b800, 509 510 MEMWIN1_APERTURE = 32768, 511 MEMWIN1_BASE = 0x28000, 512 513 MEMWIN2_APERTURE_T4 = 65536, 514 MEMWIN2_BASE_T4 = 0x30000, 515 516 MEMWIN2_APERTURE_T5 = 128 * 1024, 517 MEMWIN2_BASE_T5 = 0x60000, 518 }; 519 520 struct memwin { 521 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 522 uint32_t mw_base; /* constant after setup_memwin */ 523 uint32_t mw_aperture; /* ditto */ 524 uint32_t mw_curpos; /* protected by mw_lock */ 525 }; 526 527 enum { 528 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 529 FL_DOOMED = (1 << 1), /* about to be destroyed */ 530 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 531 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 532 }; 533 534 #define FL_RUNNING_LOW(fl) \ 535 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 536 #define FL_NOT_RUNNING_LOW(fl) \ 537 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 538 539 struct sge_fl { 540 struct mtx fl_lock; 541 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 542 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 543 uint16_t zidx; /* refill zone idx */ 544 uint16_t safe_zidx; 545 uint16_t lowat; /* # of buffers <= this means fl needs help */ 546 int flags; 547 uint16_t buf_boundary; 548 549 /* The 16b idx all deal with hw descriptors */ 550 uint16_t dbidx; /* hw pidx after last doorbell */ 551 uint16_t sidx; /* index of status page */ 552 volatile uint16_t hw_cidx; 553 554 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 555 uint32_t cidx; /* consumer index */ 556 uint32_t pidx; /* producer index */ 557 558 uint32_t dbval; 559 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 560 volatile uint32_t *udb; 561 562 uint64_t cl_allocated; /* # of clusters allocated */ 563 uint64_t cl_recycled; /* # of clusters recycled */ 564 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 565 566 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 567 struct mbuf *m0; 568 struct mbuf **pnext; 569 u_int remaining; 570 571 uint16_t qsize; /* # of hw descriptors (status page included) */ 572 uint16_t cntxt_id; /* SGE context id for the freelist */ 573 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 574 bus_dma_tag_t desc_tag; 575 bus_dmamap_t desc_map; 576 char lockname[16]; 577 bus_addr_t ba; /* bus address of descriptor ring */ 578 }; 579 580 struct mp_ring; 581 582 struct txpkts { 583 uint8_t wr_type; /* type 0 or type 1 */ 584 uint8_t npkt; /* # of packets in this work request */ 585 uint8_t len16; /* # of 16B pieces used by this work request */ 586 uint8_t score; 587 uint8_t max_npkt; /* maximum number of packets allowed */ 588 uint16_t plen; /* total payload (sum of all packets) */ 589 590 /* straight from fw_eth_tx_pkts_vm_wr. */ 591 __u8 ethmacdst[6]; 592 __u8 ethmacsrc[6]; 593 __be16 ethtype; 594 __be16 vlantci; 595 596 struct mbuf *mb[15]; 597 }; 598 599 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 600 struct sge_txq { 601 struct sge_eq eq; /* MUST be first */ 602 603 struct ifnet *ifp; /* the interface this txq belongs to */ 604 struct mp_ring *r; /* tx software ring */ 605 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 606 struct sglist *gl; 607 __be32 cpl_ctrl0; /* for convenience */ 608 int tc_idx; /* traffic class */ 609 uint64_t last_tx; /* cycle count when eth_tx was last called */ 610 struct txpkts txp; 611 612 struct task tx_reclaim_task; 613 /* stats for common events first */ 614 615 uint64_t txcsum; /* # of times hardware assisted with checksum */ 616 uint64_t tso_wrs; /* # of TSO work requests */ 617 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 618 uint64_t imm_wrs; /* # of work requests with immediate data */ 619 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 620 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 621 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 622 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 623 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 624 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 625 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 626 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 627 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 628 uint64_t vxlan_txcsum; 629 630 uint64_t kern_tls_records; 631 uint64_t kern_tls_short; 632 uint64_t kern_tls_partial; 633 uint64_t kern_tls_full; 634 uint64_t kern_tls_octets; 635 uint64_t kern_tls_waste; 636 uint64_t kern_tls_options; 637 uint64_t kern_tls_header; 638 uint64_t kern_tls_fin; 639 uint64_t kern_tls_fin_short; 640 uint64_t kern_tls_cbc; 641 uint64_t kern_tls_gcm; 642 643 /* stats for not-that-common events */ 644 645 /* Optional scratch space for constructing work requests. */ 646 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 647 } __aligned(CACHE_LINE_SIZE); 648 649 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 650 struct sge_rxq { 651 struct sge_iq iq; /* MUST be first */ 652 struct sge_fl fl; /* MUST follow iq */ 653 654 struct ifnet *ifp; /* the interface this rxq belongs to */ 655 struct lro_ctrl lro; /* LRO state */ 656 657 /* stats for common events first */ 658 659 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 660 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 661 uint64_t vxlan_rxcsum; 662 663 /* stats for not-that-common events */ 664 665 } __aligned(CACHE_LINE_SIZE); 666 667 static inline struct sge_rxq * 668 iq_to_rxq(struct sge_iq *iq) 669 { 670 671 return (__containerof(iq, struct sge_rxq, iq)); 672 } 673 674 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 675 struct sge_ofld_rxq { 676 struct sge_iq iq; /* MUST be first */ 677 struct sge_fl fl; /* MUST follow iq */ 678 counter_u64_t rx_iscsi_ddp_setup_ok; 679 counter_u64_t rx_iscsi_ddp_setup_error; 680 uint64_t rx_iscsi_ddp_pdus; 681 uint64_t rx_iscsi_ddp_octets; 682 uint64_t rx_iscsi_fl_pdus; 683 uint64_t rx_iscsi_fl_octets; 684 uint64_t rx_iscsi_padding_errors; 685 uint64_t rx_iscsi_header_digest_errors; 686 uint64_t rx_iscsi_data_digest_errors; 687 u_long rx_toe_tls_records; 688 u_long rx_toe_tls_octets; 689 } __aligned(CACHE_LINE_SIZE); 690 691 static inline struct sge_ofld_rxq * 692 iq_to_ofld_rxq(struct sge_iq *iq) 693 { 694 695 return (__containerof(iq, struct sge_ofld_rxq, iq)); 696 } 697 698 struct wrqe { 699 STAILQ_ENTRY(wrqe) link; 700 struct sge_wrq *wrq; 701 int wr_len; 702 char wr[] __aligned(16); 703 }; 704 705 struct wrq_cookie { 706 TAILQ_ENTRY(wrq_cookie) link; 707 int ndesc; 708 int pidx; 709 }; 710 711 /* 712 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 713 * are of this type. 714 */ 715 struct sge_wrq { 716 struct sge_eq eq; /* MUST be first */ 717 718 struct adapter *adapter; 719 struct task wrq_tx_task; 720 721 /* Tx desc reserved but WR not "committed" yet. */ 722 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 723 724 /* List of WRs ready to go out as soon as descriptors are available. */ 725 STAILQ_HEAD(, wrqe) wr_list; 726 u_int nwr_pending; 727 u_int ndesc_needed; 728 729 /* stats for common events first */ 730 731 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 732 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 733 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 734 735 /* stats for not-that-common events */ 736 737 /* 738 * Scratch space for work requests that wrap around after reaching the 739 * status page, and some information about the last WR that used it. 740 */ 741 uint16_t ss_pidx; 742 uint16_t ss_len; 743 uint8_t ss[SGE_MAX_WR_LEN]; 744 745 } __aligned(CACHE_LINE_SIZE); 746 747 /* ofld_txq: SGE egress queue + miscellaneous items */ 748 struct sge_ofld_txq { 749 struct sge_wrq wrq; 750 counter_u64_t tx_iscsi_pdus; 751 counter_u64_t tx_iscsi_octets; 752 counter_u64_t tx_iscsi_iso_wrs; 753 counter_u64_t tx_toe_tls_records; 754 counter_u64_t tx_toe_tls_octets; 755 } __aligned(CACHE_LINE_SIZE); 756 757 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 758 struct sge_nm_rxq { 759 /* Items used by the driver rx ithread are in this cacheline. */ 760 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 761 u_int nid; /* netmap ring # for this queue */ 762 struct vi_info *vi; 763 764 struct iq_desc *iq_desc; 765 uint16_t iq_abs_id; 766 uint16_t iq_cntxt_id; 767 uint16_t iq_cidx; 768 uint16_t iq_sidx; 769 uint8_t iq_gen; 770 uint32_t fl_sidx; 771 772 /* Items used by netmap rxsync are in this cacheline. */ 773 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 774 uint16_t fl_cntxt_id; 775 uint32_t fl_pidx; 776 uint32_t fl_sidx2; /* copy of fl_sidx */ 777 uint32_t fl_db_val; 778 u_int fl_db_saved; 779 u_int fl_db_threshold; /* in descriptors */ 780 u_int fl_hwidx:4; 781 782 /* 783 * fl_cidx is used by both the ithread and rxsync, the rest are not used 784 * in the rx fast path. 785 */ 786 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 787 788 bus_dma_tag_t iq_desc_tag; 789 bus_dmamap_t iq_desc_map; 790 bus_addr_t iq_ba; 791 int intr_idx; 792 793 bus_dma_tag_t fl_desc_tag; 794 bus_dmamap_t fl_desc_map; 795 bus_addr_t fl_ba; 796 }; 797 798 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 799 struct sge_nm_txq { 800 struct tx_desc *desc; 801 uint16_t cidx; 802 uint16_t pidx; 803 uint16_t sidx; 804 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 805 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 806 uint16_t dbidx; /* pidx of the most recent doorbell */ 807 uint8_t doorbells; 808 volatile uint32_t *udb; 809 u_int udb_qid; 810 u_int cntxt_id; 811 __be32 cpl_ctrl0; /* for convenience */ 812 __be32 op_pkd; /* ditto */ 813 u_int nid; /* netmap ring # for this queue */ 814 815 /* infrequently used items after this */ 816 817 bus_dma_tag_t desc_tag; 818 bus_dmamap_t desc_map; 819 bus_addr_t ba; 820 int iqidx; 821 } __aligned(CACHE_LINE_SIZE); 822 823 struct sge { 824 int nrxq; /* total # of Ethernet rx queues */ 825 int ntxq; /* total # of Ethernet tx queues */ 826 int nofldrxq; /* total # of TOE rx queues */ 827 int nofldtxq; /* total # of TOE tx queues */ 828 int nnmrxq; /* total # of netmap rx queues */ 829 int nnmtxq; /* total # of netmap tx queues */ 830 int niq; /* total # of ingress queues */ 831 int neq; /* total # of egress queues */ 832 833 struct sge_iq fwq; /* Firmware event queue */ 834 struct sge_wrq *ctrlq; /* Control queues */ 835 struct sge_txq *txq; /* NIC tx queues */ 836 struct sge_rxq *rxq; /* NIC rx queues */ 837 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 838 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 839 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 840 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 841 842 uint16_t iq_start; /* first cntxt_id */ 843 uint16_t iq_base; /* first abs_id */ 844 int eq_start; /* first cntxt_id */ 845 int eq_base; /* first abs_id */ 846 int iqmap_sz; 847 int eqmap_sz; 848 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 849 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 850 851 int8_t safe_zidx; 852 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 853 }; 854 855 struct devnames { 856 const char *nexus_name; 857 const char *ifnet_name; 858 const char *vi_ifnet_name; 859 const char *pf03_drv_name; 860 const char *vf_nexus_name; 861 const char *vf_ifnet_name; 862 }; 863 864 struct clip_entry; 865 866 struct adapter { 867 SLIST_ENTRY(adapter) link; 868 device_t dev; 869 struct cdev *cdev; 870 const struct devnames *names; 871 872 /* PCIe register resources */ 873 int regs_rid; 874 struct resource *regs_res; 875 int msix_rid; 876 struct resource *msix_res; 877 bus_space_handle_t bh; 878 bus_space_tag_t bt; 879 bus_size_t mmio_len; 880 int udbs_rid; 881 struct resource *udbs_res; 882 volatile uint8_t *udbs_base; 883 884 unsigned int pf; 885 unsigned int mbox; 886 unsigned int vpd_busy; 887 unsigned int vpd_flag; 888 889 /* Interrupt information */ 890 int intr_type; 891 int intr_count; 892 struct irq { 893 struct resource *res; 894 int rid; 895 void *tag; 896 struct sge_rxq *rxq; 897 struct sge_nm_rxq *nm_rxq; 898 } __aligned(CACHE_LINE_SIZE) *irq; 899 int sge_gts_reg; 900 int sge_kdoorbell_reg; 901 902 bus_dma_tag_t dmat; /* Parent DMA tag */ 903 904 struct sge sge; 905 int lro_timeout; 906 int sc_do_rxcopy; 907 908 int vxlan_port; 909 u_int vxlan_refcount; 910 int rawf_base; 911 int nrawf; 912 913 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 914 struct port_info *port[MAX_NPORTS]; 915 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 916 917 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 918 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 919 u_long clip_mask; 920 int clip_gen; 921 struct timeout_task clip_task; 922 923 void *tom_softc; /* (struct tom_data *) */ 924 struct tom_tunables tt; 925 struct t4_offload_policy *policy; 926 struct rwlock policy_lock; 927 928 void *iwarp_softc; /* (struct c4iw_dev *) */ 929 struct iw_tunables iwt; 930 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 931 void *ccr_softc; /* (struct ccr_softc *) */ 932 struct l2t_data *l2t; /* L2 table */ 933 struct smt_data *smt; /* Source MAC Table */ 934 struct tid_info tids; 935 vmem_t *key_map; 936 struct tls_tunables tlst; 937 938 uint8_t doorbells; 939 int offload_map; /* port_id's with IFCAP_TOE enabled */ 940 int bt_map; /* tx_chan's with BASE-T */ 941 int active_ulds; /* ULDs activated on this adapter */ 942 int flags; 943 int debug_flags; 944 int error_flags; /* Used by error handler and live reset. */ 945 946 char ifp_lockname[16]; 947 struct mtx ifp_lock; 948 struct ifnet *ifp; /* tracer ifp */ 949 struct ifmedia media; 950 int traceq; /* iq used by all tracers, -1 if none */ 951 int tracer_valid; /* bitmap of valid tracers */ 952 int tracer_enabled; /* bitmap of enabled tracers */ 953 954 char fw_version[16]; 955 char tp_version[16]; 956 char er_version[16]; 957 char bs_version[16]; 958 char cfg_file[32]; 959 u_int cfcsum; 960 struct adapter_params params; 961 const struct chip_params *chip_params; 962 struct t4_virt_res vres; 963 964 uint16_t nbmcaps; 965 uint16_t linkcaps; 966 uint16_t switchcaps; 967 uint16_t niccaps; 968 uint16_t toecaps; 969 uint16_t rdmacaps; 970 uint16_t cryptocaps; 971 uint16_t iscsicaps; 972 uint16_t fcoecaps; 973 974 struct sysctl_ctx_list ctx; 975 struct sysctl_oid *ctrlq_oid; 976 struct sysctl_oid *fwq_oid; 977 978 struct mtx sc_lock; 979 char lockname[16]; 980 981 /* Starving free lists */ 982 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 983 TAILQ_HEAD(, sge_fl) sfl; 984 struct callout sfl_callout; 985 986 /* 987 * Driver code that can run when the adapter is suspended must use this 988 * lock or a synchronized_op and check for HW_OFF_LIMITS before 989 * accessing hardware. 990 * 991 * XXX: could be changed to rwlock. wlock in suspend/resume and for 992 * indirect register access, rlock everywhere else. 993 */ 994 struct mtx reg_lock; 995 996 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 997 998 struct mtx tc_lock; 999 struct task tc_task; 1000 1001 struct task fatal_error_task; 1002 struct task reset_task; 1003 const void *reset_thread; 1004 int num_resets; 1005 int incarnation; 1006 1007 const char *last_op; 1008 const void *last_op_thr; 1009 int last_op_flags; 1010 1011 int swintr; 1012 int sensor_resets; 1013 1014 struct callout ktls_tick; 1015 }; 1016 1017 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1018 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1019 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1020 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1021 1022 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1023 KASSERT(IS_BUSY(sc) && \ 1024 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1025 ("%s: operation not synchronized.", __func__)) 1026 1027 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1028 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1029 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1030 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1031 1032 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1033 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1034 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1035 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1036 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1037 1038 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1039 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1040 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1041 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1042 1043 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1044 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1045 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1046 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1047 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1048 1049 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1050 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1051 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1052 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1053 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1054 1055 #define for_each_txq(vi, iter, q) \ 1056 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1057 iter < vi->ntxq; ++iter, ++q) 1058 #define for_each_rxq(vi, iter, q) \ 1059 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1060 iter < vi->nrxq; ++iter, ++q) 1061 #define for_each_ofld_txq(vi, iter, q) \ 1062 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1063 iter < vi->nofldtxq; ++iter, ++q) 1064 #define for_each_ofld_rxq(vi, iter, q) \ 1065 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1066 iter < vi->nofldrxq; ++iter, ++q) 1067 #define for_each_nm_txq(vi, iter, q) \ 1068 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1069 iter < vi->nnmtxq; ++iter, ++q) 1070 #define for_each_nm_rxq(vi, iter, q) \ 1071 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1072 iter < vi->nnmrxq; ++iter, ++q) 1073 #define for_each_vi(_pi, _iter, _vi) \ 1074 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1075 ++(_iter), ++(_vi)) 1076 1077 #define IDXINCR(idx, incr, wrap) do { \ 1078 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1079 } while (0) 1080 #define IDXDIFF(head, tail, wrap) \ 1081 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1082 1083 /* One for errors, one for firmware events */ 1084 #define T4_EXTRA_INTR 2 1085 1086 /* One for firmware events */ 1087 #define T4VF_EXTRA_INTR 1 1088 1089 static inline int 1090 forwarding_intr_to_fwq(struct adapter *sc) 1091 { 1092 1093 return (sc->intr_count == 1); 1094 } 1095 1096 /* Works reliably inside a sync_op or with reg_lock held. */ 1097 static inline bool 1098 hw_off_limits(struct adapter *sc) 1099 { 1100 int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1101 1102 return (__predict_false(off_limits != 0)); 1103 } 1104 1105 static inline uint32_t 1106 t4_read_reg(struct adapter *sc, uint32_t reg) 1107 { 1108 if (hw_off_limits(sc)) 1109 MPASS(curthread == sc->reset_thread); 1110 return bus_space_read_4(sc->bt, sc->bh, reg); 1111 } 1112 1113 static inline void 1114 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1115 { 1116 if (hw_off_limits(sc)) 1117 MPASS(curthread == sc->reset_thread); 1118 bus_space_write_4(sc->bt, sc->bh, reg, val); 1119 } 1120 1121 static inline uint64_t 1122 t4_read_reg64(struct adapter *sc, uint32_t reg) 1123 { 1124 if (hw_off_limits(sc)) 1125 MPASS(curthread == sc->reset_thread); 1126 #ifdef __LP64__ 1127 return bus_space_read_8(sc->bt, sc->bh, reg); 1128 #else 1129 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1130 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1131 1132 #endif 1133 } 1134 1135 static inline void 1136 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1137 { 1138 if (hw_off_limits(sc)) 1139 MPASS(curthread == sc->reset_thread); 1140 #ifdef __LP64__ 1141 bus_space_write_8(sc->bt, sc->bh, reg, val); 1142 #else 1143 bus_space_write_4(sc->bt, sc->bh, reg, val); 1144 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1145 #endif 1146 } 1147 1148 static inline void 1149 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1150 { 1151 if (hw_off_limits(sc)) 1152 MPASS(curthread == sc->reset_thread); 1153 *val = pci_read_config(sc->dev, reg, 1); 1154 } 1155 1156 static inline void 1157 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1158 { 1159 if (hw_off_limits(sc)) 1160 MPASS(curthread == sc->reset_thread); 1161 pci_write_config(sc->dev, reg, val, 1); 1162 } 1163 1164 static inline void 1165 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1166 { 1167 1168 if (hw_off_limits(sc)) 1169 MPASS(curthread == sc->reset_thread); 1170 *val = pci_read_config(sc->dev, reg, 2); 1171 } 1172 1173 static inline void 1174 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1175 { 1176 if (hw_off_limits(sc)) 1177 MPASS(curthread == sc->reset_thread); 1178 pci_write_config(sc->dev, reg, val, 2); 1179 } 1180 1181 static inline void 1182 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1183 { 1184 if (hw_off_limits(sc)) 1185 MPASS(curthread == sc->reset_thread); 1186 *val = pci_read_config(sc->dev, reg, 4); 1187 } 1188 1189 static inline void 1190 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1191 { 1192 if (hw_off_limits(sc)) 1193 MPASS(curthread == sc->reset_thread); 1194 pci_write_config(sc->dev, reg, val, 4); 1195 } 1196 1197 static inline struct port_info * 1198 adap2pinfo(struct adapter *sc, int idx) 1199 { 1200 1201 return (sc->port[idx]); 1202 } 1203 1204 static inline void 1205 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1206 { 1207 1208 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1209 } 1210 1211 static inline int 1212 tx_resume_threshold(struct sge_eq *eq) 1213 { 1214 1215 /* not quite the same as qsize / 4, but this will do. */ 1216 return (eq->sidx / 4); 1217 } 1218 1219 static inline int 1220 t4_use_ldst(struct adapter *sc) 1221 { 1222 1223 #ifdef notyet 1224 return (sc->flags & FW_OK || !sc->use_bd); 1225 #else 1226 return (0); 1227 #endif 1228 } 1229 1230 static inline void 1231 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1232 const char *msg, const __be64 *const p, const bool err) 1233 { 1234 1235 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1236 return; 1237 if (p != NULL) { 1238 log(err ? LOG_ERR : LOG_DEBUG, 1239 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1240 "%016llx %016llx %016llx %016llx\n", 1241 device_get_nameunit(sc->dev), mbox, msg, 1242 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1243 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1244 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1245 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1246 } else { 1247 log(err ? LOG_ERR : LOG_DEBUG, 1248 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1249 "%016llx %016llx %016llx %016llx\n", 1250 device_get_nameunit(sc->dev), mbox, msg, 1251 (long long)t4_read_reg64(sc, reg), 1252 (long long)t4_read_reg64(sc, reg + 8), 1253 (long long)t4_read_reg64(sc, reg + 16), 1254 (long long)t4_read_reg64(sc, reg + 24), 1255 (long long)t4_read_reg64(sc, reg + 32), 1256 (long long)t4_read_reg64(sc, reg + 40), 1257 (long long)t4_read_reg64(sc, reg + 48), 1258 (long long)t4_read_reg64(sc, reg + 56)); 1259 } 1260 } 1261 1262 /* t4_main.c */ 1263 extern int t4_ntxq; 1264 extern int t4_nrxq; 1265 extern int t4_intr_types; 1266 extern int t4_tmr_idx; 1267 extern int t4_pktc_idx; 1268 extern unsigned int t4_qsize_rxq; 1269 extern unsigned int t4_qsize_txq; 1270 extern device_method_t cxgbe_methods[]; 1271 1272 int t4_os_find_pci_capability(struct adapter *, int); 1273 int t4_os_pci_save_state(struct adapter *); 1274 int t4_os_pci_restore_state(struct adapter *); 1275 void t4_os_portmod_changed(struct port_info *); 1276 void t4_os_link_changed(struct port_info *); 1277 void t4_iterate(void (*)(struct adapter *, void *), void *); 1278 void t4_init_devnames(struct adapter *); 1279 void t4_add_adapter(struct adapter *); 1280 int t4_detach_common(device_t); 1281 int t4_map_bars_0_and_4(struct adapter *); 1282 int t4_map_bar_2(struct adapter *); 1283 int t4_setup_intr_handlers(struct adapter *); 1284 void t4_sysctls(struct adapter *); 1285 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1286 void doom_vi(struct adapter *, struct vi_info *); 1287 void end_synchronized_op(struct adapter *, int); 1288 int update_mac_settings(struct ifnet *, int); 1289 int adapter_init(struct adapter *); 1290 int vi_init(struct vi_info *); 1291 void vi_sysctls(struct vi_info *); 1292 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1293 int alloc_atid(struct adapter *, void *); 1294 void *lookup_atid(struct adapter *, int); 1295 void free_atid(struct adapter *, int); 1296 void release_tid(struct adapter *, int, struct sge_wrq *); 1297 int cxgbe_media_change(struct ifnet *); 1298 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1299 void t4_os_cim_err(struct adapter *); 1300 1301 #ifdef KERN_TLS 1302 /* t4_kern_tls.c */ 1303 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1304 struct m_snd_tag **); 1305 void t6_ktls_modload(void); 1306 void t6_ktls_modunload(void); 1307 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1308 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1309 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1310 #endif 1311 1312 /* t4_keyctx.c */ 1313 struct auth_hash; 1314 union authctx; 1315 #ifdef KERN_TLS 1316 struct ktls_session; 1317 struct tls_key_req; 1318 struct tls_keyctx; 1319 #endif 1320 1321 void t4_aes_getdeckey(void *, const void *, unsigned int); 1322 void t4_copy_partial_hash(int, union authctx *, void *); 1323 void t4_init_gmac_hash(const char *, int, char *); 1324 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1325 char *); 1326 #ifdef KERN_TLS 1327 u_int t4_tls_key_info_size(const struct ktls_session *); 1328 int t4_tls_proto_ver(const struct ktls_session *); 1329 int t4_tls_cipher_mode(const struct ktls_session *); 1330 int t4_tls_auth_mode(const struct ktls_session *); 1331 int t4_tls_hmac_ctrl(const struct ktls_session *); 1332 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1333 int t4_alloc_tls_keyid(struct adapter *); 1334 void t4_free_tls_keyid(struct adapter *, int); 1335 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1336 struct tls_key_req *); 1337 #endif 1338 1339 #ifdef DEV_NETMAP 1340 /* t4_netmap.c */ 1341 struct sge_nm_rxq; 1342 void cxgbe_nm_attach(struct vi_info *); 1343 void cxgbe_nm_detach(struct vi_info *); 1344 void service_nm_rxq(struct sge_nm_rxq *); 1345 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1346 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1347 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1348 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1349 #endif 1350 1351 /* t4_sge.c */ 1352 void t4_sge_modload(void); 1353 void t4_sge_modunload(void); 1354 uint64_t t4_sge_extfree_refs(void); 1355 void t4_tweak_chip_settings(struct adapter *); 1356 int t4_verify_chip_settings(struct adapter *); 1357 void t4_init_rx_buf_info(struct adapter *); 1358 int t4_create_dma_tag(struct adapter *); 1359 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1360 struct sysctl_oid_list *); 1361 int t4_destroy_dma_tag(struct adapter *); 1362 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1363 bus_addr_t *, void **); 1364 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1365 void *); 1366 void free_fl_buffers(struct adapter *, struct sge_fl *); 1367 int t4_setup_adapter_queues(struct adapter *); 1368 int t4_teardown_adapter_queues(struct adapter *); 1369 int t4_setup_vi_queues(struct vi_info *); 1370 int t4_teardown_vi_queues(struct vi_info *); 1371 void t4_intr_all(void *); 1372 void t4_intr(void *); 1373 #ifdef DEV_NETMAP 1374 void t4_nm_intr(void *); 1375 void t4_vi_intr(void *); 1376 #endif 1377 void t4_intr_err(void *); 1378 void t4_intr_evt(void *); 1379 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1380 void t4_update_fl_bufsize(struct ifnet *); 1381 struct mbuf *alloc_wr_mbuf(int, int); 1382 int parse_pkt(struct mbuf **, bool); 1383 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1384 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1385 int tnl_cong(struct port_info *, int); 1386 void t4_register_an_handler(an_handler_t); 1387 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1388 void t4_register_cpl_handler(int, cpl_handler_t); 1389 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1390 #ifdef RATELIMIT 1391 int ethofld_transmit(struct ifnet *, struct mbuf *); 1392 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1393 #endif 1394 1395 /* t4_tracer.c */ 1396 struct t4_tracer; 1397 void t4_tracer_modload(void); 1398 void t4_tracer_modunload(void); 1399 void t4_tracer_port_detach(struct adapter *); 1400 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1401 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1402 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1403 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1404 1405 /* t4_sched.c */ 1406 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1407 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1408 int t4_init_tx_sched(struct adapter *); 1409 int t4_free_tx_sched(struct adapter *); 1410 void t4_update_tx_sched(struct adapter *); 1411 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1412 void t4_release_cl_rl(struct adapter *, int, int); 1413 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1414 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1415 #ifdef RATELIMIT 1416 void t4_init_etid_table(struct adapter *); 1417 void t4_free_etid_table(struct adapter *); 1418 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1419 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1420 struct m_snd_tag **); 1421 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1422 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1423 #endif 1424 1425 /* t4_filter.c */ 1426 int get_filter_mode(struct adapter *, uint32_t *); 1427 int set_filter_mode(struct adapter *, uint32_t); 1428 int set_filter_mask(struct adapter *, uint32_t); 1429 int get_filter(struct adapter *, struct t4_filter *); 1430 int set_filter(struct adapter *, struct t4_filter *); 1431 int del_filter(struct adapter *, struct t4_filter *); 1432 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1433 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1434 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1435 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1436 void free_hftid_hash(struct tid_info *); 1437 1438 static inline struct wrqe * 1439 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1440 { 1441 int len = offsetof(struct wrqe, wr) + wr_len; 1442 struct wrqe *wr; 1443 1444 wr = malloc(len, M_CXGBE, M_NOWAIT); 1445 if (__predict_false(wr == NULL)) 1446 return (NULL); 1447 wr->wr_len = wr_len; 1448 wr->wrq = wrq; 1449 return (wr); 1450 } 1451 1452 static inline void * 1453 wrtod(struct wrqe *wr) 1454 { 1455 return (&wr->wr[0]); 1456 } 1457 1458 static inline void 1459 free_wrqe(struct wrqe *wr) 1460 { 1461 free(wr, M_CXGBE); 1462 } 1463 1464 static inline void 1465 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1466 { 1467 struct sge_wrq *wrq = wr->wrq; 1468 1469 TXQ_LOCK(wrq); 1470 t4_wrq_tx_locked(sc, wrq, wr); 1471 TXQ_UNLOCK(wrq); 1472 } 1473 1474 static inline int 1475 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1476 int len) 1477 { 1478 1479 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1480 } 1481 1482 static inline int 1483 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1484 const uint32_t *val, int len) 1485 { 1486 1487 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1488 } 1489 1490 /* Number of len16 -> number of descriptors */ 1491 static inline int 1492 tx_len16_to_desc(int len16) 1493 { 1494 1495 return (howmany(len16, EQ_ESIZE / 16)); 1496 } 1497 #endif 1498