1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "firmware/t4fw_interface.h" 58 59 MALLOC_DECLARE(M_CXGBE); 60 #define CXGBE_UNIMPLEMENTED(s) \ 61 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 62 63 #if defined(__i386__) || defined(__amd64__) 64 static __inline void 65 prefetch(void *x) 66 { 67 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 68 } 69 #else 70 #define prefetch(x) 71 #endif 72 73 #ifndef SYSCTL_ADD_UQUAD 74 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 75 #define sysctl_handle_64 sysctl_handle_quad 76 #define CTLTYPE_U64 CTLTYPE_QUAD 77 #endif 78 79 #if (__FreeBSD_version >= 900030) || \ 80 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 81 #define SBUF_DRAIN 1 82 #endif 83 84 #ifdef __amd64__ 85 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 86 static __inline uint64_t 87 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 88 bus_size_t offset) 89 { 90 KASSERT(tag == X86_BUS_SPACE_MEM, 91 ("%s: can only handle mem space", __func__)); 92 93 return (*(volatile uint64_t *)(handle + offset)); 94 } 95 96 static __inline void 97 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 98 bus_size_t offset, uint64_t value) 99 { 100 KASSERT(tag == X86_BUS_SPACE_MEM, 101 ("%s: can only handle mem space", __func__)); 102 103 *(volatile uint64_t *)(bsh + offset) = value; 104 } 105 #else 106 static __inline uint64_t 107 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 108 bus_size_t offset) 109 { 110 return (uint64_t)bus_space_read_4(tag, handle, offset) + 111 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 112 } 113 114 static __inline void 115 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 116 bus_size_t offset, uint64_t value) 117 { 118 bus_space_write_4(tag, bsh, offset, value); 119 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 120 } 121 #endif 122 123 struct adapter; 124 typedef struct adapter adapter_t; 125 126 enum { 127 FW_IQ_QSIZE = 256, 128 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 129 130 RX_IQ_QSIZE = 1024, 131 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 132 133 EQ_ESIZE = 64, /* All egress queues use this entry size */ 134 135 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 136 #if MJUMPAGESIZE != MCLBYTES 137 FL_BUF_SIZES_MAX = 5, /* cluster, jumbop, jumbo9k, jumbo16k, extra */ 138 #else 139 FL_BUF_SIZES_MAX = 4, /* cluster, jumbo9k, jumbo16k, extra */ 140 #endif 141 142 CTRL_EQ_QSIZE = 128, 143 144 TX_EQ_QSIZE = 1024, 145 TX_SGL_SEGS = 36, 146 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 147 }; 148 149 enum { 150 /* adapter intr_type */ 151 INTR_INTX = (1 << 0), 152 INTR_MSI = (1 << 1), 153 INTR_MSIX = (1 << 2) 154 }; 155 156 enum { 157 /* flags understood by begin_synchronized_op */ 158 HOLD_LOCK = (1 << 0), 159 SLEEP_OK = (1 << 1), 160 INTR_OK = (1 << 2), 161 162 /* flags understood by end_synchronized_op */ 163 LOCK_HELD = HOLD_LOCK, 164 }; 165 166 enum { 167 /* adapter flags */ 168 FULL_INIT_DONE = (1 << 0), 169 FW_OK = (1 << 1), 170 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 171 MASTER_PF = (1 << 3), 172 ADAP_SYSCTL_CTX = (1 << 4), 173 TOM_INIT_DONE = (1 << 5), 174 BUF_PACKING_OK = (1 << 6), 175 176 CXGBE_BUSY = (1 << 9), 177 178 /* port flags */ 179 DOOMED = (1 << 0), 180 PORT_INIT_DONE = (1 << 1), 181 PORT_SYSCTL_CTX = (1 << 2), 182 HAS_TRACEQ = (1 << 3), 183 }; 184 185 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 186 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 187 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 188 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 189 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 190 191 struct port_info { 192 device_t dev; 193 struct adapter *adapter; 194 195 struct ifnet *ifp; 196 struct ifmedia media; 197 198 struct mtx pi_lock; 199 char lockname[16]; 200 unsigned long flags; 201 int if_flags; 202 203 uint16_t *rss; 204 uint16_t viid; 205 int16_t xact_addr_filt;/* index of exact MAC address filter */ 206 uint16_t rss_size; /* size of VI's RSS table slice */ 207 uint8_t lport; /* associated offload logical port */ 208 int8_t mdio_addr; 209 uint8_t port_type; 210 uint8_t mod_type; 211 uint8_t port_id; 212 uint8_t tx_chan; 213 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 214 215 /* These need to be int as they are used in sysctl */ 216 int ntxq; /* # of tx queues */ 217 int first_txq; /* index of first tx queue */ 218 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 219 int nrxq; /* # of rx queues */ 220 int first_rxq; /* index of first rx queue */ 221 #ifdef TCP_OFFLOAD 222 int nofldtxq; /* # of offload tx queues */ 223 int first_ofld_txq; /* index of first offload tx queue */ 224 int nofldrxq; /* # of offload rx queues */ 225 int first_ofld_rxq; /* index of first offload rx queue */ 226 #endif 227 int tmr_idx; 228 int pktc_idx; 229 int qsize_rxq; 230 int qsize_txq; 231 232 int linkdnrc; 233 struct link_config link_cfg; 234 struct port_stats stats; 235 236 eventhandler_tag vlan_c; 237 238 struct callout tick; 239 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 240 241 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 242 }; 243 244 struct fl_sdesc { 245 bus_dmamap_t map; 246 caddr_t cl; 247 uint8_t tag_idx; /* the fl->tag entry this map comes from */ 248 #ifdef INVARIANTS 249 __be64 ba_hwtag; 250 #endif 251 }; 252 253 struct tx_desc { 254 __be64 flit[8]; 255 }; 256 257 struct tx_map { 258 struct mbuf *m; 259 bus_dmamap_t map; 260 }; 261 262 /* DMA maps used for tx */ 263 struct tx_maps { 264 struct tx_map *maps; 265 uint32_t map_total; /* # of DMA maps */ 266 uint32_t map_pidx; /* next map to be used */ 267 uint32_t map_cidx; /* reclaimed up to this index */ 268 uint32_t map_avail; /* # of available maps */ 269 }; 270 271 struct tx_sdesc { 272 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 273 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 274 }; 275 276 enum { 277 /* iq flags */ 278 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 279 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 280 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 281 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 282 283 /* iq state */ 284 IQS_DISABLED = 0, 285 IQS_BUSY = 1, 286 IQS_IDLE = 2, 287 }; 288 289 /* 290 * Ingress Queue: T4 is producer, driver is consumer. 291 */ 292 struct sge_iq { 293 bus_dma_tag_t desc_tag; 294 bus_dmamap_t desc_map; 295 bus_addr_t ba; /* bus address of descriptor ring */ 296 uint32_t flags; 297 uint16_t abs_id; /* absolute SGE id for the iq */ 298 int8_t intr_pktc_idx; /* packet count threshold index */ 299 int8_t pad0; 300 __be64 *desc; /* KVA of descriptor ring */ 301 302 volatile int state; 303 struct adapter *adapter; 304 const __be64 *cdesc; /* current descriptor */ 305 uint8_t gen; /* generation bit */ 306 uint8_t intr_params; /* interrupt holdoff parameters */ 307 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 308 uint8_t esize; /* size (bytes) of each entry in the queue */ 309 uint16_t qsize; /* size (# of entries) of the queue */ 310 uint16_t cidx; /* consumer index */ 311 uint16_t cntxt_id; /* SGE context id for the iq */ 312 313 STAILQ_ENTRY(sge_iq) link; 314 }; 315 316 enum { 317 EQ_CTRL = 1, 318 EQ_ETH = 2, 319 #ifdef TCP_OFFLOAD 320 EQ_OFLD = 3, 321 #endif 322 323 /* eq flags */ 324 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 325 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 326 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 327 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 328 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 329 }; 330 331 /* Listed in order of preference. Update t4_sysctls too if you change these */ 332 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 333 334 /* 335 * Egress Queue: driver is producer, T4 is consumer. 336 * 337 * Note: A free list is an egress queue (driver produces the buffers and T4 338 * consumes them) but it's special enough to have its own struct (see sge_fl). 339 */ 340 struct sge_eq { 341 unsigned int flags; /* MUST be first */ 342 unsigned int cntxt_id; /* SGE context id for the eq */ 343 bus_dma_tag_t desc_tag; 344 bus_dmamap_t desc_map; 345 char lockname[16]; 346 struct mtx eq_lock; 347 348 struct tx_desc *desc; /* KVA of descriptor ring */ 349 bus_addr_t ba; /* bus address of descriptor ring */ 350 struct sge_qstat *spg; /* status page, for convenience */ 351 int doorbells; 352 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 353 u_int udb_qid; /* relative qid within the doorbell page */ 354 uint16_t cap; /* max # of desc, for convenience */ 355 uint16_t avail; /* available descriptors, for convenience */ 356 uint16_t qsize; /* size (# of entries) of the queue */ 357 uint16_t cidx; /* consumer idx (desc idx) */ 358 uint16_t pidx; /* producer idx (desc idx) */ 359 uint16_t pending; /* # of descriptors used since last doorbell */ 360 uint16_t iqid; /* iq that gets egr_update for the eq */ 361 uint8_t tx_chan; /* tx channel used by the eq */ 362 struct task tx_task; 363 struct callout tx_callout; 364 365 /* stats */ 366 367 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 368 uint32_t unstalled; /* recovered from stall */ 369 }; 370 371 struct fl_buf_info { 372 u_int size; 373 int type; 374 int hwtag:4; /* tag in low 4 bits of the pa. */ 375 uma_zone_t zone; 376 }; 377 #define FL_BUF_SIZES(sc) (sc->sge.fl_buf_sizes) 378 #define FL_BUF_SIZE(sc, x) (sc->sge.fl_buf_info[x].size) 379 #define FL_BUF_TYPE(sc, x) (sc->sge.fl_buf_info[x].type) 380 #define FL_BUF_HWTAG(sc, x) (sc->sge.fl_buf_info[x].hwtag) 381 #define FL_BUF_ZONE(sc, x) (sc->sge.fl_buf_info[x].zone) 382 383 enum { 384 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 385 FL_DOOMED = (1 << 1), /* about to be destroyed */ 386 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 387 }; 388 389 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 390 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 391 392 struct sge_fl { 393 bus_dma_tag_t desc_tag; 394 bus_dmamap_t desc_map; 395 bus_dma_tag_t tag[FL_BUF_SIZES_MAX]; /* only first FL_BUF_SIZES(sc) are 396 valid */ 397 uint8_t tag_idx; 398 struct mtx fl_lock; 399 char lockname[16]; 400 int flags; 401 402 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 403 bus_addr_t ba; /* bus address of descriptor ring */ 404 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 405 uint32_t cap; /* max # of buffers, for convenience */ 406 uint16_t qsize; /* size (# of entries) of the queue */ 407 uint16_t cntxt_id; /* SGE context id for the freelist */ 408 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 409 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 410 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 411 uint32_t needed; /* # of buffers needed to fill up fl. */ 412 uint32_t lowat; /* # of buffers <= this means fl needs help */ 413 uint32_t pending; /* # of bufs allocated since last doorbell */ 414 u_int dmamap_failed; 415 struct mbuf *mstash[8]; 416 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 417 }; 418 419 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 420 struct sge_txq { 421 struct sge_eq eq; /* MUST be first */ 422 423 struct ifnet *ifp; /* the interface this txq belongs to */ 424 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 425 struct buf_ring *br; /* tx buffer ring */ 426 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 427 struct mbuf *m; /* held up due to temporary resource shortage */ 428 429 struct tx_maps txmaps; 430 431 /* stats for common events first */ 432 433 uint64_t txcsum; /* # of times hardware assisted with checksum */ 434 uint64_t tso_wrs; /* # of TSO work requests */ 435 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 436 uint64_t imm_wrs; /* # of work requests with immediate data */ 437 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 438 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 439 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 440 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 441 442 /* stats for not-that-common events */ 443 444 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 445 uint32_t no_desc; /* out of hardware descriptors */ 446 } __aligned(CACHE_LINE_SIZE); 447 448 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 449 struct sge_rxq { 450 struct sge_iq iq; /* MUST be first */ 451 struct sge_fl fl; /* MUST follow iq */ 452 453 struct ifnet *ifp; /* the interface this rxq belongs to */ 454 #if defined(INET) || defined(INET6) 455 struct lro_ctrl lro; /* LRO state */ 456 #endif 457 458 /* stats for common events first */ 459 460 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 461 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 462 463 /* stats for not-that-common events */ 464 465 } __aligned(CACHE_LINE_SIZE); 466 467 static inline struct sge_rxq * 468 iq_to_rxq(struct sge_iq *iq) 469 { 470 471 return (__containerof(iq, struct sge_rxq, iq)); 472 } 473 474 475 #ifdef TCP_OFFLOAD 476 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 477 struct sge_ofld_rxq { 478 struct sge_iq iq; /* MUST be first */ 479 struct sge_fl fl; /* MUST follow iq */ 480 } __aligned(CACHE_LINE_SIZE); 481 482 static inline struct sge_ofld_rxq * 483 iq_to_ofld_rxq(struct sge_iq *iq) 484 { 485 486 return (__containerof(iq, struct sge_ofld_rxq, iq)); 487 } 488 #endif 489 490 struct wrqe { 491 STAILQ_ENTRY(wrqe) link; 492 struct sge_wrq *wrq; 493 int wr_len; 494 uint64_t wr[] __aligned(16); 495 }; 496 497 /* 498 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 499 * and offload tx queues are of this type. 500 */ 501 struct sge_wrq { 502 struct sge_eq eq; /* MUST be first */ 503 504 struct adapter *adapter; 505 506 /* List of WRs held up due to lack of tx descriptors */ 507 STAILQ_HEAD(, wrqe) wr_list; 508 509 /* stats for common events first */ 510 511 uint64_t tx_wrs; /* # of tx work requests */ 512 513 /* stats for not-that-common events */ 514 515 uint32_t no_desc; /* out of hardware descriptors */ 516 } __aligned(CACHE_LINE_SIZE); 517 518 struct sge { 519 int timer_val[SGE_NTIMERS]; 520 int counter_val[SGE_NCOUNTERS]; 521 int fl_starve_threshold; 522 int fl_starve_threshold2; 523 int eq_s_qpp; 524 int iq_s_qpp; 525 526 int nrxq; /* total # of Ethernet rx queues */ 527 int ntxq; /* total # of Ethernet tx tx queues */ 528 #ifdef TCP_OFFLOAD 529 int nofldrxq; /* total # of TOE rx queues */ 530 int nofldtxq; /* total # of TOE tx queues */ 531 #endif 532 int niq; /* total # of ingress queues */ 533 int neq; /* total # of egress queues */ 534 535 struct sge_iq fwq; /* Firmware event queue */ 536 struct sge_wrq mgmtq; /* Management queue (control queue) */ 537 struct sge_wrq *ctrlq; /* Control queues */ 538 struct sge_txq *txq; /* NIC tx queues */ 539 struct sge_rxq *rxq; /* NIC rx queues */ 540 #ifdef TCP_OFFLOAD 541 struct sge_wrq *ofld_txq; /* TOE tx queues */ 542 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 543 #endif 544 545 uint16_t iq_start; 546 int eq_start; 547 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 548 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 549 550 u_int fl_buf_sizes __aligned(CACHE_LINE_SIZE); 551 struct fl_buf_info fl_buf_info[FL_BUF_SIZES_MAX]; 552 }; 553 554 struct rss_header; 555 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 556 struct mbuf *); 557 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 558 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 559 560 struct adapter { 561 SLIST_ENTRY(adapter) link; 562 device_t dev; 563 struct cdev *cdev; 564 565 /* PCIe register resources */ 566 int regs_rid; 567 struct resource *regs_res; 568 int msix_rid; 569 struct resource *msix_res; 570 bus_space_handle_t bh; 571 bus_space_tag_t bt; 572 bus_size_t mmio_len; 573 int udbs_rid; 574 struct resource *udbs_res; 575 volatile uint8_t *udbs_base; 576 577 unsigned int pf; 578 unsigned int mbox; 579 580 /* Interrupt information */ 581 int intr_type; 582 int intr_count; 583 struct irq { 584 struct resource *res; 585 int rid; 586 void *tag; 587 } *irq; 588 589 bus_dma_tag_t dmat; /* Parent DMA tag */ 590 591 struct sge sge; 592 int lro_timeout; 593 594 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 595 struct port_info *port[MAX_NPORTS]; 596 uint8_t chan_map[NCHAN]; 597 598 #ifdef TCP_OFFLOAD 599 void *tom_softc; /* (struct tom_data *) */ 600 struct tom_tunables tt; 601 void *iwarp_softc; /* (struct c4iw_dev *) */ 602 #endif 603 struct l2t_data *l2t; /* L2 table */ 604 struct tid_info tids; 605 606 int doorbells; 607 int open_device_map; 608 #ifdef TCP_OFFLOAD 609 int offload_map; 610 #endif 611 int flags; 612 613 char ifp_lockname[16]; 614 struct mtx ifp_lock; 615 struct ifnet *ifp; /* tracer ifp */ 616 struct ifmedia media; 617 int traceq; /* iq used by all tracers, -1 if none */ 618 int tracer_valid; /* bitmap of valid tracers */ 619 int tracer_enabled; /* bitmap of enabled tracers */ 620 621 char fw_version[32]; 622 char cfg_file[32]; 623 u_int cfcsum; 624 struct adapter_params params; 625 struct t4_virt_res vres; 626 627 uint16_t linkcaps; 628 uint16_t niccaps; 629 uint16_t toecaps; 630 uint16_t rdmacaps; 631 uint16_t iscsicaps; 632 uint16_t fcoecaps; 633 634 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 635 636 struct mtx sc_lock; 637 char lockname[16]; 638 639 /* Starving free lists */ 640 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 641 TAILQ_HEAD(, sge_fl) sfl; 642 struct callout sfl_callout; 643 644 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 645 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 646 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 647 648 #ifdef INVARIANTS 649 const char *last_op; 650 const void *last_op_thr; 651 #endif 652 653 int sc_do_rxcopy; 654 }; 655 656 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 657 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 658 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 659 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 660 661 /* XXX: not bulletproof, but much better than nothing */ 662 #define ASSERT_SYNCHRONIZED_OP(sc) \ 663 KASSERT(IS_BUSY(sc) && \ 664 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 665 ("%s: operation not synchronized.", __func__)) 666 667 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 668 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 669 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 670 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 671 672 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 673 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 674 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 675 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 676 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 677 678 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 679 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 680 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 681 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 682 683 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 684 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 685 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 686 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 687 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 688 689 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 690 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 691 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 692 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 693 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 694 695 #define for_each_txq(pi, iter, q) \ 696 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 697 iter < pi->ntxq; ++iter, ++q) 698 #define for_each_rxq(pi, iter, q) \ 699 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 700 iter < pi->nrxq; ++iter, ++q) 701 #define for_each_ofld_txq(pi, iter, q) \ 702 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 703 iter < pi->nofldtxq; ++iter, ++q) 704 #define for_each_ofld_rxq(pi, iter, q) \ 705 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 706 iter < pi->nofldrxq; ++iter, ++q) 707 708 /* One for errors, one for firmware events */ 709 #define T4_EXTRA_INTR 2 710 711 static inline uint32_t 712 t4_read_reg(struct adapter *sc, uint32_t reg) 713 { 714 715 return bus_space_read_4(sc->bt, sc->bh, reg); 716 } 717 718 static inline void 719 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 720 { 721 722 bus_space_write_4(sc->bt, sc->bh, reg, val); 723 } 724 725 static inline uint64_t 726 t4_read_reg64(struct adapter *sc, uint32_t reg) 727 { 728 729 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 730 } 731 732 static inline void 733 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 734 { 735 736 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 737 } 738 739 static inline void 740 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 741 { 742 743 *val = pci_read_config(sc->dev, reg, 1); 744 } 745 746 static inline void 747 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 748 { 749 750 pci_write_config(sc->dev, reg, val, 1); 751 } 752 753 static inline void 754 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 755 { 756 757 *val = pci_read_config(sc->dev, reg, 2); 758 } 759 760 static inline void 761 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 762 { 763 764 pci_write_config(sc->dev, reg, val, 2); 765 } 766 767 static inline void 768 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 769 { 770 771 *val = pci_read_config(sc->dev, reg, 4); 772 } 773 774 static inline void 775 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 776 { 777 778 pci_write_config(sc->dev, reg, val, 4); 779 } 780 781 static inline struct port_info * 782 adap2pinfo(struct adapter *sc, int idx) 783 { 784 785 return (sc->port[idx]); 786 } 787 788 static inline void 789 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 790 { 791 792 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 793 } 794 795 static inline bool 796 is_10G_port(const struct port_info *pi) 797 { 798 799 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 800 } 801 802 static inline bool 803 is_40G_port(const struct port_info *pi) 804 { 805 806 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 807 } 808 809 static inline int 810 tx_resume_threshold(struct sge_eq *eq) 811 { 812 813 return (eq->qsize / 4); 814 } 815 816 /* t4_main.c */ 817 void t4_tx_task(void *, int); 818 void t4_tx_callout(void *); 819 int t4_os_find_pci_capability(struct adapter *, int); 820 int t4_os_pci_save_state(struct adapter *); 821 int t4_os_pci_restore_state(struct adapter *); 822 void t4_os_portmod_changed(const struct adapter *, int); 823 void t4_os_link_changed(struct adapter *, int, int, int); 824 void t4_iterate(void (*)(struct adapter *, void *), void *); 825 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 826 int t4_register_an_handler(struct adapter *, an_handler_t); 827 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 828 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 829 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 830 void end_synchronized_op(struct adapter *, int); 831 832 /* t4_sge.c */ 833 void t4_sge_modload(void); 834 void t4_init_sge_cpl_handlers(struct adapter *); 835 void t4_tweak_chip_settings(struct adapter *); 836 int t4_read_chip_settings(struct adapter *); 837 int t4_create_dma_tag(struct adapter *); 838 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 839 struct sysctl_oid_list *); 840 int t4_destroy_dma_tag(struct adapter *); 841 int t4_setup_adapter_queues(struct adapter *); 842 int t4_teardown_adapter_queues(struct adapter *); 843 int t4_setup_port_queues(struct port_info *); 844 int t4_teardown_port_queues(struct port_info *); 845 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 846 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 847 void t4_intr_all(void *); 848 void t4_intr(void *); 849 void t4_intr_err(void *); 850 void t4_intr_evt(void *); 851 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 852 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 853 void t4_update_fl_bufsize(struct ifnet *); 854 int can_resume_tx(struct sge_eq *); 855 856 /* t4_tracer.c */ 857 struct t4_tracer; 858 void t4_tracer_modload(void); 859 void t4_tracer_modunload(void); 860 void t4_tracer_port_detach(struct adapter *); 861 int t4_get_tracer(struct adapter *, struct t4_tracer *); 862 int t4_set_tracer(struct adapter *, struct t4_tracer *); 863 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 864 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 865 866 static inline struct wrqe * 867 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 868 { 869 int len = offsetof(struct wrqe, wr) + wr_len; 870 struct wrqe *wr; 871 872 wr = malloc(len, M_CXGBE, M_NOWAIT); 873 if (__predict_false(wr == NULL)) 874 return (NULL); 875 wr->wr_len = wr_len; 876 wr->wrq = wrq; 877 return (wr); 878 } 879 880 static inline void * 881 wrtod(struct wrqe *wr) 882 { 883 return (&wr->wr[0]); 884 } 885 886 static inline void 887 free_wrqe(struct wrqe *wr) 888 { 889 free(wr, M_CXGBE); 890 } 891 892 static inline void 893 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 894 { 895 struct sge_wrq *wrq = wr->wrq; 896 897 TXQ_LOCK(wrq); 898 t4_wrq_tx_locked(sc, wrq, wr); 899 TXQ_UNLOCK(wrq); 900 } 901 902 #endif 903