1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_media.h> 58 #include <net/pfil.h> 59 #include <netinet/in.h> 60 #include <netinet/tcp_lro.h> 61 62 #include "offload.h" 63 #include "t4_ioctl.h" 64 #include "common/t4_msg.h" 65 #include "firmware/t4fw_interface.h" 66 67 #define KTR_CXGBE KTR_SPARE3 68 MALLOC_DECLARE(M_CXGBE); 69 #define CXGBE_UNIMPLEMENTED(s) \ 70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 71 72 /* 73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 74 * LIST_HEAD when building iw_cxgbe. 75 */ 76 #define CXGBE_LIST_HEAD(name, type) \ 77 struct name { \ 78 struct type *lh_first; /* first element */ \ 79 } 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 ADAP_SYSCTL_CTX = (1 << 4), 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 167 CXGBE_BUSY = (1 << 9), 168 HW_OFF_LIMITS = (1 << 10), /* off limits to all except reset_thread */ 169 170 /* port flags */ 171 HAS_TRACEQ = (1 << 3), 172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 173 174 /* VI flags */ 175 DOOMED = (1 << 0), 176 VI_INIT_DONE = (1 << 1), 177 VI_SYSCTL_CTX = (1 << 2), 178 TX_USES_VM_WR = (1 << 3), 179 VI_SKIP_STATS = (1 << 4), 180 181 /* adapter debug_flags */ 182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 187 }; 188 189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 194 195 struct vi_info { 196 device_t dev; 197 struct port_info *pi; 198 struct adapter *adapter; 199 200 struct ifnet *ifp; 201 struct pfil_head *pfil; 202 203 unsigned long flags; 204 int if_flags; 205 206 uint16_t *rss, *nm_rss; 207 uint16_t viid; /* opaque VI identifier */ 208 uint16_t smt_idx; 209 uint16_t vin; 210 uint8_t vfvld; 211 int16_t xact_addr_filt;/* index of exact MAC address filter */ 212 uint16_t rss_size; /* size of VI's RSS table slice */ 213 uint16_t rss_base; /* start of VI's RSS table slice */ 214 int hashen; 215 216 int nintr; 217 int first_intr; 218 219 /* These need to be int as they are used in sysctl */ 220 int ntxq; /* # of tx queues */ 221 int first_txq; /* index of first tx queue */ 222 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 223 int nrxq; /* # of rx queues */ 224 int first_rxq; /* index of first rx queue */ 225 int nofldtxq; /* # of offload tx queues */ 226 int first_ofld_txq; /* index of first offload tx queue */ 227 int nofldrxq; /* # of offload rx queues */ 228 int first_ofld_rxq; /* index of first offload rx queue */ 229 int nnmtxq; 230 int first_nm_txq; 231 int nnmrxq; 232 int first_nm_rxq; 233 int tmr_idx; 234 int ofld_tmr_idx; 235 int pktc_idx; 236 int ofld_pktc_idx; 237 int qsize_rxq; 238 int qsize_txq; 239 240 struct timeval last_refreshed; 241 struct fw_vi_stats_vf stats; 242 struct mtx tick_mtx; 243 struct callout tick; 244 245 struct sysctl_ctx_list ctx; 246 struct sysctl_oid *rxq_oid; 247 struct sysctl_oid *txq_oid; 248 struct sysctl_oid *nm_rxq_oid; 249 struct sysctl_oid *nm_txq_oid; 250 struct sysctl_oid *ofld_rxq_oid; 251 struct sysctl_oid *ofld_txq_oid; 252 253 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 254 }; 255 256 struct tx_ch_rl_params { 257 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 258 uint32_t maxrate; 259 }; 260 261 enum { 262 CLRL_USER = (1 << 0), /* allocated manually. */ 263 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 264 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 265 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 266 }; 267 268 struct tx_cl_rl_params { 269 int refcount; 270 uint8_t flags; 271 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 272 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 273 enum fw_sched_params_mode mode; /* aggr or per-flow */ 274 uint32_t maxrate; 275 uint16_t pktsize; 276 uint16_t burstsize; 277 }; 278 279 /* Tx scheduler parameters for a channel/port */ 280 struct tx_sched_params { 281 /* Channel Rate Limiter */ 282 struct tx_ch_rl_params ch_rl; 283 284 /* Class WRR */ 285 /* XXX */ 286 287 /* Class Rate Limiter (including the default pktsize and burstsize). */ 288 int pktsize; 289 int burstsize; 290 struct tx_cl_rl_params cl_rl[]; 291 }; 292 293 struct port_info { 294 device_t dev; 295 struct adapter *adapter; 296 297 struct vi_info *vi; 298 int nvi; 299 int up_vis; 300 int uld_vis; 301 bool vxlan_tcam_entry; 302 303 struct tx_sched_params *sched_params; 304 305 struct mtx pi_lock; 306 char lockname[16]; 307 unsigned long flags; 308 309 uint8_t lport; /* associated offload logical port */ 310 int8_t mdio_addr; 311 uint8_t port_type; 312 uint8_t mod_type; 313 uint8_t port_id; 314 uint8_t tx_chan; 315 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 316 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 317 uint8_t rx_c_chan; /* rx TP c-channel */ 318 319 struct link_config link_cfg; 320 struct ifmedia media; 321 322 struct port_stats stats; 323 u_int tnl_cong_drops; 324 u_int tx_parse_error; 325 int fcs_reg; 326 uint64_t fcs_base; 327 }; 328 329 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 330 331 struct cluster_metadata { 332 uma_zone_t zone; 333 caddr_t cl; 334 u_int refcount; 335 }; 336 337 struct fl_sdesc { 338 caddr_t cl; 339 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 340 int16_t moff; /* offset of metadata from cl */ 341 uint8_t zidx; 342 }; 343 344 struct tx_desc { 345 __be64 flit[8]; 346 }; 347 348 struct tx_sdesc { 349 struct mbuf *m; /* m_nextpkt linked chain of frames */ 350 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 351 }; 352 353 354 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 355 struct iq_desc { 356 struct rss_header rss; 357 uint8_t cpl[IQ_PAD]; 358 struct rsp_ctrl rsp; 359 }; 360 #undef IQ_PAD 361 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 362 363 enum { 364 /* iq flags */ 365 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 366 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 367 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 368 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 369 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 370 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 371 372 /* iq state */ 373 IQS_DISABLED = 0, 374 IQS_BUSY = 1, 375 IQS_IDLE = 2, 376 377 /* netmap related flags */ 378 NM_OFF = 0, 379 NM_ON = 1, 380 NM_BUSY = 2, 381 }; 382 383 enum { 384 CPL_COOKIE_RESERVED = 0, 385 CPL_COOKIE_FILTER, 386 CPL_COOKIE_DDP0, 387 CPL_COOKIE_DDP1, 388 CPL_COOKIE_TOM, 389 CPL_COOKIE_HASHFILTER, 390 CPL_COOKIE_ETHOFLD, 391 CPL_COOKIE_KERN_TLS, 392 393 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 394 }; 395 396 struct sge_iq; 397 struct rss_header; 398 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 399 struct mbuf *); 400 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 401 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 402 403 /* 404 * Ingress Queue: T4 is producer, driver is consumer. 405 */ 406 struct sge_iq { 407 uint32_t flags; 408 volatile int state; 409 struct adapter *adapter; 410 struct iq_desc *desc; /* KVA of descriptor ring */ 411 int8_t intr_pktc_idx; /* packet count threshold index */ 412 uint8_t gen; /* generation bit */ 413 uint8_t intr_params; /* interrupt holdoff parameters */ 414 int8_t cong; /* congestion settings */ 415 uint16_t qsize; /* size (# of entries) of the queue */ 416 uint16_t sidx; /* index of the entry with the status page */ 417 uint16_t cidx; /* consumer index */ 418 uint16_t cntxt_id; /* SGE context id for the iq */ 419 uint16_t abs_id; /* absolute SGE id for the iq */ 420 int16_t intr_idx; /* interrupt used by the queue */ 421 422 STAILQ_ENTRY(sge_iq) link; 423 424 bus_dma_tag_t desc_tag; 425 bus_dmamap_t desc_map; 426 bus_addr_t ba; /* bus address of descriptor ring */ 427 }; 428 429 enum { 430 /* eq type */ 431 EQ_CTRL = 1, 432 EQ_ETH = 2, 433 EQ_OFLD = 3, 434 435 /* eq flags */ 436 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 437 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 438 EQ_ENABLED = (1 << 3), /* open for business */ 439 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 440 }; 441 442 /* Listed in order of preference. Update t4_sysctls too if you change these */ 443 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 444 445 /* 446 * Egress Queue: driver is producer, T4 is consumer. 447 * 448 * Note: A free list is an egress queue (driver produces the buffers and T4 449 * consumes them) but it's special enough to have its own struct (see sge_fl). 450 */ 451 struct sge_eq { 452 unsigned int flags; /* MUST be first */ 453 unsigned int cntxt_id; /* SGE context id for the eq */ 454 unsigned int abs_id; /* absolute SGE id for the eq */ 455 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 456 uint8_t doorbells; 457 uint8_t tx_chan; /* tx channel used by the eq */ 458 struct mtx eq_lock; 459 460 struct tx_desc *desc; /* KVA of descriptor ring */ 461 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 462 u_int udb_qid; /* relative qid within the doorbell page */ 463 uint16_t sidx; /* index of the entry with the status page */ 464 uint16_t cidx; /* consumer idx (desc idx) */ 465 uint16_t pidx; /* producer idx (desc idx) */ 466 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 467 uint16_t dbidx; /* pidx of the most recent doorbell */ 468 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 469 volatile u_int equiq; /* EQUIQ outstanding */ 470 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 471 472 bus_dma_tag_t desc_tag; 473 bus_dmamap_t desc_map; 474 bus_addr_t ba; /* bus address of descriptor ring */ 475 char lockname[16]; 476 }; 477 478 struct rx_buf_info { 479 uma_zone_t zone; /* zone that this cluster comes from */ 480 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 481 * hwsize[hwidx1] = size1. No spare. */ 482 uint16_t size2; /* hwsize[hwidx2] = size2. 483 * spare in cluster = size1 - size2. */ 484 int8_t hwidx1; /* SGE bufsize idx for size1 */ 485 int8_t hwidx2; /* SGE bufsize idx for size2 */ 486 uint8_t type; /* EXT_xxx type of the cluster */ 487 }; 488 489 enum { 490 NUM_MEMWIN = 3, 491 492 MEMWIN0_APERTURE = 2048, 493 MEMWIN0_BASE = 0x1b800, 494 495 MEMWIN1_APERTURE = 32768, 496 MEMWIN1_BASE = 0x28000, 497 498 MEMWIN2_APERTURE_T4 = 65536, 499 MEMWIN2_BASE_T4 = 0x30000, 500 501 MEMWIN2_APERTURE_T5 = 128 * 1024, 502 MEMWIN2_BASE_T5 = 0x60000, 503 }; 504 505 struct memwin { 506 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 507 uint32_t mw_base; /* constant after setup_memwin */ 508 uint32_t mw_aperture; /* ditto */ 509 uint32_t mw_curpos; /* protected by mw_lock */ 510 }; 511 512 enum { 513 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 514 FL_DOOMED = (1 << 1), /* about to be destroyed */ 515 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 516 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 517 }; 518 519 #define FL_RUNNING_LOW(fl) \ 520 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 521 #define FL_NOT_RUNNING_LOW(fl) \ 522 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 523 524 struct sge_fl { 525 struct mtx fl_lock; 526 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 527 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 528 uint16_t zidx; /* refill zone idx */ 529 uint16_t safe_zidx; 530 uint16_t lowat; /* # of buffers <= this means fl needs help */ 531 int flags; 532 uint16_t buf_boundary; 533 534 /* The 16b idx all deal with hw descriptors */ 535 uint16_t dbidx; /* hw pidx after last doorbell */ 536 uint16_t sidx; /* index of status page */ 537 volatile uint16_t hw_cidx; 538 539 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 540 uint32_t cidx; /* consumer index */ 541 uint32_t pidx; /* producer index */ 542 543 uint32_t dbval; 544 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 545 volatile uint32_t *udb; 546 547 uint64_t cl_allocated; /* # of clusters allocated */ 548 uint64_t cl_recycled; /* # of clusters recycled */ 549 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 550 551 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 552 struct mbuf *m0; 553 struct mbuf **pnext; 554 u_int remaining; 555 556 uint16_t qsize; /* # of hw descriptors (status page included) */ 557 uint16_t cntxt_id; /* SGE context id for the freelist */ 558 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 559 bus_dma_tag_t desc_tag; 560 bus_dmamap_t desc_map; 561 char lockname[16]; 562 bus_addr_t ba; /* bus address of descriptor ring */ 563 }; 564 565 struct mp_ring; 566 567 struct txpkts { 568 uint8_t wr_type; /* type 0 or type 1 */ 569 uint8_t npkt; /* # of packets in this work request */ 570 uint8_t len16; /* # of 16B pieces used by this work request */ 571 uint8_t score; 572 uint8_t max_npkt; /* maximum number of packets allowed */ 573 uint16_t plen; /* total payload (sum of all packets) */ 574 575 /* straight from fw_eth_tx_pkts_vm_wr. */ 576 __u8 ethmacdst[6]; 577 __u8 ethmacsrc[6]; 578 __be16 ethtype; 579 __be16 vlantci; 580 581 struct mbuf *mb[15]; 582 }; 583 584 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 585 struct sge_txq { 586 struct sge_eq eq; /* MUST be first */ 587 588 struct ifnet *ifp; /* the interface this txq belongs to */ 589 struct mp_ring *r; /* tx software ring */ 590 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 591 struct sglist *gl; 592 __be32 cpl_ctrl0; /* for convenience */ 593 int tc_idx; /* traffic class */ 594 uint64_t last_tx; /* cycle count when eth_tx was last called */ 595 struct txpkts txp; 596 597 struct task tx_reclaim_task; 598 /* stats for common events first */ 599 600 uint64_t txcsum; /* # of times hardware assisted with checksum */ 601 uint64_t tso_wrs; /* # of TSO work requests */ 602 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 603 uint64_t imm_wrs; /* # of work requests with immediate data */ 604 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 605 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 606 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 607 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 608 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 609 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 610 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 611 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 612 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 613 uint64_t vxlan_txcsum; 614 615 uint64_t kern_tls_records; 616 uint64_t kern_tls_short; 617 uint64_t kern_tls_partial; 618 uint64_t kern_tls_full; 619 uint64_t kern_tls_octets; 620 uint64_t kern_tls_waste; 621 uint64_t kern_tls_options; 622 uint64_t kern_tls_header; 623 uint64_t kern_tls_fin; 624 uint64_t kern_tls_fin_short; 625 uint64_t kern_tls_cbc; 626 uint64_t kern_tls_gcm; 627 628 /* stats for not-that-common events */ 629 630 /* Optional scratch space for constructing work requests. */ 631 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 632 } __aligned(CACHE_LINE_SIZE); 633 634 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 635 struct sge_rxq { 636 struct sge_iq iq; /* MUST be first */ 637 struct sge_fl fl; /* MUST follow iq */ 638 639 struct ifnet *ifp; /* the interface this rxq belongs to */ 640 struct lro_ctrl lro; /* LRO state */ 641 642 /* stats for common events first */ 643 644 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 645 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 646 uint64_t vxlan_rxcsum; 647 648 /* stats for not-that-common events */ 649 650 } __aligned(CACHE_LINE_SIZE); 651 652 static inline struct sge_rxq * 653 iq_to_rxq(struct sge_iq *iq) 654 { 655 656 return (__containerof(iq, struct sge_rxq, iq)); 657 } 658 659 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 660 struct sge_ofld_rxq { 661 struct sge_iq iq; /* MUST be first */ 662 struct sge_fl fl; /* MUST follow iq */ 663 counter_u64_t rx_iscsi_ddp_setup_ok; 664 counter_u64_t rx_iscsi_ddp_setup_error; 665 uint64_t rx_iscsi_ddp_pdus; 666 uint64_t rx_iscsi_ddp_octets; 667 uint64_t rx_iscsi_fl_pdus; 668 uint64_t rx_iscsi_fl_octets; 669 u_long rx_toe_tls_records; 670 u_long rx_toe_tls_octets; 671 } __aligned(CACHE_LINE_SIZE); 672 673 static inline struct sge_ofld_rxq * 674 iq_to_ofld_rxq(struct sge_iq *iq) 675 { 676 677 return (__containerof(iq, struct sge_ofld_rxq, iq)); 678 } 679 680 struct wrqe { 681 STAILQ_ENTRY(wrqe) link; 682 struct sge_wrq *wrq; 683 int wr_len; 684 char wr[] __aligned(16); 685 }; 686 687 struct wrq_cookie { 688 TAILQ_ENTRY(wrq_cookie) link; 689 int ndesc; 690 int pidx; 691 }; 692 693 /* 694 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 695 * are of this type. 696 */ 697 struct sge_wrq { 698 struct sge_eq eq; /* MUST be first */ 699 700 struct adapter *adapter; 701 struct task wrq_tx_task; 702 703 /* Tx desc reserved but WR not "committed" yet. */ 704 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 705 706 /* List of WRs ready to go out as soon as descriptors are available. */ 707 STAILQ_HEAD(, wrqe) wr_list; 708 u_int nwr_pending; 709 u_int ndesc_needed; 710 711 /* stats for common events first */ 712 713 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 714 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 715 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 716 717 /* stats for not-that-common events */ 718 719 /* 720 * Scratch space for work requests that wrap around after reaching the 721 * status page, and some information about the last WR that used it. 722 */ 723 uint16_t ss_pidx; 724 uint16_t ss_len; 725 uint8_t ss[SGE_MAX_WR_LEN]; 726 727 } __aligned(CACHE_LINE_SIZE); 728 729 /* ofld_txq: SGE egress queue + miscellaneous items */ 730 struct sge_ofld_txq { 731 struct sge_wrq wrq; 732 counter_u64_t tx_iscsi_pdus; 733 counter_u64_t tx_iscsi_octets; 734 counter_u64_t tx_toe_tls_records; 735 counter_u64_t tx_toe_tls_octets; 736 } __aligned(CACHE_LINE_SIZE); 737 738 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 739 struct sge_nm_rxq { 740 /* Items used by the driver rx ithread are in this cacheline. */ 741 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 742 u_int nid; /* netmap ring # for this queue */ 743 struct vi_info *vi; 744 745 struct iq_desc *iq_desc; 746 uint16_t iq_abs_id; 747 uint16_t iq_cntxt_id; 748 uint16_t iq_cidx; 749 uint16_t iq_sidx; 750 uint8_t iq_gen; 751 uint32_t fl_sidx; 752 753 /* Items used by netmap rxsync are in this cacheline. */ 754 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 755 uint16_t fl_cntxt_id; 756 uint32_t fl_pidx; 757 uint32_t fl_sidx2; /* copy of fl_sidx */ 758 uint32_t fl_db_val; 759 u_int fl_db_saved; 760 u_int fl_db_threshold; /* in descriptors */ 761 u_int fl_hwidx:4; 762 763 /* 764 * fl_cidx is used by both the ithread and rxsync, the rest are not used 765 * in the rx fast path. 766 */ 767 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 768 769 bus_dma_tag_t iq_desc_tag; 770 bus_dmamap_t iq_desc_map; 771 bus_addr_t iq_ba; 772 int intr_idx; 773 774 bus_dma_tag_t fl_desc_tag; 775 bus_dmamap_t fl_desc_map; 776 bus_addr_t fl_ba; 777 }; 778 779 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 780 struct sge_nm_txq { 781 struct tx_desc *desc; 782 uint16_t cidx; 783 uint16_t pidx; 784 uint16_t sidx; 785 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 786 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 787 uint16_t dbidx; /* pidx of the most recent doorbell */ 788 uint8_t doorbells; 789 volatile uint32_t *udb; 790 u_int udb_qid; 791 u_int cntxt_id; 792 __be32 cpl_ctrl0; /* for convenience */ 793 __be32 op_pkd; /* ditto */ 794 u_int nid; /* netmap ring # for this queue */ 795 796 /* infrequently used items after this */ 797 798 bus_dma_tag_t desc_tag; 799 bus_dmamap_t desc_map; 800 bus_addr_t ba; 801 int iqidx; 802 } __aligned(CACHE_LINE_SIZE); 803 804 struct sge { 805 int nrxq; /* total # of Ethernet rx queues */ 806 int ntxq; /* total # of Ethernet tx queues */ 807 int nofldrxq; /* total # of TOE rx queues */ 808 int nofldtxq; /* total # of TOE tx queues */ 809 int nnmrxq; /* total # of netmap rx queues */ 810 int nnmtxq; /* total # of netmap tx queues */ 811 int niq; /* total # of ingress queues */ 812 int neq; /* total # of egress queues */ 813 814 struct sge_iq fwq; /* Firmware event queue */ 815 struct sge_wrq *ctrlq; /* Control queues */ 816 struct sge_txq *txq; /* NIC tx queues */ 817 struct sge_rxq *rxq; /* NIC rx queues */ 818 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 819 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 820 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 821 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 822 823 uint16_t iq_start; /* first cntxt_id */ 824 uint16_t iq_base; /* first abs_id */ 825 int eq_start; /* first cntxt_id */ 826 int eq_base; /* first abs_id */ 827 int iqmap_sz; 828 int eqmap_sz; 829 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 830 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 831 832 int8_t safe_zidx; 833 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 834 }; 835 836 struct devnames { 837 const char *nexus_name; 838 const char *ifnet_name; 839 const char *vi_ifnet_name; 840 const char *pf03_drv_name; 841 const char *vf_nexus_name; 842 const char *vf_ifnet_name; 843 }; 844 845 struct clip_entry; 846 847 struct adapter { 848 SLIST_ENTRY(adapter) link; 849 device_t dev; 850 struct cdev *cdev; 851 const struct devnames *names; 852 853 /* PCIe register resources */ 854 int regs_rid; 855 struct resource *regs_res; 856 int msix_rid; 857 struct resource *msix_res; 858 bus_space_handle_t bh; 859 bus_space_tag_t bt; 860 bus_size_t mmio_len; 861 int udbs_rid; 862 struct resource *udbs_res; 863 volatile uint8_t *udbs_base; 864 865 unsigned int pf; 866 unsigned int mbox; 867 unsigned int vpd_busy; 868 unsigned int vpd_flag; 869 870 /* Interrupt information */ 871 int intr_type; 872 int intr_count; 873 struct irq { 874 struct resource *res; 875 int rid; 876 void *tag; 877 struct sge_rxq *rxq; 878 struct sge_nm_rxq *nm_rxq; 879 } __aligned(CACHE_LINE_SIZE) *irq; 880 int sge_gts_reg; 881 int sge_kdoorbell_reg; 882 883 bus_dma_tag_t dmat; /* Parent DMA tag */ 884 885 struct sge sge; 886 int lro_timeout; 887 int sc_do_rxcopy; 888 889 int vxlan_port; 890 u_int vxlan_refcount; 891 int rawf_base; 892 int nrawf; 893 894 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 895 struct task async_event_task; 896 struct port_info *port[MAX_NPORTS]; 897 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 898 899 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 900 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 901 u_long clip_mask; 902 int clip_gen; 903 struct timeout_task clip_task; 904 905 void *tom_softc; /* (struct tom_data *) */ 906 struct tom_tunables tt; 907 struct t4_offload_policy *policy; 908 struct rwlock policy_lock; 909 910 void *iwarp_softc; /* (struct c4iw_dev *) */ 911 struct iw_tunables iwt; 912 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 913 void *ccr_softc; /* (struct ccr_softc *) */ 914 struct l2t_data *l2t; /* L2 table */ 915 struct smt_data *smt; /* Source MAC Table */ 916 struct tid_info tids; 917 vmem_t *key_map; 918 struct tls_tunables tlst; 919 920 uint8_t doorbells; 921 int offload_map; /* ports with IFCAP_TOE enabled */ 922 int active_ulds; /* ULDs activated on this adapter */ 923 int flags; 924 int debug_flags; 925 926 char ifp_lockname[16]; 927 struct mtx ifp_lock; 928 struct ifnet *ifp; /* tracer ifp */ 929 struct ifmedia media; 930 int traceq; /* iq used by all tracers, -1 if none */ 931 int tracer_valid; /* bitmap of valid tracers */ 932 int tracer_enabled; /* bitmap of enabled tracers */ 933 934 char fw_version[16]; 935 char tp_version[16]; 936 char er_version[16]; 937 char bs_version[16]; 938 char cfg_file[32]; 939 u_int cfcsum; 940 struct adapter_params params; 941 const struct chip_params *chip_params; 942 struct t4_virt_res vres; 943 944 uint16_t nbmcaps; 945 uint16_t linkcaps; 946 uint16_t switchcaps; 947 uint16_t niccaps; 948 uint16_t toecaps; 949 uint16_t rdmacaps; 950 uint16_t cryptocaps; 951 uint16_t iscsicaps; 952 uint16_t fcoecaps; 953 954 struct sysctl_ctx_list ctx; 955 struct sysctl_oid *ctrlq_oid; 956 struct sysctl_oid *fwq_oid; 957 958 struct mtx sc_lock; 959 char lockname[16]; 960 961 /* Starving free lists */ 962 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 963 TAILQ_HEAD(, sge_fl) sfl; 964 struct callout sfl_callout; 965 966 /* 967 * Driver code that can run when the adapter is suspended must use this 968 * lock or a synchronized_op and check for HW_OFF_LIMITS before 969 * accessing hardware. 970 * 971 * XXX: could be changed to rwlock. wlock in suspend/resume and for 972 * indirect register access, rlock everywhere else. 973 */ 974 struct mtx reg_lock; 975 976 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 977 978 struct mtx tc_lock; 979 struct task tc_task; 980 981 struct task reset_task; 982 const void *reset_thread; 983 int num_resets; 984 int incarnation; 985 986 const char *last_op; 987 const void *last_op_thr; 988 int last_op_flags; 989 990 int swintr; 991 int sensor_resets; 992 993 struct callout ktls_tick; 994 }; 995 996 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 997 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 998 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 999 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1000 1001 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1002 KASSERT(IS_BUSY(sc) && \ 1003 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1004 ("%s: operation not synchronized.", __func__)) 1005 1006 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1007 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1008 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1009 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1010 1011 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1012 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1013 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1014 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1015 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1016 1017 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1018 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1019 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1020 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1021 1022 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1023 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1024 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1025 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1026 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1027 1028 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1029 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1030 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1031 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1032 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1033 1034 #define for_each_txq(vi, iter, q) \ 1035 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1036 iter < vi->ntxq; ++iter, ++q) 1037 #define for_each_rxq(vi, iter, q) \ 1038 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1039 iter < vi->nrxq; ++iter, ++q) 1040 #define for_each_ofld_txq(vi, iter, q) \ 1041 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1042 iter < vi->nofldtxq; ++iter, ++q) 1043 #define for_each_ofld_rxq(vi, iter, q) \ 1044 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1045 iter < vi->nofldrxq; ++iter, ++q) 1046 #define for_each_nm_txq(vi, iter, q) \ 1047 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1048 iter < vi->nnmtxq; ++iter, ++q) 1049 #define for_each_nm_rxq(vi, iter, q) \ 1050 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1051 iter < vi->nnmrxq; ++iter, ++q) 1052 #define for_each_vi(_pi, _iter, _vi) \ 1053 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1054 ++(_iter), ++(_vi)) 1055 1056 #define IDXINCR(idx, incr, wrap) do { \ 1057 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1058 } while (0) 1059 #define IDXDIFF(head, tail, wrap) \ 1060 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1061 1062 /* One for errors, one for firmware events */ 1063 #define T4_EXTRA_INTR 2 1064 1065 /* One for firmware events */ 1066 #define T4VF_EXTRA_INTR 1 1067 1068 static inline int 1069 forwarding_intr_to_fwq(struct adapter *sc) 1070 { 1071 1072 return (sc->intr_count == 1); 1073 } 1074 1075 /* Works reliably inside a sync_op or with reg_lock held. */ 1076 static inline bool 1077 hw_off_limits(struct adapter *sc) 1078 { 1079 return (__predict_false(sc->flags & HW_OFF_LIMITS)); 1080 } 1081 1082 static inline uint32_t 1083 t4_read_reg(struct adapter *sc, uint32_t reg) 1084 { 1085 if (hw_off_limits(sc)) 1086 MPASS(curthread == sc->reset_thread); 1087 return bus_space_read_4(sc->bt, sc->bh, reg); 1088 } 1089 1090 static inline void 1091 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1092 { 1093 if (hw_off_limits(sc)) 1094 MPASS(curthread == sc->reset_thread); 1095 bus_space_write_4(sc->bt, sc->bh, reg, val); 1096 } 1097 1098 static inline uint64_t 1099 t4_read_reg64(struct adapter *sc, uint32_t reg) 1100 { 1101 if (hw_off_limits(sc)) 1102 MPASS(curthread == sc->reset_thread); 1103 #ifdef __LP64__ 1104 return bus_space_read_8(sc->bt, sc->bh, reg); 1105 #else 1106 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1107 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1108 1109 #endif 1110 } 1111 1112 static inline void 1113 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1114 { 1115 if (hw_off_limits(sc)) 1116 MPASS(curthread == sc->reset_thread); 1117 #ifdef __LP64__ 1118 bus_space_write_8(sc->bt, sc->bh, reg, val); 1119 #else 1120 bus_space_write_4(sc->bt, sc->bh, reg, val); 1121 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1122 #endif 1123 } 1124 1125 static inline void 1126 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1127 { 1128 if (hw_off_limits(sc)) 1129 MPASS(curthread == sc->reset_thread); 1130 *val = pci_read_config(sc->dev, reg, 1); 1131 } 1132 1133 static inline void 1134 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1135 { 1136 if (hw_off_limits(sc)) 1137 MPASS(curthread == sc->reset_thread); 1138 pci_write_config(sc->dev, reg, val, 1); 1139 } 1140 1141 static inline void 1142 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1143 { 1144 1145 if (hw_off_limits(sc)) 1146 MPASS(curthread == sc->reset_thread); 1147 *val = pci_read_config(sc->dev, reg, 2); 1148 } 1149 1150 static inline void 1151 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1152 { 1153 if (hw_off_limits(sc)) 1154 MPASS(curthread == sc->reset_thread); 1155 pci_write_config(sc->dev, reg, val, 2); 1156 } 1157 1158 static inline void 1159 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1160 { 1161 if (hw_off_limits(sc)) 1162 MPASS(curthread == sc->reset_thread); 1163 *val = pci_read_config(sc->dev, reg, 4); 1164 } 1165 1166 static inline void 1167 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1168 { 1169 if (hw_off_limits(sc)) 1170 MPASS(curthread == sc->reset_thread); 1171 pci_write_config(sc->dev, reg, val, 4); 1172 } 1173 1174 static inline struct port_info * 1175 adap2pinfo(struct adapter *sc, int idx) 1176 { 1177 1178 return (sc->port[idx]); 1179 } 1180 1181 static inline void 1182 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1183 { 1184 1185 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1186 } 1187 1188 static inline int 1189 tx_resume_threshold(struct sge_eq *eq) 1190 { 1191 1192 /* not quite the same as qsize / 4, but this will do. */ 1193 return (eq->sidx / 4); 1194 } 1195 1196 static inline int 1197 t4_use_ldst(struct adapter *sc) 1198 { 1199 1200 #ifdef notyet 1201 return (sc->flags & FW_OK || !sc->use_bd); 1202 #else 1203 return (0); 1204 #endif 1205 } 1206 1207 static inline void 1208 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1209 const char *msg, const __be64 *const p, const bool err) 1210 { 1211 1212 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1213 return; 1214 if (p != NULL) { 1215 log(err ? LOG_ERR : LOG_DEBUG, 1216 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1217 "%016llx %016llx %016llx %016llx\n", 1218 device_get_nameunit(sc->dev), mbox, msg, 1219 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1220 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1221 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1222 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1223 } else { 1224 log(err ? LOG_ERR : LOG_DEBUG, 1225 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1226 "%016llx %016llx %016llx %016llx\n", 1227 device_get_nameunit(sc->dev), mbox, msg, 1228 (long long)t4_read_reg64(sc, reg), 1229 (long long)t4_read_reg64(sc, reg + 8), 1230 (long long)t4_read_reg64(sc, reg + 16), 1231 (long long)t4_read_reg64(sc, reg + 24), 1232 (long long)t4_read_reg64(sc, reg + 32), 1233 (long long)t4_read_reg64(sc, reg + 40), 1234 (long long)t4_read_reg64(sc, reg + 48), 1235 (long long)t4_read_reg64(sc, reg + 56)); 1236 } 1237 } 1238 1239 /* t4_main.c */ 1240 extern int t4_ntxq; 1241 extern int t4_nrxq; 1242 extern int t4_intr_types; 1243 extern int t4_tmr_idx; 1244 extern int t4_pktc_idx; 1245 extern unsigned int t4_qsize_rxq; 1246 extern unsigned int t4_qsize_txq; 1247 extern device_method_t cxgbe_methods[]; 1248 1249 int t4_os_find_pci_capability(struct adapter *, int); 1250 int t4_os_pci_save_state(struct adapter *); 1251 int t4_os_pci_restore_state(struct adapter *); 1252 void t4_os_portmod_changed(struct port_info *); 1253 void t4_os_link_changed(struct port_info *); 1254 void t4_iterate(void (*)(struct adapter *, void *), void *); 1255 void t4_init_devnames(struct adapter *); 1256 void t4_add_adapter(struct adapter *); 1257 int t4_detach_common(device_t); 1258 int t4_map_bars_0_and_4(struct adapter *); 1259 int t4_map_bar_2(struct adapter *); 1260 int t4_setup_intr_handlers(struct adapter *); 1261 void t4_sysctls(struct adapter *); 1262 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1263 void doom_vi(struct adapter *, struct vi_info *); 1264 void end_synchronized_op(struct adapter *, int); 1265 int update_mac_settings(struct ifnet *, int); 1266 int adapter_init(struct adapter *); 1267 int vi_init(struct vi_info *); 1268 void vi_sysctls(struct vi_info *); 1269 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1270 int alloc_atid(struct adapter *, void *); 1271 void *lookup_atid(struct adapter *, int); 1272 void free_atid(struct adapter *, int); 1273 void release_tid(struct adapter *, int, struct sge_wrq *); 1274 int cxgbe_media_change(struct ifnet *); 1275 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1276 bool t4_os_dump_cimla(struct adapter *, int, bool); 1277 void t4_os_dump_devlog(struct adapter *); 1278 1279 #ifdef KERN_TLS 1280 /* t4_kern_tls.c */ 1281 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1282 struct m_snd_tag **); 1283 void cxgbe_tls_tag_free(struct m_snd_tag *); 1284 void t6_ktls_modload(void); 1285 void t6_ktls_modunload(void); 1286 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1287 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1288 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1289 #endif 1290 1291 /* t4_keyctx.c */ 1292 struct auth_hash; 1293 union authctx; 1294 1295 void t4_aes_getdeckey(void *, const void *, unsigned int); 1296 void t4_copy_partial_hash(int, union authctx *, void *); 1297 void t4_init_gmac_hash(const char *, int, char *); 1298 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *); 1299 1300 #ifdef DEV_NETMAP 1301 /* t4_netmap.c */ 1302 struct sge_nm_rxq; 1303 void cxgbe_nm_attach(struct vi_info *); 1304 void cxgbe_nm_detach(struct vi_info *); 1305 void service_nm_rxq(struct sge_nm_rxq *); 1306 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1307 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1308 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1309 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1310 #endif 1311 1312 /* t4_sge.c */ 1313 void t4_sge_modload(void); 1314 void t4_sge_modunload(void); 1315 uint64_t t4_sge_extfree_refs(void); 1316 void t4_tweak_chip_settings(struct adapter *); 1317 int t4_verify_chip_settings(struct adapter *); 1318 void t4_init_rx_buf_info(struct adapter *); 1319 int t4_create_dma_tag(struct adapter *); 1320 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1321 struct sysctl_oid_list *); 1322 int t4_destroy_dma_tag(struct adapter *); 1323 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1324 bus_addr_t *, void **); 1325 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1326 void *); 1327 void free_fl_buffers(struct adapter *, struct sge_fl *); 1328 int t4_setup_adapter_queues(struct adapter *); 1329 int t4_teardown_adapter_queues(struct adapter *); 1330 int t4_setup_vi_queues(struct vi_info *); 1331 int t4_teardown_vi_queues(struct vi_info *); 1332 void t4_intr_all(void *); 1333 void t4_intr(void *); 1334 #ifdef DEV_NETMAP 1335 void t4_nm_intr(void *); 1336 void t4_vi_intr(void *); 1337 #endif 1338 void t4_intr_err(void *); 1339 void t4_intr_evt(void *); 1340 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1341 void t4_update_fl_bufsize(struct ifnet *); 1342 struct mbuf *alloc_wr_mbuf(int, int); 1343 int parse_pkt(struct mbuf **, bool); 1344 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1345 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1346 int tnl_cong(struct port_info *, int); 1347 void t4_register_an_handler(an_handler_t); 1348 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1349 void t4_register_cpl_handler(int, cpl_handler_t); 1350 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1351 #ifdef RATELIMIT 1352 int ethofld_transmit(struct ifnet *, struct mbuf *); 1353 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1354 #endif 1355 1356 /* t4_tracer.c */ 1357 struct t4_tracer; 1358 void t4_tracer_modload(void); 1359 void t4_tracer_modunload(void); 1360 void t4_tracer_port_detach(struct adapter *); 1361 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1362 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1363 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1364 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1365 1366 /* t4_sched.c */ 1367 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1368 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1369 int t4_init_tx_sched(struct adapter *); 1370 int t4_free_tx_sched(struct adapter *); 1371 void t4_update_tx_sched(struct adapter *); 1372 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1373 void t4_release_cl_rl(struct adapter *, int, int); 1374 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1375 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1376 #ifdef RATELIMIT 1377 void t4_init_etid_table(struct adapter *); 1378 void t4_free_etid_table(struct adapter *); 1379 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1380 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1381 struct m_snd_tag **); 1382 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1383 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1384 void cxgbe_rate_tag_free(struct m_snd_tag *); 1385 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1386 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1387 #endif 1388 1389 /* t4_filter.c */ 1390 int get_filter_mode(struct adapter *, uint32_t *); 1391 int set_filter_mode(struct adapter *, uint32_t); 1392 int set_filter_mask(struct adapter *, uint32_t); 1393 int get_filter(struct adapter *, struct t4_filter *); 1394 int set_filter(struct adapter *, struct t4_filter *); 1395 int del_filter(struct adapter *, struct t4_filter *); 1396 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1397 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1398 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1399 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1400 void free_hftid_hash(struct tid_info *); 1401 1402 static inline struct wrqe * 1403 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1404 { 1405 int len = offsetof(struct wrqe, wr) + wr_len; 1406 struct wrqe *wr; 1407 1408 wr = malloc(len, M_CXGBE, M_NOWAIT); 1409 if (__predict_false(wr == NULL)) 1410 return (NULL); 1411 wr->wr_len = wr_len; 1412 wr->wrq = wrq; 1413 return (wr); 1414 } 1415 1416 static inline void * 1417 wrtod(struct wrqe *wr) 1418 { 1419 return (&wr->wr[0]); 1420 } 1421 1422 static inline void 1423 free_wrqe(struct wrqe *wr) 1424 { 1425 free(wr, M_CXGBE); 1426 } 1427 1428 static inline void 1429 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1430 { 1431 struct sge_wrq *wrq = wr->wrq; 1432 1433 TXQ_LOCK(wrq); 1434 t4_wrq_tx_locked(sc, wrq, wr); 1435 TXQ_UNLOCK(wrq); 1436 } 1437 1438 static inline int 1439 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1440 int len) 1441 { 1442 1443 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1444 } 1445 1446 static inline int 1447 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1448 const uint32_t *val, int len) 1449 { 1450 1451 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1452 } 1453 1454 /* Number of len16 -> number of descriptors */ 1455 static inline int 1456 tx_len16_to_desc(int len16) 1457 { 1458 1459 return (howmany(len16, EQ_ESIZE / 16)); 1460 } 1461 #endif 1462