1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 #if defined(__i386__) || defined(__amd64__) 72 static __inline void 73 prefetch(void *x) 74 { 75 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 76 } 77 #else 78 #define prefetch(x) __builtin_prefetch(x) 79 #endif 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 122 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 123 }; 124 125 enum { 126 /* adapter intr_type */ 127 INTR_INTX = (1 << 0), 128 INTR_MSI = (1 << 1), 129 INTR_MSIX = (1 << 2) 130 }; 131 132 enum { 133 XGMAC_MTU = (1 << 0), 134 XGMAC_PROMISC = (1 << 1), 135 XGMAC_ALLMULTI = (1 << 2), 136 XGMAC_VLANEX = (1 << 3), 137 XGMAC_UCADDR = (1 << 4), 138 XGMAC_MCADDRS = (1 << 5), 139 140 XGMAC_ALL = 0xffff 141 }; 142 143 enum { 144 /* flags understood by begin_synchronized_op */ 145 HOLD_LOCK = (1 << 0), 146 SLEEP_OK = (1 << 1), 147 INTR_OK = (1 << 2), 148 149 /* flags understood by end_synchronized_op */ 150 LOCK_HELD = HOLD_LOCK, 151 }; 152 153 enum { 154 /* adapter flags */ 155 FULL_INIT_DONE = (1 << 0), 156 FW_OK = (1 << 1), 157 CHK_MBOX_ACCESS = (1 << 2), 158 MASTER_PF = (1 << 3), 159 ADAP_SYSCTL_CTX = (1 << 4), 160 ADAP_ERR = (1 << 5), 161 BUF_PACKING_OK = (1 << 6), 162 IS_VF = (1 << 7), 163 KERN_TLS_OK = (1 << 8), 164 165 CXGBE_BUSY = (1 << 9), 166 167 /* port flags */ 168 HAS_TRACEQ = (1 << 3), 169 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 170 171 /* VI flags */ 172 DOOMED = (1 << 0), 173 VI_INIT_DONE = (1 << 1), 174 VI_SYSCTL_CTX = (1 << 2), 175 176 /* adapter debug_flags */ 177 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 178 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 179 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 180 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 181 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 182 }; 183 184 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 185 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 186 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 187 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 188 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 189 190 struct vi_info { 191 device_t dev; 192 struct port_info *pi; 193 194 struct ifnet *ifp; 195 struct pfil_head *pfil; 196 197 unsigned long flags; 198 int if_flags; 199 200 uint16_t *rss, *nm_rss; 201 uint16_t viid; /* opaque VI identifier */ 202 uint16_t smt_idx; 203 uint16_t vin; 204 uint8_t vfvld; 205 int16_t xact_addr_filt;/* index of exact MAC address filter */ 206 uint16_t rss_size; /* size of VI's RSS table slice */ 207 uint16_t rss_base; /* start of VI's RSS table slice */ 208 int hashen; 209 210 int nintr; 211 int first_intr; 212 213 /* These need to be int as they are used in sysctl */ 214 int ntxq; /* # of tx queues */ 215 int first_txq; /* index of first tx queue */ 216 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 217 int nrxq; /* # of rx queues */ 218 int first_rxq; /* index of first rx queue */ 219 int nofldtxq; /* # of offload tx queues */ 220 int first_ofld_txq; /* index of first offload tx queue */ 221 int nofldrxq; /* # of offload rx queues */ 222 int first_ofld_rxq; /* index of first offload rx queue */ 223 int nnmtxq; 224 int first_nm_txq; 225 int nnmrxq; 226 int first_nm_rxq; 227 int tmr_idx; 228 int ofld_tmr_idx; 229 int pktc_idx; 230 int ofld_pktc_idx; 231 int qsize_rxq; 232 int qsize_txq; 233 234 struct timeval last_refreshed; 235 struct fw_vi_stats_vf stats; 236 237 struct callout tick; 238 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 239 240 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 241 }; 242 243 struct tx_ch_rl_params { 244 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 245 uint32_t maxrate; 246 }; 247 248 enum { 249 CLRL_USER = (1 << 0), /* allocated manually. */ 250 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 251 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 252 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 253 }; 254 255 struct tx_cl_rl_params { 256 int refcount; 257 uint8_t flags; 258 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 259 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 260 enum fw_sched_params_mode mode; /* aggr or per-flow */ 261 uint32_t maxrate; 262 uint16_t pktsize; 263 uint16_t burstsize; 264 }; 265 266 /* Tx scheduler parameters for a channel/port */ 267 struct tx_sched_params { 268 /* Channel Rate Limiter */ 269 struct tx_ch_rl_params ch_rl; 270 271 /* Class WRR */ 272 /* XXX */ 273 274 /* Class Rate Limiter (including the default pktsize and burstsize). */ 275 int pktsize; 276 int burstsize; 277 struct tx_cl_rl_params cl_rl[]; 278 }; 279 280 struct port_info { 281 device_t dev; 282 struct adapter *adapter; 283 284 struct vi_info *vi; 285 int nvi; 286 int up_vis; 287 int uld_vis; 288 289 struct tx_sched_params *sched_params; 290 291 struct mtx pi_lock; 292 char lockname[16]; 293 unsigned long flags; 294 295 uint8_t lport; /* associated offload logical port */ 296 int8_t mdio_addr; 297 uint8_t port_type; 298 uint8_t mod_type; 299 uint8_t port_id; 300 uint8_t tx_chan; 301 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 302 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 303 304 struct link_config link_cfg; 305 struct ifmedia media; 306 307 struct timeval last_refreshed; 308 struct port_stats stats; 309 u_int tnl_cong_drops; 310 u_int tx_parse_error; 311 u_long tx_toe_tls_records; 312 u_long tx_toe_tls_octets; 313 u_long rx_toe_tls_records; 314 u_long rx_toe_tls_octets; 315 316 struct callout tick; 317 }; 318 319 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 320 321 struct cluster_metadata { 322 uma_zone_t zone; 323 caddr_t cl; 324 u_int refcount; 325 }; 326 327 struct fl_sdesc { 328 caddr_t cl; 329 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 330 int16_t moff; /* offset of metadata from cl */ 331 uint8_t zidx; 332 }; 333 334 struct tx_desc { 335 __be64 flit[8]; 336 }; 337 338 struct tx_sdesc { 339 struct mbuf *m; /* m_nextpkt linked chain of frames */ 340 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 341 }; 342 343 344 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 345 struct iq_desc { 346 struct rss_header rss; 347 uint8_t cpl[IQ_PAD]; 348 struct rsp_ctrl rsp; 349 }; 350 #undef IQ_PAD 351 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 352 353 enum { 354 /* iq flags */ 355 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 356 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 357 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 358 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 359 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 360 361 /* iq state */ 362 IQS_DISABLED = 0, 363 IQS_BUSY = 1, 364 IQS_IDLE = 2, 365 366 /* netmap related flags */ 367 NM_OFF = 0, 368 NM_ON = 1, 369 NM_BUSY = 2, 370 }; 371 372 enum { 373 CPL_COOKIE_RESERVED = 0, 374 CPL_COOKIE_FILTER, 375 CPL_COOKIE_DDP0, 376 CPL_COOKIE_DDP1, 377 CPL_COOKIE_TOM, 378 CPL_COOKIE_HASHFILTER, 379 CPL_COOKIE_ETHOFLD, 380 CPL_COOKIE_KERN_TLS, 381 382 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 383 }; 384 385 struct sge_iq; 386 struct rss_header; 387 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 388 struct mbuf *); 389 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 390 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 391 392 /* 393 * Ingress Queue: T4 is producer, driver is consumer. 394 */ 395 struct sge_iq { 396 uint32_t flags; 397 volatile int state; 398 struct adapter *adapter; 399 struct iq_desc *desc; /* KVA of descriptor ring */ 400 int8_t intr_pktc_idx; /* packet count threshold index */ 401 uint8_t gen; /* generation bit */ 402 uint8_t intr_params; /* interrupt holdoff parameters */ 403 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 404 uint16_t qsize; /* size (# of entries) of the queue */ 405 uint16_t sidx; /* index of the entry with the status page */ 406 uint16_t cidx; /* consumer index */ 407 uint16_t cntxt_id; /* SGE context id for the iq */ 408 uint16_t abs_id; /* absolute SGE id for the iq */ 409 410 STAILQ_ENTRY(sge_iq) link; 411 412 bus_dma_tag_t desc_tag; 413 bus_dmamap_t desc_map; 414 bus_addr_t ba; /* bus address of descriptor ring */ 415 }; 416 417 enum { 418 EQ_CTRL = 1, 419 EQ_ETH = 2, 420 EQ_OFLD = 3, 421 422 /* eq flags */ 423 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 424 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 425 EQ_ENABLED = (1 << 3), /* open for business */ 426 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 427 }; 428 429 /* Listed in order of preference. Update t4_sysctls too if you change these */ 430 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 431 432 /* 433 * Egress Queue: driver is producer, T4 is consumer. 434 * 435 * Note: A free list is an egress queue (driver produces the buffers and T4 436 * consumes them) but it's special enough to have its own struct (see sge_fl). 437 */ 438 struct sge_eq { 439 unsigned int flags; /* MUST be first */ 440 unsigned int cntxt_id; /* SGE context id for the eq */ 441 unsigned int abs_id; /* absolute SGE id for the eq */ 442 struct mtx eq_lock; 443 444 struct tx_desc *desc; /* KVA of descriptor ring */ 445 uint8_t doorbells; 446 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 447 u_int udb_qid; /* relative qid within the doorbell page */ 448 uint16_t sidx; /* index of the entry with the status page */ 449 uint16_t cidx; /* consumer idx (desc idx) */ 450 uint16_t pidx; /* producer idx (desc idx) */ 451 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 452 uint16_t dbidx; /* pidx of the most recent doorbell */ 453 uint16_t iqid; /* iq that gets egr_update for the eq */ 454 uint8_t tx_chan; /* tx channel used by the eq */ 455 volatile u_int equiq; /* EQUIQ outstanding */ 456 457 bus_dma_tag_t desc_tag; 458 bus_dmamap_t desc_map; 459 bus_addr_t ba; /* bus address of descriptor ring */ 460 char lockname[16]; 461 }; 462 463 struct rx_buf_info { 464 uma_zone_t zone; /* zone that this cluster comes from */ 465 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 466 * hwsize[hwidx1] = size1. No spare. */ 467 uint16_t size2; /* hwsize[hwidx2] = size2. 468 * spare in cluster = size1 - size2. */ 469 int8_t hwidx1; /* SGE bufsize idx for size1 */ 470 int8_t hwidx2; /* SGE bufsize idx for size2 */ 471 uint8_t type; /* EXT_xxx type of the cluster */ 472 }; 473 474 enum { 475 NUM_MEMWIN = 3, 476 477 MEMWIN0_APERTURE = 2048, 478 MEMWIN0_BASE = 0x1b800, 479 480 MEMWIN1_APERTURE = 32768, 481 MEMWIN1_BASE = 0x28000, 482 483 MEMWIN2_APERTURE_T4 = 65536, 484 MEMWIN2_BASE_T4 = 0x30000, 485 486 MEMWIN2_APERTURE_T5 = 128 * 1024, 487 MEMWIN2_BASE_T5 = 0x60000, 488 }; 489 490 struct memwin { 491 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 492 uint32_t mw_base; /* constant after setup_memwin */ 493 uint32_t mw_aperture; /* ditto */ 494 uint32_t mw_curpos; /* protected by mw_lock */ 495 }; 496 497 enum { 498 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 499 FL_DOOMED = (1 << 1), /* about to be destroyed */ 500 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 501 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 502 }; 503 504 #define FL_RUNNING_LOW(fl) \ 505 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 506 #define FL_NOT_RUNNING_LOW(fl) \ 507 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 508 509 struct sge_fl { 510 struct mtx fl_lock; 511 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 512 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 513 uint16_t zidx; /* refill zone idx */ 514 uint16_t safe_zidx; 515 uint16_t lowat; /* # of buffers <= this means fl needs help */ 516 int flags; 517 uint16_t buf_boundary; 518 519 /* The 16b idx all deal with hw descriptors */ 520 uint16_t dbidx; /* hw pidx after last doorbell */ 521 uint16_t sidx; /* index of status page */ 522 volatile uint16_t hw_cidx; 523 524 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 525 uint32_t cidx; /* consumer index */ 526 uint32_t pidx; /* producer index */ 527 528 uint32_t dbval; 529 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 530 volatile uint32_t *udb; 531 532 uint64_t cl_allocated; /* # of clusters allocated */ 533 uint64_t cl_recycled; /* # of clusters recycled */ 534 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 535 536 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 537 struct mbuf *m0; 538 struct mbuf **pnext; 539 u_int remaining; 540 541 uint16_t qsize; /* # of hw descriptors (status page included) */ 542 uint16_t cntxt_id; /* SGE context id for the freelist */ 543 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 544 bus_dma_tag_t desc_tag; 545 bus_dmamap_t desc_map; 546 char lockname[16]; 547 bus_addr_t ba; /* bus address of descriptor ring */ 548 }; 549 550 struct mp_ring; 551 552 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 553 struct sge_txq { 554 struct sge_eq eq; /* MUST be first */ 555 556 struct ifnet *ifp; /* the interface this txq belongs to */ 557 struct mp_ring *r; /* tx software ring */ 558 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 559 struct sglist *gl; 560 __be32 cpl_ctrl0; /* for convenience */ 561 int tc_idx; /* traffic class */ 562 563 struct task tx_reclaim_task; 564 /* stats for common events first */ 565 566 uint64_t txcsum; /* # of times hardware assisted with checksum */ 567 uint64_t tso_wrs; /* # of TSO work requests */ 568 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 569 uint64_t imm_wrs; /* # of work requests with immediate data */ 570 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 571 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 572 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 573 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 574 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 575 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 576 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 577 578 uint64_t kern_tls_records; 579 uint64_t kern_tls_short; 580 uint64_t kern_tls_partial; 581 uint64_t kern_tls_full; 582 uint64_t kern_tls_octets; 583 uint64_t kern_tls_waste; 584 uint64_t kern_tls_options; 585 uint64_t kern_tls_header; 586 uint64_t kern_tls_fin; 587 uint64_t kern_tls_fin_short; 588 uint64_t kern_tls_cbc; 589 uint64_t kern_tls_gcm; 590 591 /* stats for not-that-common events */ 592 593 /* Optional scratch space for constructing work requests. */ 594 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 595 } __aligned(CACHE_LINE_SIZE); 596 597 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 598 struct sge_rxq { 599 struct sge_iq iq; /* MUST be first */ 600 struct sge_fl fl; /* MUST follow iq */ 601 602 struct ifnet *ifp; /* the interface this rxq belongs to */ 603 struct lro_ctrl lro; /* LRO state */ 604 605 /* stats for common events first */ 606 607 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 608 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 609 610 /* stats for not-that-common events */ 611 612 } __aligned(CACHE_LINE_SIZE); 613 614 static inline struct sge_rxq * 615 iq_to_rxq(struct sge_iq *iq) 616 { 617 618 return (__containerof(iq, struct sge_rxq, iq)); 619 } 620 621 622 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 623 struct sge_ofld_rxq { 624 struct sge_iq iq; /* MUST be first */ 625 struct sge_fl fl; /* MUST follow iq */ 626 } __aligned(CACHE_LINE_SIZE); 627 628 static inline struct sge_ofld_rxq * 629 iq_to_ofld_rxq(struct sge_iq *iq) 630 { 631 632 return (__containerof(iq, struct sge_ofld_rxq, iq)); 633 } 634 635 struct wrqe { 636 STAILQ_ENTRY(wrqe) link; 637 struct sge_wrq *wrq; 638 int wr_len; 639 char wr[] __aligned(16); 640 }; 641 642 struct wrq_cookie { 643 TAILQ_ENTRY(wrq_cookie) link; 644 int ndesc; 645 int pidx; 646 }; 647 648 /* 649 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 650 * and offload tx queues are of this type. 651 */ 652 struct sge_wrq { 653 struct sge_eq eq; /* MUST be first */ 654 655 struct adapter *adapter; 656 struct task wrq_tx_task; 657 658 /* Tx desc reserved but WR not "committed" yet. */ 659 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 660 661 /* List of WRs ready to go out as soon as descriptors are available. */ 662 STAILQ_HEAD(, wrqe) wr_list; 663 u_int nwr_pending; 664 u_int ndesc_needed; 665 666 /* stats for common events first */ 667 668 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 669 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 670 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 671 672 /* stats for not-that-common events */ 673 674 /* 675 * Scratch space for work requests that wrap around after reaching the 676 * status page, and some information about the last WR that used it. 677 */ 678 uint16_t ss_pidx; 679 uint16_t ss_len; 680 uint8_t ss[SGE_MAX_WR_LEN]; 681 682 } __aligned(CACHE_LINE_SIZE); 683 684 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 685 struct sge_nm_rxq { 686 /* Items used by the driver rx ithread are in this cacheline. */ 687 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 688 u_int nid; /* netmap ring # for this queue */ 689 struct vi_info *vi; 690 691 struct iq_desc *iq_desc; 692 uint16_t iq_abs_id; 693 uint16_t iq_cntxt_id; 694 uint16_t iq_cidx; 695 uint16_t iq_sidx; 696 uint8_t iq_gen; 697 uint32_t fl_sidx; 698 699 /* Items used by netmap rxsync are in this cacheline. */ 700 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 701 uint16_t fl_cntxt_id; 702 uint32_t fl_pidx; 703 uint32_t fl_sidx2; /* copy of fl_sidx */ 704 uint32_t fl_db_val; 705 u_int fl_db_saved; 706 u_int fl_hwidx:4; 707 708 /* 709 * fl_cidx is used by both the ithread and rxsync, the rest are not used 710 * in the rx fast path. 711 */ 712 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 713 714 bus_dma_tag_t iq_desc_tag; 715 bus_dmamap_t iq_desc_map; 716 bus_addr_t iq_ba; 717 int intr_idx; 718 719 bus_dma_tag_t fl_desc_tag; 720 bus_dmamap_t fl_desc_map; 721 bus_addr_t fl_ba; 722 }; 723 724 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 725 struct sge_nm_txq { 726 struct tx_desc *desc; 727 uint16_t cidx; 728 uint16_t pidx; 729 uint16_t sidx; 730 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 731 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 732 uint16_t dbidx; /* pidx of the most recent doorbell */ 733 uint8_t doorbells; 734 volatile uint32_t *udb; 735 u_int udb_qid; 736 u_int cntxt_id; 737 __be32 cpl_ctrl0; /* for convenience */ 738 __be32 op_pkd; /* ditto */ 739 u_int nid; /* netmap ring # for this queue */ 740 741 /* infrequently used items after this */ 742 743 bus_dma_tag_t desc_tag; 744 bus_dmamap_t desc_map; 745 bus_addr_t ba; 746 int iqidx; 747 } __aligned(CACHE_LINE_SIZE); 748 749 struct sge { 750 int nrxq; /* total # of Ethernet rx queues */ 751 int ntxq; /* total # of Ethernet tx queues */ 752 int nofldrxq; /* total # of TOE rx queues */ 753 int nofldtxq; /* total # of TOE tx queues */ 754 int nnmrxq; /* total # of netmap rx queues */ 755 int nnmtxq; /* total # of netmap tx queues */ 756 int niq; /* total # of ingress queues */ 757 int neq; /* total # of egress queues */ 758 759 struct sge_iq fwq; /* Firmware event queue */ 760 struct sge_wrq *ctrlq; /* Control queues */ 761 struct sge_txq *txq; /* NIC tx queues */ 762 struct sge_rxq *rxq; /* NIC rx queues */ 763 struct sge_wrq *ofld_txq; /* TOE tx queues */ 764 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 765 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 766 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 767 768 uint16_t iq_start; /* first cntxt_id */ 769 uint16_t iq_base; /* first abs_id */ 770 int eq_start; /* first cntxt_id */ 771 int eq_base; /* first abs_id */ 772 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 773 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 774 775 int8_t safe_zidx; 776 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 777 }; 778 779 struct devnames { 780 const char *nexus_name; 781 const char *ifnet_name; 782 const char *vi_ifnet_name; 783 const char *pf03_drv_name; 784 const char *vf_nexus_name; 785 const char *vf_ifnet_name; 786 }; 787 788 struct clip_entry; 789 790 struct adapter { 791 SLIST_ENTRY(adapter) link; 792 device_t dev; 793 struct cdev *cdev; 794 const struct devnames *names; 795 796 /* PCIe register resources */ 797 int regs_rid; 798 struct resource *regs_res; 799 int msix_rid; 800 struct resource *msix_res; 801 bus_space_handle_t bh; 802 bus_space_tag_t bt; 803 bus_size_t mmio_len; 804 int udbs_rid; 805 struct resource *udbs_res; 806 volatile uint8_t *udbs_base; 807 808 unsigned int pf; 809 unsigned int mbox; 810 unsigned int vpd_busy; 811 unsigned int vpd_flag; 812 813 /* Interrupt information */ 814 int intr_type; 815 int intr_count; 816 struct irq { 817 struct resource *res; 818 int rid; 819 void *tag; 820 struct sge_rxq *rxq; 821 struct sge_nm_rxq *nm_rxq; 822 } __aligned(CACHE_LINE_SIZE) *irq; 823 int sge_gts_reg; 824 int sge_kdoorbell_reg; 825 826 bus_dma_tag_t dmat; /* Parent DMA tag */ 827 828 struct sge sge; 829 int lro_timeout; 830 int sc_do_rxcopy; 831 832 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 833 struct port_info *port[MAX_NPORTS]; 834 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 835 836 struct mtx clip_table_lock; 837 TAILQ_HEAD(, clip_entry) clip_table; 838 int clip_gen; 839 840 void *tom_softc; /* (struct tom_data *) */ 841 struct tom_tunables tt; 842 struct t4_offload_policy *policy; 843 struct rwlock policy_lock; 844 845 void *iwarp_softc; /* (struct c4iw_dev *) */ 846 struct iw_tunables iwt; 847 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 848 void *ccr_softc; /* (struct ccr_softc *) */ 849 struct l2t_data *l2t; /* L2 table */ 850 struct smt_data *smt; /* Source MAC Table */ 851 struct tid_info tids; 852 vmem_t *key_map; 853 struct tls_tunables tlst; 854 855 uint8_t doorbells; 856 int offload_map; /* ports with IFCAP_TOE enabled */ 857 int active_ulds; /* ULDs activated on this adapter */ 858 int flags; 859 int debug_flags; 860 861 char ifp_lockname[16]; 862 struct mtx ifp_lock; 863 struct ifnet *ifp; /* tracer ifp */ 864 struct ifmedia media; 865 int traceq; /* iq used by all tracers, -1 if none */ 866 int tracer_valid; /* bitmap of valid tracers */ 867 int tracer_enabled; /* bitmap of enabled tracers */ 868 869 char fw_version[16]; 870 char tp_version[16]; 871 char er_version[16]; 872 char bs_version[16]; 873 char cfg_file[32]; 874 u_int cfcsum; 875 struct adapter_params params; 876 const struct chip_params *chip_params; 877 struct t4_virt_res vres; 878 879 uint16_t nbmcaps; 880 uint16_t linkcaps; 881 uint16_t switchcaps; 882 uint16_t niccaps; 883 uint16_t toecaps; 884 uint16_t rdmacaps; 885 uint16_t cryptocaps; 886 uint16_t iscsicaps; 887 uint16_t fcoecaps; 888 889 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 890 891 struct mtx sc_lock; 892 char lockname[16]; 893 894 /* Starving free lists */ 895 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 896 TAILQ_HEAD(, sge_fl) sfl; 897 struct callout sfl_callout; 898 899 struct mtx reg_lock; /* for indirect register access */ 900 901 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 902 903 struct mtx tc_lock; 904 struct task tc_task; 905 906 const char *last_op; 907 const void *last_op_thr; 908 int last_op_flags; 909 910 int swintr; 911 int sensor_resets; 912 913 struct callout ktls_tick; 914 }; 915 916 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 917 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 918 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 919 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 920 921 #define ASSERT_SYNCHRONIZED_OP(sc) \ 922 KASSERT(IS_BUSY(sc) && \ 923 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 924 ("%s: operation not synchronized.", __func__)) 925 926 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 927 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 928 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 929 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 930 931 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 932 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 933 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 934 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 935 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 936 937 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 938 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 939 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 940 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 941 942 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 943 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 944 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 945 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 946 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 947 948 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 949 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 950 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 951 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 952 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 953 954 #define for_each_txq(vi, iter, q) \ 955 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 956 iter < vi->ntxq; ++iter, ++q) 957 #define for_each_rxq(vi, iter, q) \ 958 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 959 iter < vi->nrxq; ++iter, ++q) 960 #define for_each_ofld_txq(vi, iter, q) \ 961 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 962 iter < vi->nofldtxq; ++iter, ++q) 963 #define for_each_ofld_rxq(vi, iter, q) \ 964 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 965 iter < vi->nofldrxq; ++iter, ++q) 966 #define for_each_nm_txq(vi, iter, q) \ 967 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 968 iter < vi->nnmtxq; ++iter, ++q) 969 #define for_each_nm_rxq(vi, iter, q) \ 970 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 971 iter < vi->nnmrxq; ++iter, ++q) 972 #define for_each_vi(_pi, _iter, _vi) \ 973 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 974 ++(_iter), ++(_vi)) 975 976 #define IDXINCR(idx, incr, wrap) do { \ 977 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 978 } while (0) 979 #define IDXDIFF(head, tail, wrap) \ 980 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 981 982 /* One for errors, one for firmware events */ 983 #define T4_EXTRA_INTR 2 984 985 /* One for firmware events */ 986 #define T4VF_EXTRA_INTR 1 987 988 static inline int 989 forwarding_intr_to_fwq(struct adapter *sc) 990 { 991 992 return (sc->intr_count == 1); 993 } 994 995 static inline uint32_t 996 t4_read_reg(struct adapter *sc, uint32_t reg) 997 { 998 999 return bus_space_read_4(sc->bt, sc->bh, reg); 1000 } 1001 1002 static inline void 1003 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1004 { 1005 1006 bus_space_write_4(sc->bt, sc->bh, reg, val); 1007 } 1008 1009 static inline uint64_t 1010 t4_read_reg64(struct adapter *sc, uint32_t reg) 1011 { 1012 1013 #ifdef __LP64__ 1014 return bus_space_read_8(sc->bt, sc->bh, reg); 1015 #else 1016 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1017 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1018 1019 #endif 1020 } 1021 1022 static inline void 1023 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1024 { 1025 1026 #ifdef __LP64__ 1027 bus_space_write_8(sc->bt, sc->bh, reg, val); 1028 #else 1029 bus_space_write_4(sc->bt, sc->bh, reg, val); 1030 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1031 #endif 1032 } 1033 1034 static inline void 1035 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1036 { 1037 1038 *val = pci_read_config(sc->dev, reg, 1); 1039 } 1040 1041 static inline void 1042 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1043 { 1044 1045 pci_write_config(sc->dev, reg, val, 1); 1046 } 1047 1048 static inline void 1049 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1050 { 1051 1052 *val = pci_read_config(sc->dev, reg, 2); 1053 } 1054 1055 static inline void 1056 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1057 { 1058 1059 pci_write_config(sc->dev, reg, val, 2); 1060 } 1061 1062 static inline void 1063 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1064 { 1065 1066 *val = pci_read_config(sc->dev, reg, 4); 1067 } 1068 1069 static inline void 1070 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1071 { 1072 1073 pci_write_config(sc->dev, reg, val, 4); 1074 } 1075 1076 static inline struct port_info * 1077 adap2pinfo(struct adapter *sc, int idx) 1078 { 1079 1080 return (sc->port[idx]); 1081 } 1082 1083 static inline void 1084 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1085 { 1086 1087 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1088 } 1089 1090 static inline int 1091 tx_resume_threshold(struct sge_eq *eq) 1092 { 1093 1094 /* not quite the same as qsize / 4, but this will do. */ 1095 return (eq->sidx / 4); 1096 } 1097 1098 static inline int 1099 t4_use_ldst(struct adapter *sc) 1100 { 1101 1102 #ifdef notyet 1103 return (sc->flags & FW_OK || !sc->use_bd); 1104 #else 1105 return (0); 1106 #endif 1107 } 1108 1109 static inline void 1110 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1111 const char *msg, const __be64 *const p, const bool err) 1112 { 1113 1114 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1115 return; 1116 if (p != NULL) { 1117 log(err ? LOG_ERR : LOG_DEBUG, 1118 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1119 "%016llx %016llx %016llx %016llx\n", 1120 device_get_nameunit(sc->dev), mbox, msg, 1121 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1122 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1123 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1124 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1125 } else { 1126 log(err ? LOG_ERR : LOG_DEBUG, 1127 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1128 "%016llx %016llx %016llx %016llx\n", 1129 device_get_nameunit(sc->dev), mbox, msg, 1130 (long long)t4_read_reg64(sc, reg), 1131 (long long)t4_read_reg64(sc, reg + 8), 1132 (long long)t4_read_reg64(sc, reg + 16), 1133 (long long)t4_read_reg64(sc, reg + 24), 1134 (long long)t4_read_reg64(sc, reg + 32), 1135 (long long)t4_read_reg64(sc, reg + 40), 1136 (long long)t4_read_reg64(sc, reg + 48), 1137 (long long)t4_read_reg64(sc, reg + 56)); 1138 } 1139 } 1140 1141 /* t4_main.c */ 1142 extern int t4_ntxq; 1143 extern int t4_nrxq; 1144 extern int t4_intr_types; 1145 extern int t4_tmr_idx; 1146 extern int t4_pktc_idx; 1147 extern unsigned int t4_qsize_rxq; 1148 extern unsigned int t4_qsize_txq; 1149 extern device_method_t cxgbe_methods[]; 1150 1151 int t4_os_find_pci_capability(struct adapter *, int); 1152 int t4_os_pci_save_state(struct adapter *); 1153 int t4_os_pci_restore_state(struct adapter *); 1154 void t4_os_portmod_changed(struct port_info *); 1155 void t4_os_link_changed(struct port_info *); 1156 void t4_iterate(void (*)(struct adapter *, void *), void *); 1157 void t4_init_devnames(struct adapter *); 1158 void t4_add_adapter(struct adapter *); 1159 int t4_detach_common(device_t); 1160 int t4_map_bars_0_and_4(struct adapter *); 1161 int t4_map_bar_2(struct adapter *); 1162 int t4_setup_intr_handlers(struct adapter *); 1163 void t4_sysctls(struct adapter *); 1164 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1165 void doom_vi(struct adapter *, struct vi_info *); 1166 void end_synchronized_op(struct adapter *, int); 1167 int update_mac_settings(struct ifnet *, int); 1168 int adapter_full_init(struct adapter *); 1169 int adapter_full_uninit(struct adapter *); 1170 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1171 void cxgbe_snd_tag_init(struct cxgbe_snd_tag *, struct ifnet *, int); 1172 int vi_full_init(struct vi_info *); 1173 int vi_full_uninit(struct vi_info *); 1174 void vi_sysctls(struct vi_info *); 1175 void vi_tick(void *); 1176 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1177 int alloc_atid(struct adapter *, void *); 1178 void *lookup_atid(struct adapter *, int); 1179 void free_atid(struct adapter *, int); 1180 void release_tid(struct adapter *, int, struct sge_wrq *); 1181 int cxgbe_media_change(struct ifnet *); 1182 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1183 bool t4_os_dump_cimla(struct adapter *, int, bool); 1184 void t4_os_dump_devlog(struct adapter *); 1185 1186 #ifdef KERN_TLS 1187 /* t4_kern_tls.c */ 1188 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1189 struct m_snd_tag **); 1190 void cxgbe_tls_tag_free(struct m_snd_tag *); 1191 void t6_ktls_modload(void); 1192 void t6_ktls_modunload(void); 1193 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1194 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1195 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1196 #endif 1197 1198 /* t4_keyctx.c */ 1199 struct auth_hash; 1200 union authctx; 1201 1202 void t4_aes_getdeckey(void *, const void *, unsigned int); 1203 void t4_copy_partial_hash(int, union authctx *, void *); 1204 void t4_init_gmac_hash(const char *, int, char *); 1205 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *); 1206 1207 #ifdef DEV_NETMAP 1208 /* t4_netmap.c */ 1209 struct sge_nm_rxq; 1210 void cxgbe_nm_attach(struct vi_info *); 1211 void cxgbe_nm_detach(struct vi_info *); 1212 void service_nm_rxq(struct sge_nm_rxq *); 1213 #endif 1214 1215 /* t4_sge.c */ 1216 void t4_sge_modload(void); 1217 void t4_sge_modunload(void); 1218 uint64_t t4_sge_extfree_refs(void); 1219 void t4_tweak_chip_settings(struct adapter *); 1220 int t4_read_chip_settings(struct adapter *); 1221 int t4_create_dma_tag(struct adapter *); 1222 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1223 struct sysctl_oid_list *); 1224 int t4_destroy_dma_tag(struct adapter *); 1225 int t4_setup_adapter_queues(struct adapter *); 1226 int t4_teardown_adapter_queues(struct adapter *); 1227 int t4_setup_vi_queues(struct vi_info *); 1228 int t4_teardown_vi_queues(struct vi_info *); 1229 void t4_intr_all(void *); 1230 void t4_intr(void *); 1231 #ifdef DEV_NETMAP 1232 void t4_nm_intr(void *); 1233 void t4_vi_intr(void *); 1234 #endif 1235 void t4_intr_err(void *); 1236 void t4_intr_evt(void *); 1237 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1238 void t4_update_fl_bufsize(struct ifnet *); 1239 struct mbuf *alloc_wr_mbuf(int, int); 1240 int parse_pkt(struct adapter *, struct mbuf **); 1241 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1242 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1243 int tnl_cong(struct port_info *, int); 1244 void t4_register_an_handler(an_handler_t); 1245 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1246 void t4_register_cpl_handler(int, cpl_handler_t); 1247 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1248 #ifdef RATELIMIT 1249 int ethofld_transmit(struct ifnet *, struct mbuf *); 1250 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1251 #endif 1252 1253 /* t4_tracer.c */ 1254 struct t4_tracer; 1255 void t4_tracer_modload(void); 1256 void t4_tracer_modunload(void); 1257 void t4_tracer_port_detach(struct adapter *); 1258 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1259 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1260 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1261 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1262 1263 /* t4_sched.c */ 1264 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1265 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1266 int t4_init_tx_sched(struct adapter *); 1267 int t4_free_tx_sched(struct adapter *); 1268 void t4_update_tx_sched(struct adapter *); 1269 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1270 void t4_release_cl_rl(struct adapter *, int, int); 1271 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1272 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1273 #ifdef RATELIMIT 1274 void t4_init_etid_table(struct adapter *); 1275 void t4_free_etid_table(struct adapter *); 1276 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1277 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1278 struct m_snd_tag **); 1279 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1280 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1281 void cxgbe_rate_tag_free(struct m_snd_tag *); 1282 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1283 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1284 #endif 1285 1286 /* t4_filter.c */ 1287 int get_filter_mode(struct adapter *, uint32_t *); 1288 int set_filter_mode(struct adapter *, uint32_t); 1289 int get_filter(struct adapter *, struct t4_filter *); 1290 int set_filter(struct adapter *, struct t4_filter *); 1291 int del_filter(struct adapter *, struct t4_filter *); 1292 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1293 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1294 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1295 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1296 void free_hftid_hash(struct tid_info *); 1297 1298 static inline struct wrqe * 1299 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1300 { 1301 int len = offsetof(struct wrqe, wr) + wr_len; 1302 struct wrqe *wr; 1303 1304 wr = malloc(len, M_CXGBE, M_NOWAIT); 1305 if (__predict_false(wr == NULL)) 1306 return (NULL); 1307 wr->wr_len = wr_len; 1308 wr->wrq = wrq; 1309 return (wr); 1310 } 1311 1312 static inline void * 1313 wrtod(struct wrqe *wr) 1314 { 1315 return (&wr->wr[0]); 1316 } 1317 1318 static inline void 1319 free_wrqe(struct wrqe *wr) 1320 { 1321 free(wr, M_CXGBE); 1322 } 1323 1324 static inline void 1325 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1326 { 1327 struct sge_wrq *wrq = wr->wrq; 1328 1329 TXQ_LOCK(wrq); 1330 t4_wrq_tx_locked(sc, wrq, wr); 1331 TXQ_UNLOCK(wrq); 1332 } 1333 1334 static inline int 1335 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1336 int len) 1337 { 1338 1339 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1340 } 1341 1342 static inline int 1343 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1344 const uint32_t *val, int len) 1345 { 1346 1347 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1348 } 1349 #endif 1350