1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/types.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/rwlock.h> 43 #include <sys/sx.h> 44 #include <sys/vmem.h> 45 #include <vm/uma.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <machine/bus.h> 50 #include <sys/socket.h> 51 #include <sys/sysctl.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <netinet/in.h> 57 #include <netinet/tcp_lro.h> 58 59 #include "offload.h" 60 #include "t4_ioctl.h" 61 #include "common/t4_msg.h" 62 #include "firmware/t4fw_interface.h" 63 64 #define KTR_CXGBE KTR_SPARE3 65 MALLOC_DECLARE(M_CXGBE); 66 #define CXGBE_UNIMPLEMENTED(s) \ 67 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 68 69 #if defined(__i386__) || defined(__amd64__) 70 static __inline void 71 prefetch(void *x) 72 { 73 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 74 } 75 #else 76 #define prefetch(x) __builtin_prefetch(x) 77 #endif 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 SYSCTL_DECL(_hw_cxgbe); 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 1024, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 120 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 121 }; 122 123 enum { 124 /* adapter intr_type */ 125 INTR_INTX = (1 << 0), 126 INTR_MSI = (1 << 1), 127 INTR_MSIX = (1 << 2) 128 }; 129 130 enum { 131 XGMAC_MTU = (1 << 0), 132 XGMAC_PROMISC = (1 << 1), 133 XGMAC_ALLMULTI = (1 << 2), 134 XGMAC_VLANEX = (1 << 3), 135 XGMAC_UCADDR = (1 << 4), 136 XGMAC_MCADDRS = (1 << 5), 137 138 XGMAC_ALL = 0xffff 139 }; 140 141 enum { 142 /* flags understood by begin_synchronized_op */ 143 HOLD_LOCK = (1 << 0), 144 SLEEP_OK = (1 << 1), 145 INTR_OK = (1 << 2), 146 147 /* flags understood by end_synchronized_op */ 148 LOCK_HELD = HOLD_LOCK, 149 }; 150 151 enum { 152 /* adapter flags */ 153 FULL_INIT_DONE = (1 << 0), 154 FW_OK = (1 << 1), 155 CHK_MBOX_ACCESS = (1 << 2), 156 MASTER_PF = (1 << 3), 157 ADAP_SYSCTL_CTX = (1 << 4), 158 /* TOM_INIT_DONE= (1 << 5), No longer used */ 159 BUF_PACKING_OK = (1 << 6), 160 IS_VF = (1 << 7), 161 162 CXGBE_BUSY = (1 << 9), 163 164 /* port flags */ 165 HAS_TRACEQ = (1 << 3), 166 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 167 168 /* VI flags */ 169 DOOMED = (1 << 0), 170 VI_INIT_DONE = (1 << 1), 171 VI_SYSCTL_CTX = (1 << 2), 172 173 /* adapter debug_flags */ 174 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 175 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 176 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 177 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 178 }; 179 180 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 181 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 182 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 183 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 184 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 185 186 struct vi_info { 187 device_t dev; 188 struct port_info *pi; 189 190 struct ifnet *ifp; 191 192 unsigned long flags; 193 int if_flags; 194 195 uint16_t *rss, *nm_rss; 196 int smt_idx; /* for convenience */ 197 uint16_t viid; 198 int16_t xact_addr_filt;/* index of exact MAC address filter */ 199 uint16_t rss_size; /* size of VI's RSS table slice */ 200 uint16_t rss_base; /* start of VI's RSS table slice */ 201 int hashen; 202 203 int nintr; 204 int first_intr; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 int nnmtxq; 217 int first_nm_txq; 218 int nnmrxq; 219 int first_nm_rxq; 220 int tmr_idx; 221 int ofld_tmr_idx; 222 int pktc_idx; 223 int ofld_pktc_idx; 224 int qsize_rxq; 225 int qsize_txq; 226 227 struct timeval last_refreshed; 228 struct fw_vi_stats_vf stats; 229 230 struct callout tick; 231 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 232 233 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 234 }; 235 236 struct tx_ch_rl_params { 237 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 238 uint32_t maxrate; 239 }; 240 241 enum { 242 CLRL_USER = (1 << 0), /* allocated manually. */ 243 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 244 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 245 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 246 }; 247 248 struct tx_cl_rl_params { 249 int refcount; 250 uint8_t flags; 251 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 252 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 253 enum fw_sched_params_mode mode; /* aggr or per-flow */ 254 uint32_t maxrate; 255 uint16_t pktsize; 256 uint16_t burstsize; 257 }; 258 259 /* Tx scheduler parameters for a channel/port */ 260 struct tx_sched_params { 261 /* Channel Rate Limiter */ 262 struct tx_ch_rl_params ch_rl; 263 264 /* Class WRR */ 265 /* XXX */ 266 267 /* Class Rate Limiter (including the default pktsize and burstsize). */ 268 int pktsize; 269 int burstsize; 270 struct tx_cl_rl_params cl_rl[]; 271 }; 272 273 struct port_info { 274 device_t dev; 275 struct adapter *adapter; 276 277 struct vi_info *vi; 278 int nvi; 279 int up_vis; 280 int uld_vis; 281 282 struct tx_sched_params *sched_params; 283 284 struct mtx pi_lock; 285 char lockname[16]; 286 unsigned long flags; 287 288 uint8_t lport; /* associated offload logical port */ 289 int8_t mdio_addr; 290 uint8_t port_type; 291 uint8_t mod_type; 292 uint8_t port_id; 293 uint8_t tx_chan; 294 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 295 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 296 297 struct link_config link_cfg; 298 struct ifmedia media; 299 300 struct timeval last_refreshed; 301 struct port_stats stats; 302 u_int tnl_cong_drops; 303 u_int tx_parse_error; 304 u_long tx_tls_records; 305 u_long tx_tls_octets; 306 u_long rx_tls_records; 307 u_long rx_tls_octets; 308 309 struct callout tick; 310 }; 311 312 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 313 314 /* Where the cluster came from, how it has been carved up. */ 315 struct cluster_layout { 316 int8_t zidx; 317 int8_t hwidx; 318 uint16_t region1; /* mbufs laid out within this region */ 319 /* region2 is the DMA region */ 320 uint16_t region3; /* cluster_metadata within this region */ 321 }; 322 323 struct cluster_metadata { 324 u_int refcount; 325 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 326 }; 327 328 struct fl_sdesc { 329 caddr_t cl; 330 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 331 struct cluster_layout cll; 332 }; 333 334 struct tx_desc { 335 __be64 flit[8]; 336 }; 337 338 struct tx_sdesc { 339 struct mbuf *m; /* m_nextpkt linked chain of frames */ 340 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 341 }; 342 343 344 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 345 struct iq_desc { 346 struct rss_header rss; 347 uint8_t cpl[IQ_PAD]; 348 struct rsp_ctrl rsp; 349 }; 350 #undef IQ_PAD 351 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 352 353 enum { 354 /* iq flags */ 355 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 356 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 357 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 358 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 359 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 360 361 /* iq state */ 362 IQS_DISABLED = 0, 363 IQS_BUSY = 1, 364 IQS_IDLE = 2, 365 366 /* netmap related flags */ 367 NM_OFF = 0, 368 NM_ON = 1, 369 NM_BUSY = 2, 370 }; 371 372 enum { 373 CPL_COOKIE_RESERVED = 0, 374 CPL_COOKIE_FILTER, 375 CPL_COOKIE_DDP0, 376 CPL_COOKIE_DDP1, 377 CPL_COOKIE_TOM, 378 CPL_COOKIE_HASHFILTER, 379 CPL_COOKIE_ETHOFLD, 380 CPL_COOKIE_AVAILABLE3, 381 382 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 383 }; 384 385 struct sge_iq; 386 struct rss_header; 387 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 388 struct mbuf *); 389 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 390 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 391 392 /* 393 * Ingress Queue: T4 is producer, driver is consumer. 394 */ 395 struct sge_iq { 396 uint32_t flags; 397 volatile int state; 398 struct adapter *adapter; 399 struct iq_desc *desc; /* KVA of descriptor ring */ 400 int8_t intr_pktc_idx; /* packet count threshold index */ 401 uint8_t gen; /* generation bit */ 402 uint8_t intr_params; /* interrupt holdoff parameters */ 403 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 404 uint16_t qsize; /* size (# of entries) of the queue */ 405 uint16_t sidx; /* index of the entry with the status page */ 406 uint16_t cidx; /* consumer index */ 407 uint16_t cntxt_id; /* SGE context id for the iq */ 408 uint16_t abs_id; /* absolute SGE id for the iq */ 409 410 STAILQ_ENTRY(sge_iq) link; 411 412 bus_dma_tag_t desc_tag; 413 bus_dmamap_t desc_map; 414 bus_addr_t ba; /* bus address of descriptor ring */ 415 }; 416 417 enum { 418 EQ_CTRL = 1, 419 EQ_ETH = 2, 420 EQ_OFLD = 3, 421 422 /* eq flags */ 423 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 424 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 425 EQ_ENABLED = (1 << 3), /* open for business */ 426 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 427 }; 428 429 /* Listed in order of preference. Update t4_sysctls too if you change these */ 430 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 431 432 /* 433 * Egress Queue: driver is producer, T4 is consumer. 434 * 435 * Note: A free list is an egress queue (driver produces the buffers and T4 436 * consumes them) but it's special enough to have its own struct (see sge_fl). 437 */ 438 struct sge_eq { 439 unsigned int flags; /* MUST be first */ 440 unsigned int cntxt_id; /* SGE context id for the eq */ 441 unsigned int abs_id; /* absolute SGE id for the eq */ 442 struct mtx eq_lock; 443 444 struct tx_desc *desc; /* KVA of descriptor ring */ 445 uint8_t doorbells; 446 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 447 u_int udb_qid; /* relative qid within the doorbell page */ 448 uint16_t sidx; /* index of the entry with the status page */ 449 uint16_t cidx; /* consumer idx (desc idx) */ 450 uint16_t pidx; /* producer idx (desc idx) */ 451 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 452 uint16_t dbidx; /* pidx of the most recent doorbell */ 453 uint16_t iqid; /* iq that gets egr_update for the eq */ 454 uint8_t tx_chan; /* tx channel used by the eq */ 455 volatile u_int equiq; /* EQUIQ outstanding */ 456 457 bus_dma_tag_t desc_tag; 458 bus_dmamap_t desc_map; 459 bus_addr_t ba; /* bus address of descriptor ring */ 460 char lockname[16]; 461 }; 462 463 struct sw_zone_info { 464 uma_zone_t zone; /* zone that this cluster comes from */ 465 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 466 int type; /* EXT_xxx type of the cluster */ 467 int8_t head_hwidx; 468 int8_t tail_hwidx; 469 }; 470 471 struct hw_buf_info { 472 int8_t zidx; /* backpointer to zone; -ve means unused */ 473 int8_t next; /* next hwidx for this zone; -1 means no more */ 474 int size; 475 }; 476 477 enum { 478 NUM_MEMWIN = 3, 479 480 MEMWIN0_APERTURE = 2048, 481 MEMWIN0_BASE = 0x1b800, 482 483 MEMWIN1_APERTURE = 32768, 484 MEMWIN1_BASE = 0x28000, 485 486 MEMWIN2_APERTURE_T4 = 65536, 487 MEMWIN2_BASE_T4 = 0x30000, 488 489 MEMWIN2_APERTURE_T5 = 128 * 1024, 490 MEMWIN2_BASE_T5 = 0x60000, 491 }; 492 493 struct memwin { 494 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 495 uint32_t mw_base; /* constant after setup_memwin */ 496 uint32_t mw_aperture; /* ditto */ 497 uint32_t mw_curpos; /* protected by mw_lock */ 498 }; 499 500 enum { 501 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 502 FL_DOOMED = (1 << 1), /* about to be destroyed */ 503 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 504 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 505 }; 506 507 #define FL_RUNNING_LOW(fl) \ 508 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 509 #define FL_NOT_RUNNING_LOW(fl) \ 510 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 511 512 struct sge_fl { 513 struct mtx fl_lock; 514 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 515 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 516 struct cluster_layout cll_def; /* default refill zone, layout */ 517 uint16_t lowat; /* # of buffers <= this means fl needs help */ 518 int flags; 519 uint16_t buf_boundary; 520 521 /* The 16b idx all deal with hw descriptors */ 522 uint16_t dbidx; /* hw pidx after last doorbell */ 523 uint16_t sidx; /* index of status page */ 524 volatile uint16_t hw_cidx; 525 526 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 527 uint32_t cidx; /* consumer index */ 528 uint32_t pidx; /* producer index */ 529 530 uint32_t dbval; 531 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 532 volatile uint32_t *udb; 533 534 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 535 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 536 uint64_t cl_allocated; /* # of clusters allocated */ 537 uint64_t cl_recycled; /* # of clusters recycled */ 538 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 539 540 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 541 struct mbuf *m0; 542 struct mbuf **pnext; 543 u_int remaining; 544 545 uint16_t qsize; /* # of hw descriptors (status page included) */ 546 uint16_t cntxt_id; /* SGE context id for the freelist */ 547 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 548 bus_dma_tag_t desc_tag; 549 bus_dmamap_t desc_map; 550 char lockname[16]; 551 bus_addr_t ba; /* bus address of descriptor ring */ 552 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 553 }; 554 555 struct mp_ring; 556 557 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 558 struct sge_txq { 559 struct sge_eq eq; /* MUST be first */ 560 561 struct ifnet *ifp; /* the interface this txq belongs to */ 562 struct mp_ring *r; /* tx software ring */ 563 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 564 struct sglist *gl; 565 __be32 cpl_ctrl0; /* for convenience */ 566 int tc_idx; /* traffic class */ 567 568 struct task tx_reclaim_task; 569 /* stats for common events first */ 570 571 uint64_t txcsum; /* # of times hardware assisted with checksum */ 572 uint64_t tso_wrs; /* # of TSO work requests */ 573 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 574 uint64_t imm_wrs; /* # of work requests with immediate data */ 575 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 576 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 577 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 578 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 579 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 580 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 581 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 582 583 /* stats for not-that-common events */ 584 } __aligned(CACHE_LINE_SIZE); 585 586 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 587 struct sge_rxq { 588 struct sge_iq iq; /* MUST be first */ 589 struct sge_fl fl; /* MUST follow iq */ 590 591 struct ifnet *ifp; /* the interface this rxq belongs to */ 592 #if defined(INET) || defined(INET6) 593 struct lro_ctrl lro; /* LRO state */ 594 #endif 595 596 /* stats for common events first */ 597 598 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 599 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 600 601 /* stats for not-that-common events */ 602 603 } __aligned(CACHE_LINE_SIZE); 604 605 static inline struct sge_rxq * 606 iq_to_rxq(struct sge_iq *iq) 607 { 608 609 return (__containerof(iq, struct sge_rxq, iq)); 610 } 611 612 613 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 614 struct sge_ofld_rxq { 615 struct sge_iq iq; /* MUST be first */ 616 struct sge_fl fl; /* MUST follow iq */ 617 } __aligned(CACHE_LINE_SIZE); 618 619 static inline struct sge_ofld_rxq * 620 iq_to_ofld_rxq(struct sge_iq *iq) 621 { 622 623 return (__containerof(iq, struct sge_ofld_rxq, iq)); 624 } 625 626 struct wrqe { 627 STAILQ_ENTRY(wrqe) link; 628 struct sge_wrq *wrq; 629 int wr_len; 630 char wr[] __aligned(16); 631 }; 632 633 struct wrq_cookie { 634 TAILQ_ENTRY(wrq_cookie) link; 635 int ndesc; 636 int pidx; 637 }; 638 639 /* 640 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 641 * and offload tx queues are of this type. 642 */ 643 struct sge_wrq { 644 struct sge_eq eq; /* MUST be first */ 645 646 struct adapter *adapter; 647 struct task wrq_tx_task; 648 649 /* Tx desc reserved but WR not "committed" yet. */ 650 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 651 652 /* List of WRs ready to go out as soon as descriptors are available. */ 653 STAILQ_HEAD(, wrqe) wr_list; 654 u_int nwr_pending; 655 u_int ndesc_needed; 656 657 /* stats for common events first */ 658 659 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 660 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 661 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 662 663 /* stats for not-that-common events */ 664 665 /* 666 * Scratch space for work requests that wrap around after reaching the 667 * status page, and some information about the last WR that used it. 668 */ 669 uint16_t ss_pidx; 670 uint16_t ss_len; 671 uint8_t ss[SGE_MAX_WR_LEN]; 672 673 } __aligned(CACHE_LINE_SIZE); 674 675 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 676 struct sge_nm_rxq { 677 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 678 struct vi_info *vi; 679 680 struct iq_desc *iq_desc; 681 uint16_t iq_abs_id; 682 uint16_t iq_cntxt_id; 683 uint16_t iq_cidx; 684 uint16_t iq_sidx; 685 uint8_t iq_gen; 686 687 __be64 *fl_desc; 688 uint16_t fl_cntxt_id; 689 uint32_t fl_cidx; 690 uint32_t fl_pidx; 691 uint32_t fl_sidx; 692 uint32_t fl_db_val; 693 u_int fl_hwidx:4; 694 695 u_int fl_db_saved; 696 u_int nid; /* netmap ring # for this queue */ 697 698 /* infrequently used items after this */ 699 700 bus_dma_tag_t iq_desc_tag; 701 bus_dmamap_t iq_desc_map; 702 bus_addr_t iq_ba; 703 int intr_idx; 704 705 bus_dma_tag_t fl_desc_tag; 706 bus_dmamap_t fl_desc_map; 707 bus_addr_t fl_ba; 708 } __aligned(CACHE_LINE_SIZE); 709 710 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 711 struct sge_nm_txq { 712 struct tx_desc *desc; 713 uint16_t cidx; 714 uint16_t pidx; 715 uint16_t sidx; 716 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 717 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 718 uint16_t dbidx; /* pidx of the most recent doorbell */ 719 uint8_t doorbells; 720 volatile uint32_t *udb; 721 u_int udb_qid; 722 u_int cntxt_id; 723 __be32 cpl_ctrl0; /* for convenience */ 724 u_int nid; /* netmap ring # for this queue */ 725 726 /* infrequently used items after this */ 727 728 bus_dma_tag_t desc_tag; 729 bus_dmamap_t desc_map; 730 bus_addr_t ba; 731 int iqidx; 732 } __aligned(CACHE_LINE_SIZE); 733 734 struct sge { 735 int nrxq; /* total # of Ethernet rx queues */ 736 int ntxq; /* total # of Ethernet tx queues */ 737 int nofldrxq; /* total # of TOE rx queues */ 738 int nofldtxq; /* total # of TOE tx queues */ 739 int nnmrxq; /* total # of netmap rx queues */ 740 int nnmtxq; /* total # of netmap tx queues */ 741 int niq; /* total # of ingress queues */ 742 int neq; /* total # of egress queues */ 743 744 struct sge_iq fwq; /* Firmware event queue */ 745 struct sge_wrq *ctrlq; /* Control queues */ 746 struct sge_txq *txq; /* NIC tx queues */ 747 struct sge_rxq *rxq; /* NIC rx queues */ 748 struct sge_wrq *ofld_txq; /* TOE tx queues */ 749 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 750 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 751 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 752 753 uint16_t iq_start; /* first cntxt_id */ 754 uint16_t iq_base; /* first abs_id */ 755 int eq_start; /* first cntxt_id */ 756 int eq_base; /* first abs_id */ 757 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 758 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 759 760 int8_t safe_hwidx1; /* may not have room for metadata */ 761 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 762 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 763 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 764 }; 765 766 struct devnames { 767 const char *nexus_name; 768 const char *ifnet_name; 769 const char *vi_ifnet_name; 770 const char *pf03_drv_name; 771 const char *vf_nexus_name; 772 const char *vf_ifnet_name; 773 }; 774 775 struct clip_entry; 776 777 struct adapter { 778 SLIST_ENTRY(adapter) link; 779 device_t dev; 780 struct cdev *cdev; 781 const struct devnames *names; 782 783 /* PCIe register resources */ 784 int regs_rid; 785 struct resource *regs_res; 786 int msix_rid; 787 struct resource *msix_res; 788 bus_space_handle_t bh; 789 bus_space_tag_t bt; 790 bus_size_t mmio_len; 791 int udbs_rid; 792 struct resource *udbs_res; 793 volatile uint8_t *udbs_base; 794 795 unsigned int pf; 796 unsigned int mbox; 797 unsigned int vpd_busy; 798 unsigned int vpd_flag; 799 800 /* Interrupt information */ 801 int intr_type; 802 int intr_count; 803 struct irq { 804 struct resource *res; 805 int rid; 806 void *tag; 807 struct sge_rxq *rxq; 808 struct sge_nm_rxq *nm_rxq; 809 } __aligned(CACHE_LINE_SIZE) *irq; 810 int sge_gts_reg; 811 int sge_kdoorbell_reg; 812 813 bus_dma_tag_t dmat; /* Parent DMA tag */ 814 815 struct sge sge; 816 int lro_timeout; 817 int sc_do_rxcopy; 818 819 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 820 struct port_info *port[MAX_NPORTS]; 821 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 822 823 struct mtx clip_table_lock; 824 TAILQ_HEAD(, clip_entry) clip_table; 825 int clip_gen; 826 827 void *tom_softc; /* (struct tom_data *) */ 828 struct tom_tunables tt; 829 struct t4_offload_policy *policy; 830 struct rwlock policy_lock; 831 832 void *iwarp_softc; /* (struct c4iw_dev *) */ 833 struct iw_tunables iwt; 834 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 835 void *ccr_softc; /* (struct ccr_softc *) */ 836 struct l2t_data *l2t; /* L2 table */ 837 struct smt_data *smt; /* Source MAC Table */ 838 struct tid_info tids; 839 vmem_t *key_map; 840 841 uint8_t doorbells; 842 int offload_map; /* ports with IFCAP_TOE enabled */ 843 int active_ulds; /* ULDs activated on this adapter */ 844 int flags; 845 int debug_flags; 846 847 char ifp_lockname[16]; 848 struct mtx ifp_lock; 849 struct ifnet *ifp; /* tracer ifp */ 850 struct ifmedia media; 851 int traceq; /* iq used by all tracers, -1 if none */ 852 int tracer_valid; /* bitmap of valid tracers */ 853 int tracer_enabled; /* bitmap of enabled tracers */ 854 855 char fw_version[16]; 856 char tp_version[16]; 857 char er_version[16]; 858 char bs_version[16]; 859 char cfg_file[32]; 860 u_int cfcsum; 861 struct adapter_params params; 862 const struct chip_params *chip_params; 863 struct t4_virt_res vres; 864 865 uint16_t nbmcaps; 866 uint16_t linkcaps; 867 uint16_t switchcaps; 868 uint16_t niccaps; 869 uint16_t toecaps; 870 uint16_t rdmacaps; 871 uint16_t cryptocaps; 872 uint16_t iscsicaps; 873 uint16_t fcoecaps; 874 875 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 876 877 struct mtx sc_lock; 878 char lockname[16]; 879 880 /* Starving free lists */ 881 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 882 TAILQ_HEAD(, sge_fl) sfl; 883 struct callout sfl_callout; 884 885 struct mtx reg_lock; /* for indirect register access */ 886 887 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 888 889 struct mtx tc_lock; 890 struct task tc_task; 891 892 const char *last_op; 893 const void *last_op_thr; 894 int last_op_flags; 895 }; 896 897 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 898 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 899 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 900 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 901 902 #define ASSERT_SYNCHRONIZED_OP(sc) \ 903 KASSERT(IS_BUSY(sc) && \ 904 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 905 ("%s: operation not synchronized.", __func__)) 906 907 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 908 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 909 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 910 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 911 912 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 913 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 914 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 915 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 916 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 917 918 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 919 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 920 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 921 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 922 923 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 924 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 925 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 926 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 927 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 928 929 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 930 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 931 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 932 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 933 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 934 935 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 936 do { \ 937 if (sc->debug_flags & DF_DUMP_MBOX) { \ 938 log(LOG_NOTICE, \ 939 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 940 "%016llx %016llx %016llx %016llx\n", \ 941 device_get_nameunit(sc->dev), mbox, \ 942 (unsigned long long)t4_read_reg64(sc, data_reg), \ 943 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 944 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 945 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 946 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 947 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 948 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 949 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 950 } \ 951 } while (0) 952 953 #define for_each_txq(vi, iter, q) \ 954 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 955 iter < vi->ntxq; ++iter, ++q) 956 #define for_each_rxq(vi, iter, q) \ 957 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 958 iter < vi->nrxq; ++iter, ++q) 959 #define for_each_ofld_txq(vi, iter, q) \ 960 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 961 iter < vi->nofldtxq; ++iter, ++q) 962 #define for_each_ofld_rxq(vi, iter, q) \ 963 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 964 iter < vi->nofldrxq; ++iter, ++q) 965 #define for_each_nm_txq(vi, iter, q) \ 966 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 967 iter < vi->nnmtxq; ++iter, ++q) 968 #define for_each_nm_rxq(vi, iter, q) \ 969 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 970 iter < vi->nnmrxq; ++iter, ++q) 971 #define for_each_vi(_pi, _iter, _vi) \ 972 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 973 ++(_iter), ++(_vi)) 974 975 #define IDXINCR(idx, incr, wrap) do { \ 976 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 977 } while (0) 978 #define IDXDIFF(head, tail, wrap) \ 979 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 980 981 /* One for errors, one for firmware events */ 982 #define T4_EXTRA_INTR 2 983 984 /* One for firmware events */ 985 #define T4VF_EXTRA_INTR 1 986 987 static inline int 988 forwarding_intr_to_fwq(struct adapter *sc) 989 { 990 991 return (sc->intr_count == 1); 992 } 993 994 static inline uint32_t 995 t4_read_reg(struct adapter *sc, uint32_t reg) 996 { 997 998 return bus_space_read_4(sc->bt, sc->bh, reg); 999 } 1000 1001 static inline void 1002 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1003 { 1004 1005 bus_space_write_4(sc->bt, sc->bh, reg, val); 1006 } 1007 1008 static inline uint64_t 1009 t4_read_reg64(struct adapter *sc, uint32_t reg) 1010 { 1011 1012 #ifdef __LP64__ 1013 return bus_space_read_8(sc->bt, sc->bh, reg); 1014 #else 1015 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1016 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1017 1018 #endif 1019 } 1020 1021 static inline void 1022 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1023 { 1024 1025 #ifdef __LP64__ 1026 bus_space_write_8(sc->bt, sc->bh, reg, val); 1027 #else 1028 bus_space_write_4(sc->bt, sc->bh, reg, val); 1029 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1030 #endif 1031 } 1032 1033 static inline void 1034 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1035 { 1036 1037 *val = pci_read_config(sc->dev, reg, 1); 1038 } 1039 1040 static inline void 1041 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1042 { 1043 1044 pci_write_config(sc->dev, reg, val, 1); 1045 } 1046 1047 static inline void 1048 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1049 { 1050 1051 *val = pci_read_config(sc->dev, reg, 2); 1052 } 1053 1054 static inline void 1055 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1056 { 1057 1058 pci_write_config(sc->dev, reg, val, 2); 1059 } 1060 1061 static inline void 1062 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1063 { 1064 1065 *val = pci_read_config(sc->dev, reg, 4); 1066 } 1067 1068 static inline void 1069 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1070 { 1071 1072 pci_write_config(sc->dev, reg, val, 4); 1073 } 1074 1075 static inline struct port_info * 1076 adap2pinfo(struct adapter *sc, int idx) 1077 { 1078 1079 return (sc->port[idx]); 1080 } 1081 1082 static inline void 1083 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1084 { 1085 1086 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1087 } 1088 1089 static inline int 1090 tx_resume_threshold(struct sge_eq *eq) 1091 { 1092 1093 /* not quite the same as qsize / 4, but this will do. */ 1094 return (eq->sidx / 4); 1095 } 1096 1097 static inline int 1098 t4_use_ldst(struct adapter *sc) 1099 { 1100 1101 #ifdef notyet 1102 return (sc->flags & FW_OK || !sc->use_bd); 1103 #else 1104 return (0); 1105 #endif 1106 } 1107 1108 /* t4_main.c */ 1109 extern int t4_ntxq; 1110 extern int t4_nrxq; 1111 extern int t4_intr_types; 1112 extern int t4_tmr_idx; 1113 extern int t4_pktc_idx; 1114 extern unsigned int t4_qsize_rxq; 1115 extern unsigned int t4_qsize_txq; 1116 extern device_method_t cxgbe_methods[]; 1117 1118 int t4_os_find_pci_capability(struct adapter *, int); 1119 int t4_os_pci_save_state(struct adapter *); 1120 int t4_os_pci_restore_state(struct adapter *); 1121 void t4_os_portmod_changed(struct port_info *); 1122 void t4_os_link_changed(struct port_info *); 1123 void t4_iterate(void (*)(struct adapter *, void *), void *); 1124 void t4_init_devnames(struct adapter *); 1125 void t4_add_adapter(struct adapter *); 1126 void t4_aes_getdeckey(void *, const void *, unsigned int); 1127 int t4_detach_common(device_t); 1128 int t4_map_bars_0_and_4(struct adapter *); 1129 int t4_map_bar_2(struct adapter *); 1130 int t4_setup_intr_handlers(struct adapter *); 1131 void t4_sysctls(struct adapter *); 1132 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1133 void doom_vi(struct adapter *, struct vi_info *); 1134 void end_synchronized_op(struct adapter *, int); 1135 int update_mac_settings(struct ifnet *, int); 1136 int adapter_full_init(struct adapter *); 1137 int adapter_full_uninit(struct adapter *); 1138 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1139 int vi_full_init(struct vi_info *); 1140 int vi_full_uninit(struct vi_info *); 1141 void vi_sysctls(struct vi_info *); 1142 void vi_tick(void *); 1143 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1144 int alloc_atid_tab(struct tid_info *, int); 1145 void free_atid_tab(struct tid_info *); 1146 int alloc_atid(struct adapter *, void *); 1147 void *lookup_atid(struct adapter *, int); 1148 void free_atid(struct adapter *, int); 1149 void release_tid(struct adapter *, int, struct sge_wrq *); 1150 int cxgbe_media_change(struct ifnet *); 1151 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1152 1153 #ifdef DEV_NETMAP 1154 /* t4_netmap.c */ 1155 struct sge_nm_rxq; 1156 void cxgbe_nm_attach(struct vi_info *); 1157 void cxgbe_nm_detach(struct vi_info *); 1158 void service_nm_rxq(struct sge_nm_rxq *); 1159 #endif 1160 1161 /* t4_sge.c */ 1162 void t4_sge_modload(void); 1163 void t4_sge_modunload(void); 1164 uint64_t t4_sge_extfree_refs(void); 1165 void t4_tweak_chip_settings(struct adapter *); 1166 int t4_read_chip_settings(struct adapter *); 1167 int t4_create_dma_tag(struct adapter *); 1168 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1169 struct sysctl_oid_list *); 1170 int t4_destroy_dma_tag(struct adapter *); 1171 int t4_setup_adapter_queues(struct adapter *); 1172 int t4_teardown_adapter_queues(struct adapter *); 1173 int t4_setup_vi_queues(struct vi_info *); 1174 int t4_teardown_vi_queues(struct vi_info *); 1175 void t4_intr_all(void *); 1176 void t4_intr(void *); 1177 #ifdef DEV_NETMAP 1178 void t4_nm_intr(void *); 1179 void t4_vi_intr(void *); 1180 #endif 1181 void t4_intr_err(void *); 1182 void t4_intr_evt(void *); 1183 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1184 void t4_update_fl_bufsize(struct ifnet *); 1185 struct mbuf *alloc_wr_mbuf(int, int); 1186 int parse_pkt(struct adapter *, struct mbuf **); 1187 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1188 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1189 int tnl_cong(struct port_info *, int); 1190 void t4_register_an_handler(an_handler_t); 1191 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1192 void t4_register_cpl_handler(int, cpl_handler_t); 1193 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1194 #ifdef RATELIMIT 1195 int ethofld_transmit(struct ifnet *, struct mbuf *); 1196 void send_etid_flush_wr(struct cxgbe_snd_tag *); 1197 #endif 1198 1199 /* t4_tracer.c */ 1200 struct t4_tracer; 1201 void t4_tracer_modload(void); 1202 void t4_tracer_modunload(void); 1203 void t4_tracer_port_detach(struct adapter *); 1204 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1205 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1206 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1207 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1208 1209 /* t4_sched.c */ 1210 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1211 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1212 int t4_init_tx_sched(struct adapter *); 1213 int t4_free_tx_sched(struct adapter *); 1214 void t4_update_tx_sched(struct adapter *); 1215 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1216 void t4_release_cl_rl(struct adapter *, int, int); 1217 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1218 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1219 #ifdef RATELIMIT 1220 void t4_init_etid_table(struct adapter *); 1221 void t4_free_etid_table(struct adapter *); 1222 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int); 1223 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1224 struct m_snd_tag **); 1225 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1226 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1227 void cxgbe_snd_tag_free(struct m_snd_tag *); 1228 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *); 1229 #endif 1230 1231 /* t4_filter.c */ 1232 int get_filter_mode(struct adapter *, uint32_t *); 1233 int set_filter_mode(struct adapter *, uint32_t); 1234 int get_filter(struct adapter *, struct t4_filter *); 1235 int set_filter(struct adapter *, struct t4_filter *); 1236 int del_filter(struct adapter *, struct t4_filter *); 1237 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1238 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1239 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1240 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1241 void free_hftid_hash(struct tid_info *); 1242 1243 static inline struct wrqe * 1244 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1245 { 1246 int len = offsetof(struct wrqe, wr) + wr_len; 1247 struct wrqe *wr; 1248 1249 wr = malloc(len, M_CXGBE, M_NOWAIT); 1250 if (__predict_false(wr == NULL)) 1251 return (NULL); 1252 wr->wr_len = wr_len; 1253 wr->wrq = wrq; 1254 return (wr); 1255 } 1256 1257 static inline void * 1258 wrtod(struct wrqe *wr) 1259 { 1260 return (&wr->wr[0]); 1261 } 1262 1263 static inline void 1264 free_wrqe(struct wrqe *wr) 1265 { 1266 free(wr, M_CXGBE); 1267 } 1268 1269 static inline void 1270 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1271 { 1272 struct sge_wrq *wrq = wr->wrq; 1273 1274 TXQ_LOCK(wrq); 1275 t4_wrq_tx_locked(sc, wrq, wr); 1276 TXQ_UNLOCK(wrq); 1277 } 1278 1279 static inline int 1280 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1281 int len) 1282 { 1283 1284 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1285 } 1286 1287 static inline int 1288 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1289 const uint32_t *val, int len) 1290 { 1291 1292 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1293 } 1294 #endif 1295