1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "firmware/t4fw_interface.h" 58 59 MALLOC_DECLARE(M_CXGBE); 60 #define CXGBE_UNIMPLEMENTED(s) \ 61 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 62 63 #if defined(__i386__) || defined(__amd64__) 64 static __inline void 65 prefetch(void *x) 66 { 67 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 68 } 69 #else 70 #define prefetch(x) 71 #endif 72 73 #ifndef SYSCTL_ADD_UQUAD 74 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 75 #define sysctl_handle_64 sysctl_handle_quad 76 #define CTLTYPE_U64 CTLTYPE_QUAD 77 #endif 78 79 #if (__FreeBSD_version >= 900030) || \ 80 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 81 #define SBUF_DRAIN 1 82 #endif 83 84 #ifdef __amd64__ 85 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 86 static __inline uint64_t 87 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 88 bus_size_t offset) 89 { 90 KASSERT(tag == X86_BUS_SPACE_MEM, 91 ("%s: can only handle mem space", __func__)); 92 93 return (*(volatile uint64_t *)(handle + offset)); 94 } 95 96 static __inline void 97 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 98 bus_size_t offset, uint64_t value) 99 { 100 KASSERT(tag == X86_BUS_SPACE_MEM, 101 ("%s: can only handle mem space", __func__)); 102 103 *(volatile uint64_t *)(bsh + offset) = value; 104 } 105 #else 106 static __inline uint64_t 107 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 108 bus_size_t offset) 109 { 110 return (uint64_t)bus_space_read_4(tag, handle, offset) + 111 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 112 } 113 114 static __inline void 115 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 116 bus_size_t offset, uint64_t value) 117 { 118 bus_space_write_4(tag, bsh, offset, value); 119 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 120 } 121 #endif 122 123 struct adapter; 124 typedef struct adapter adapter_t; 125 126 enum { 127 FW_IQ_QSIZE = 256, 128 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 129 130 RX_IQ_QSIZE = 1024, 131 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 132 133 EQ_ESIZE = 64, /* All egress queues use this entry size */ 134 135 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 136 #if MJUMPAGESIZE != MCLBYTES 137 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 138 #else 139 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 140 #endif 141 CL_METADATA_SIZE = CACHE_LINE_SIZE, 142 143 CTRL_EQ_QSIZE = 128, 144 145 TX_EQ_QSIZE = 1024, 146 TX_SGL_SEGS = 36, 147 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 148 }; 149 150 enum { 151 /* adapter intr_type */ 152 INTR_INTX = (1 << 0), 153 INTR_MSI = (1 << 1), 154 INTR_MSIX = (1 << 2) 155 }; 156 157 enum { 158 /* flags understood by begin_synchronized_op */ 159 HOLD_LOCK = (1 << 0), 160 SLEEP_OK = (1 << 1), 161 INTR_OK = (1 << 2), 162 163 /* flags understood by end_synchronized_op */ 164 LOCK_HELD = HOLD_LOCK, 165 }; 166 167 enum { 168 /* adapter flags */ 169 FULL_INIT_DONE = (1 << 0), 170 FW_OK = (1 << 1), 171 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 172 MASTER_PF = (1 << 3), 173 ADAP_SYSCTL_CTX = (1 << 4), 174 TOM_INIT_DONE = (1 << 5), 175 BUF_PACKING_OK = (1 << 6), 176 177 CXGBE_BUSY = (1 << 9), 178 179 /* port flags */ 180 DOOMED = (1 << 0), 181 PORT_INIT_DONE = (1 << 1), 182 PORT_SYSCTL_CTX = (1 << 2), 183 HAS_TRACEQ = (1 << 3), 184 }; 185 186 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 187 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 188 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 189 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 190 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 191 192 struct port_info { 193 device_t dev; 194 struct adapter *adapter; 195 196 struct ifnet *ifp; 197 struct ifmedia media; 198 199 struct mtx pi_lock; 200 char lockname[16]; 201 unsigned long flags; 202 int if_flags; 203 204 uint16_t *rss; 205 uint16_t viid; 206 int16_t xact_addr_filt;/* index of exact MAC address filter */ 207 uint16_t rss_size; /* size of VI's RSS table slice */ 208 uint8_t lport; /* associated offload logical port */ 209 int8_t mdio_addr; 210 uint8_t port_type; 211 uint8_t mod_type; 212 uint8_t port_id; 213 uint8_t tx_chan; 214 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 215 216 /* These need to be int as they are used in sysctl */ 217 int ntxq; /* # of tx queues */ 218 int first_txq; /* index of first tx queue */ 219 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 220 int nrxq; /* # of rx queues */ 221 int first_rxq; /* index of first rx queue */ 222 #ifdef TCP_OFFLOAD 223 int nofldtxq; /* # of offload tx queues */ 224 int first_ofld_txq; /* index of first offload tx queue */ 225 int nofldrxq; /* # of offload rx queues */ 226 int first_ofld_rxq; /* index of first offload rx queue */ 227 #endif 228 int tmr_idx; 229 int pktc_idx; 230 int qsize_rxq; 231 int qsize_txq; 232 233 int linkdnrc; 234 struct link_config link_cfg; 235 struct port_stats stats; 236 237 eventhandler_tag vlan_c; 238 239 struct callout tick; 240 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 241 242 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 243 }; 244 245 /* Where the cluster came from, how it has been carved up. */ 246 struct cluster_layout { 247 int8_t zidx; 248 int8_t hwidx; 249 uint16_t region1; /* mbufs laid out within this region */ 250 /* region2 is the DMA region */ 251 uint16_t region3; /* cluster_metadata within this region */ 252 }; 253 254 struct cluster_metadata { 255 u_int refcount; 256 #ifdef INVARIANTS 257 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 258 #endif 259 }; 260 261 struct fl_sdesc { 262 caddr_t cl; 263 uint8_t nmbuf; 264 struct cluster_layout cll; 265 }; 266 267 struct tx_desc { 268 __be64 flit[8]; 269 }; 270 271 struct tx_map { 272 struct mbuf *m; 273 bus_dmamap_t map; 274 }; 275 276 /* DMA maps used for tx */ 277 struct tx_maps { 278 struct tx_map *maps; 279 uint32_t map_total; /* # of DMA maps */ 280 uint32_t map_pidx; /* next map to be used */ 281 uint32_t map_cidx; /* reclaimed up to this index */ 282 uint32_t map_avail; /* # of available maps */ 283 }; 284 285 struct tx_sdesc { 286 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 287 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 288 }; 289 290 enum { 291 /* iq flags */ 292 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 293 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 294 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 295 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 296 297 /* iq state */ 298 IQS_DISABLED = 0, 299 IQS_BUSY = 1, 300 IQS_IDLE = 2, 301 }; 302 303 /* 304 * Ingress Queue: T4 is producer, driver is consumer. 305 */ 306 struct sge_iq { 307 bus_dma_tag_t desc_tag; 308 bus_dmamap_t desc_map; 309 bus_addr_t ba; /* bus address of descriptor ring */ 310 uint32_t flags; 311 uint16_t abs_id; /* absolute SGE id for the iq */ 312 int8_t intr_pktc_idx; /* packet count threshold index */ 313 int8_t pad0; 314 __be64 *desc; /* KVA of descriptor ring */ 315 316 volatile int state; 317 struct adapter *adapter; 318 const __be64 *cdesc; /* current descriptor */ 319 uint8_t gen; /* generation bit */ 320 uint8_t intr_params; /* interrupt holdoff parameters */ 321 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 322 uint8_t esize; /* size (bytes) of each entry in the queue */ 323 uint16_t qsize; /* size (# of entries) of the queue */ 324 uint16_t cidx; /* consumer index */ 325 uint16_t cntxt_id; /* SGE context id for the iq */ 326 327 STAILQ_ENTRY(sge_iq) link; 328 }; 329 330 enum { 331 EQ_CTRL = 1, 332 EQ_ETH = 2, 333 #ifdef TCP_OFFLOAD 334 EQ_OFLD = 3, 335 #endif 336 337 /* eq flags */ 338 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 339 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 340 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 341 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 342 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 343 }; 344 345 /* Listed in order of preference. Update t4_sysctls too if you change these */ 346 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 347 348 /* 349 * Egress Queue: driver is producer, T4 is consumer. 350 * 351 * Note: A free list is an egress queue (driver produces the buffers and T4 352 * consumes them) but it's special enough to have its own struct (see sge_fl). 353 */ 354 struct sge_eq { 355 unsigned int flags; /* MUST be first */ 356 unsigned int cntxt_id; /* SGE context id for the eq */ 357 bus_dma_tag_t desc_tag; 358 bus_dmamap_t desc_map; 359 char lockname[16]; 360 struct mtx eq_lock; 361 362 struct tx_desc *desc; /* KVA of descriptor ring */ 363 bus_addr_t ba; /* bus address of descriptor ring */ 364 struct sge_qstat *spg; /* status page, for convenience */ 365 int doorbells; 366 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 367 u_int udb_qid; /* relative qid within the doorbell page */ 368 uint16_t cap; /* max # of desc, for convenience */ 369 uint16_t avail; /* available descriptors, for convenience */ 370 uint16_t qsize; /* size (# of entries) of the queue */ 371 uint16_t cidx; /* consumer idx (desc idx) */ 372 uint16_t pidx; /* producer idx (desc idx) */ 373 uint16_t pending; /* # of descriptors used since last doorbell */ 374 uint16_t iqid; /* iq that gets egr_update for the eq */ 375 uint8_t tx_chan; /* tx channel used by the eq */ 376 struct task tx_task; 377 struct callout tx_callout; 378 379 /* stats */ 380 381 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 382 uint32_t unstalled; /* recovered from stall */ 383 }; 384 385 struct sw_zone_info { 386 uma_zone_t zone; /* zone that this cluster comes from */ 387 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 388 int type; /* EXT_xxx type of the cluster */ 389 int8_t head_hwidx; 390 int8_t tail_hwidx; 391 }; 392 393 struct hw_buf_info { 394 int8_t zidx; /* backpointer to zone; -ve means unused */ 395 int8_t next; /* next hwidx for this zone; -1 means no more */ 396 int size; 397 }; 398 399 enum { 400 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 401 FL_DOOMED = (1 << 1), /* about to be destroyed */ 402 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 403 }; 404 405 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 406 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 407 408 struct sge_fl { 409 bus_dma_tag_t desc_tag; 410 bus_dmamap_t desc_map; 411 struct cluster_layout cll_def; /* default refill zone, layout */ 412 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 413 struct mtx fl_lock; 414 char lockname[16]; 415 int flags; 416 417 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 418 bus_addr_t ba; /* bus address of descriptor ring */ 419 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 420 uint32_t cap; /* max # of buffers, for convenience */ 421 uint16_t qsize; /* size (# of entries) of the queue */ 422 uint16_t cntxt_id; /* SGE context id for the freelist */ 423 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 424 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 425 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 426 uint32_t needed; /* # of buffers needed to fill up fl. */ 427 uint32_t lowat; /* # of buffers <= this means fl needs help */ 428 uint32_t pending; /* # of bufs allocated since last doorbell */ 429 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 430 431 struct mbuf *m0; 432 struct mbuf **pnext; 433 u_int remaining; 434 435 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 436 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 437 uint64_t cl_allocated; /* # of clusters allocated */ 438 uint64_t cl_recycled; /* # of clusters recycled */ 439 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 440 }; 441 442 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 443 struct sge_txq { 444 struct sge_eq eq; /* MUST be first */ 445 446 struct ifnet *ifp; /* the interface this txq belongs to */ 447 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 448 struct buf_ring *br; /* tx buffer ring */ 449 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 450 struct mbuf *m; /* held up due to temporary resource shortage */ 451 452 struct tx_maps txmaps; 453 454 /* stats for common events first */ 455 456 uint64_t txcsum; /* # of times hardware assisted with checksum */ 457 uint64_t tso_wrs; /* # of TSO work requests */ 458 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 459 uint64_t imm_wrs; /* # of work requests with immediate data */ 460 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 461 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 462 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 463 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 464 465 /* stats for not-that-common events */ 466 467 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 468 uint32_t no_desc; /* out of hardware descriptors */ 469 } __aligned(CACHE_LINE_SIZE); 470 471 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 472 struct sge_rxq { 473 struct sge_iq iq; /* MUST be first */ 474 struct sge_fl fl; /* MUST follow iq */ 475 476 struct ifnet *ifp; /* the interface this rxq belongs to */ 477 #if defined(INET) || defined(INET6) 478 struct lro_ctrl lro; /* LRO state */ 479 #endif 480 481 /* stats for common events first */ 482 483 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 484 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 485 486 /* stats for not-that-common events */ 487 488 } __aligned(CACHE_LINE_SIZE); 489 490 static inline struct sge_rxq * 491 iq_to_rxq(struct sge_iq *iq) 492 { 493 494 return (__containerof(iq, struct sge_rxq, iq)); 495 } 496 497 498 #ifdef TCP_OFFLOAD 499 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 500 struct sge_ofld_rxq { 501 struct sge_iq iq; /* MUST be first */ 502 struct sge_fl fl; /* MUST follow iq */ 503 } __aligned(CACHE_LINE_SIZE); 504 505 static inline struct sge_ofld_rxq * 506 iq_to_ofld_rxq(struct sge_iq *iq) 507 { 508 509 return (__containerof(iq, struct sge_ofld_rxq, iq)); 510 } 511 #endif 512 513 struct wrqe { 514 STAILQ_ENTRY(wrqe) link; 515 struct sge_wrq *wrq; 516 int wr_len; 517 uint64_t wr[] __aligned(16); 518 }; 519 520 /* 521 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 522 * and offload tx queues are of this type. 523 */ 524 struct sge_wrq { 525 struct sge_eq eq; /* MUST be first */ 526 527 struct adapter *adapter; 528 529 /* List of WRs held up due to lack of tx descriptors */ 530 STAILQ_HEAD(, wrqe) wr_list; 531 532 /* stats for common events first */ 533 534 uint64_t tx_wrs; /* # of tx work requests */ 535 536 /* stats for not-that-common events */ 537 538 uint32_t no_desc; /* out of hardware descriptors */ 539 } __aligned(CACHE_LINE_SIZE); 540 541 struct sge { 542 int timer_val[SGE_NTIMERS]; 543 int counter_val[SGE_NCOUNTERS]; 544 int fl_starve_threshold; 545 int fl_starve_threshold2; 546 int eq_s_qpp; 547 int iq_s_qpp; 548 549 int nrxq; /* total # of Ethernet rx queues */ 550 int ntxq; /* total # of Ethernet tx tx queues */ 551 #ifdef TCP_OFFLOAD 552 int nofldrxq; /* total # of TOE rx queues */ 553 int nofldtxq; /* total # of TOE tx queues */ 554 #endif 555 int niq; /* total # of ingress queues */ 556 int neq; /* total # of egress queues */ 557 558 struct sge_iq fwq; /* Firmware event queue */ 559 struct sge_wrq mgmtq; /* Management queue (control queue) */ 560 struct sge_wrq *ctrlq; /* Control queues */ 561 struct sge_txq *txq; /* NIC tx queues */ 562 struct sge_rxq *rxq; /* NIC rx queues */ 563 #ifdef TCP_OFFLOAD 564 struct sge_wrq *ofld_txq; /* TOE tx queues */ 565 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 566 #endif 567 568 uint16_t iq_start; 569 int eq_start; 570 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 571 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 572 573 int pack_boundary; 574 int8_t safe_hwidx1; /* may not have room for metadata */ 575 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 576 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 577 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 578 }; 579 580 struct rss_header; 581 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 582 struct mbuf *); 583 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 584 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 585 586 struct adapter { 587 SLIST_ENTRY(adapter) link; 588 device_t dev; 589 struct cdev *cdev; 590 591 /* PCIe register resources */ 592 int regs_rid; 593 struct resource *regs_res; 594 int msix_rid; 595 struct resource *msix_res; 596 bus_space_handle_t bh; 597 bus_space_tag_t bt; 598 bus_size_t mmio_len; 599 int udbs_rid; 600 struct resource *udbs_res; 601 volatile uint8_t *udbs_base; 602 603 unsigned int pf; 604 unsigned int mbox; 605 606 /* Interrupt information */ 607 int intr_type; 608 int intr_count; 609 struct irq { 610 struct resource *res; 611 int rid; 612 void *tag; 613 } *irq; 614 615 bus_dma_tag_t dmat; /* Parent DMA tag */ 616 617 struct sge sge; 618 int lro_timeout; 619 620 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 621 struct port_info *port[MAX_NPORTS]; 622 uint8_t chan_map[NCHAN]; 623 624 #ifdef TCP_OFFLOAD 625 void *tom_softc; /* (struct tom_data *) */ 626 struct tom_tunables tt; 627 void *iwarp_softc; /* (struct c4iw_dev *) */ 628 #endif 629 struct l2t_data *l2t; /* L2 table */ 630 struct tid_info tids; 631 632 int doorbells; 633 int open_device_map; 634 #ifdef TCP_OFFLOAD 635 int offload_map; 636 #endif 637 int flags; 638 639 char ifp_lockname[16]; 640 struct mtx ifp_lock; 641 struct ifnet *ifp; /* tracer ifp */ 642 struct ifmedia media; 643 int traceq; /* iq used by all tracers, -1 if none */ 644 int tracer_valid; /* bitmap of valid tracers */ 645 int tracer_enabled; /* bitmap of enabled tracers */ 646 647 char fw_version[32]; 648 char cfg_file[32]; 649 u_int cfcsum; 650 struct adapter_params params; 651 struct t4_virt_res vres; 652 653 uint16_t linkcaps; 654 uint16_t niccaps; 655 uint16_t toecaps; 656 uint16_t rdmacaps; 657 uint16_t iscsicaps; 658 uint16_t fcoecaps; 659 660 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 661 662 struct mtx sc_lock; 663 char lockname[16]; 664 665 /* Starving free lists */ 666 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 667 TAILQ_HEAD(, sge_fl) sfl; 668 struct callout sfl_callout; 669 670 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 671 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 672 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 673 674 #ifdef INVARIANTS 675 const char *last_op; 676 const void *last_op_thr; 677 #endif 678 679 int sc_do_rxcopy; 680 }; 681 682 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 683 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 684 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 685 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 686 687 /* XXX: not bulletproof, but much better than nothing */ 688 #define ASSERT_SYNCHRONIZED_OP(sc) \ 689 KASSERT(IS_BUSY(sc) && \ 690 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 691 ("%s: operation not synchronized.", __func__)) 692 693 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 694 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 695 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 696 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 697 698 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 699 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 700 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 701 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 702 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 703 704 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 705 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 706 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 707 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 708 709 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 710 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 711 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 712 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 713 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 714 715 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 716 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 717 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 718 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 719 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 720 721 #define for_each_txq(pi, iter, q) \ 722 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 723 iter < pi->ntxq; ++iter, ++q) 724 #define for_each_rxq(pi, iter, q) \ 725 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 726 iter < pi->nrxq; ++iter, ++q) 727 #define for_each_ofld_txq(pi, iter, q) \ 728 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 729 iter < pi->nofldtxq; ++iter, ++q) 730 #define for_each_ofld_rxq(pi, iter, q) \ 731 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 732 iter < pi->nofldrxq; ++iter, ++q) 733 734 /* One for errors, one for firmware events */ 735 #define T4_EXTRA_INTR 2 736 737 static inline uint32_t 738 t4_read_reg(struct adapter *sc, uint32_t reg) 739 { 740 741 return bus_space_read_4(sc->bt, sc->bh, reg); 742 } 743 744 static inline void 745 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 746 { 747 748 bus_space_write_4(sc->bt, sc->bh, reg, val); 749 } 750 751 static inline uint64_t 752 t4_read_reg64(struct adapter *sc, uint32_t reg) 753 { 754 755 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 756 } 757 758 static inline void 759 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 760 { 761 762 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 763 } 764 765 static inline void 766 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 767 { 768 769 *val = pci_read_config(sc->dev, reg, 1); 770 } 771 772 static inline void 773 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 774 { 775 776 pci_write_config(sc->dev, reg, val, 1); 777 } 778 779 static inline void 780 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 781 { 782 783 *val = pci_read_config(sc->dev, reg, 2); 784 } 785 786 static inline void 787 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 788 { 789 790 pci_write_config(sc->dev, reg, val, 2); 791 } 792 793 static inline void 794 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 795 { 796 797 *val = pci_read_config(sc->dev, reg, 4); 798 } 799 800 static inline void 801 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 802 { 803 804 pci_write_config(sc->dev, reg, val, 4); 805 } 806 807 static inline struct port_info * 808 adap2pinfo(struct adapter *sc, int idx) 809 { 810 811 return (sc->port[idx]); 812 } 813 814 static inline void 815 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 816 { 817 818 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 819 } 820 821 static inline bool 822 is_10G_port(const struct port_info *pi) 823 { 824 825 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 826 } 827 828 static inline bool 829 is_40G_port(const struct port_info *pi) 830 { 831 832 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 833 } 834 835 static inline int 836 tx_resume_threshold(struct sge_eq *eq) 837 { 838 839 return (eq->qsize / 4); 840 } 841 842 /* t4_main.c */ 843 void t4_tx_task(void *, int); 844 void t4_tx_callout(void *); 845 int t4_os_find_pci_capability(struct adapter *, int); 846 int t4_os_pci_save_state(struct adapter *); 847 int t4_os_pci_restore_state(struct adapter *); 848 void t4_os_portmod_changed(const struct adapter *, int); 849 void t4_os_link_changed(struct adapter *, int, int, int); 850 void t4_iterate(void (*)(struct adapter *, void *), void *); 851 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 852 int t4_register_an_handler(struct adapter *, an_handler_t); 853 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 854 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 855 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 856 void end_synchronized_op(struct adapter *, int); 857 858 /* t4_sge.c */ 859 void t4_sge_modload(void); 860 void t4_init_sge_cpl_handlers(struct adapter *); 861 void t4_tweak_chip_settings(struct adapter *); 862 int t4_read_chip_settings(struct adapter *); 863 int t4_create_dma_tag(struct adapter *); 864 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 865 struct sysctl_oid_list *); 866 int t4_destroy_dma_tag(struct adapter *); 867 int t4_setup_adapter_queues(struct adapter *); 868 int t4_teardown_adapter_queues(struct adapter *); 869 int t4_setup_port_queues(struct port_info *); 870 int t4_teardown_port_queues(struct port_info *); 871 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 872 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 873 void t4_intr_all(void *); 874 void t4_intr(void *); 875 void t4_intr_err(void *); 876 void t4_intr_evt(void *); 877 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 878 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 879 void t4_update_fl_bufsize(struct ifnet *); 880 int can_resume_tx(struct sge_eq *); 881 882 /* t4_tracer.c */ 883 struct t4_tracer; 884 void t4_tracer_modload(void); 885 void t4_tracer_modunload(void); 886 void t4_tracer_port_detach(struct adapter *); 887 int t4_get_tracer(struct adapter *, struct t4_tracer *); 888 int t4_set_tracer(struct adapter *, struct t4_tracer *); 889 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 890 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 891 892 static inline struct wrqe * 893 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 894 { 895 int len = offsetof(struct wrqe, wr) + wr_len; 896 struct wrqe *wr; 897 898 wr = malloc(len, M_CXGBE, M_NOWAIT); 899 if (__predict_false(wr == NULL)) 900 return (NULL); 901 wr->wr_len = wr_len; 902 wr->wrq = wrq; 903 return (wr); 904 } 905 906 static inline void * 907 wrtod(struct wrqe *wr) 908 { 909 return (&wr->wr[0]); 910 } 911 912 static inline void 913 free_wrqe(struct wrqe *wr) 914 { 915 free(wr, M_CXGBE); 916 } 917 918 static inline void 919 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 920 { 921 struct sge_wrq *wrq = wr->wrq; 922 923 TXQ_LOCK(wrq); 924 t4_wrq_tx_locked(sc, wrq, wr); 925 TXQ_UNLOCK(wrq); 926 } 927 928 #endif 929