1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/malloc.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <machine/bus.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <net/ethernet.h> 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <netinet/in.h> 48 #include <netinet/tcp_lro.h> 49 50 #include "offload.h" 51 #include "firmware/t4fw_interface.h" 52 53 MALLOC_DECLARE(M_CXGBE); 54 #define CXGBE_UNIMPLEMENTED(s) \ 55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56 57 #if defined(__i386__) || defined(__amd64__) 58 static __inline void 59 prefetch(void *x) 60 { 61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62 } 63 #else 64 #define prefetch(x) 65 #endif 66 67 #ifndef SYSCTL_ADD_UQUAD 68 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 69 #define sysctl_handle_64 sysctl_handle_quad 70 #define CTLTYPE_U64 CTLTYPE_QUAD 71 #endif 72 73 #if (__FreeBSD_version >= 900030) || \ 74 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 75 #define SBUF_DRAIN 1 76 #endif 77 78 #ifdef __amd64__ 79 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 80 static __inline uint64_t 81 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 82 bus_size_t offset) 83 { 84 KASSERT(tag == X86_BUS_SPACE_MEM, 85 ("%s: can only handle mem space", __func__)); 86 87 return (*(volatile uint64_t *)(handle + offset)); 88 } 89 90 static __inline void 91 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 92 bus_size_t offset, uint64_t value) 93 { 94 KASSERT(tag == X86_BUS_SPACE_MEM, 95 ("%s: can only handle mem space", __func__)); 96 97 *(volatile uint64_t *)(bsh + offset) = value; 98 } 99 #else 100 static __inline uint64_t 101 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 102 bus_size_t offset) 103 { 104 return (uint64_t)bus_space_read_4(tag, handle, offset) + 105 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 106 } 107 108 static __inline void 109 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 110 bus_size_t offset, uint64_t value) 111 { 112 bus_space_write_4(tag, bsh, offset, value); 113 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 114 } 115 #endif 116 117 struct adapter; 118 typedef struct adapter adapter_t; 119 120 enum { 121 FW_IQ_QSIZE = 256, 122 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 123 124 RX_IQ_QSIZE = 1024, 125 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 126 127 EQ_ESIZE = 64, /* All egress queues use this entry size */ 128 129 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 130 #if MJUMPAGESIZE != MCLBYTES 131 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 132 #else 133 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 134 #endif 135 OFLD_BUF_SIZE = MJUM16BYTES, /* size of fl buffer for TOE rxq */ 136 137 CTRL_EQ_QSIZE = 128, 138 139 TX_EQ_QSIZE = 1024, 140 TX_SGL_SEGS = 36, 141 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 142 }; 143 144 enum { 145 /* adapter intr_type */ 146 INTR_INTX = (1 << 0), 147 INTR_MSI = (1 << 1), 148 INTR_MSIX = (1 << 2) 149 }; 150 151 enum { 152 /* flags understood by begin_synchronized_op */ 153 HOLD_LOCK = (1 << 0), 154 SLEEP_OK = (1 << 1), 155 INTR_OK = (1 << 2), 156 157 /* flags understood by end_synchronized_op */ 158 LOCK_HELD = HOLD_LOCK, 159 }; 160 161 enum { 162 /* adapter flags */ 163 FULL_INIT_DONE = (1 << 0), 164 FW_OK = (1 << 1), 165 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 166 MASTER_PF = (1 << 3), 167 ADAP_SYSCTL_CTX = (1 << 4), 168 TOM_INIT_DONE = (1 << 5), 169 170 CXGBE_BUSY = (1 << 9), 171 172 /* port flags */ 173 DOOMED = (1 << 0), 174 PORT_INIT_DONE = (1 << 1), 175 PORT_SYSCTL_CTX = (1 << 2), 176 }; 177 178 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 179 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 180 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 181 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 182 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 183 184 struct port_info { 185 device_t dev; 186 struct adapter *adapter; 187 188 struct ifnet *ifp; 189 struct ifmedia media; 190 191 struct mtx pi_lock; 192 char lockname[16]; 193 unsigned long flags; 194 int if_flags; 195 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint8_t lport; /* associated offload logical port */ 200 int8_t mdio_addr; 201 uint8_t port_type; 202 uint8_t mod_type; 203 uint8_t port_id; 204 uint8_t tx_chan; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int nrxq; /* # of rx queues */ 210 int first_rxq; /* index of first rx queue */ 211 #ifdef TCP_OFFLOAD 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 #endif 217 int tmr_idx; 218 int pktc_idx; 219 int qsize_rxq; 220 int qsize_txq; 221 222 struct link_config link_cfg; 223 struct port_stats stats; 224 225 eventhandler_tag vlan_c; 226 227 struct callout tick; 228 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 229 230 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 231 }; 232 233 struct fl_sdesc { 234 struct mbuf *m; 235 bus_dmamap_t map; 236 caddr_t cl; 237 uint8_t tag_idx; /* the sc->fl_tag this map comes from */ 238 #ifdef INVARIANTS 239 __be64 ba_tag; 240 #endif 241 }; 242 243 struct tx_desc { 244 __be64 flit[8]; 245 }; 246 247 struct tx_map { 248 struct mbuf *m; 249 bus_dmamap_t map; 250 }; 251 252 /* DMA maps used for tx */ 253 struct tx_maps { 254 struct tx_map *maps; 255 uint32_t map_total; /* # of DMA maps */ 256 uint32_t map_pidx; /* next map to be used */ 257 uint32_t map_cidx; /* reclaimed up to this index */ 258 uint32_t map_avail; /* # of available maps */ 259 }; 260 261 struct tx_sdesc { 262 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 263 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 264 }; 265 266 enum { 267 /* iq flags */ 268 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 269 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 270 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 271 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 272 273 /* iq state */ 274 IQS_DISABLED = 0, 275 IQS_BUSY = 1, 276 IQS_IDLE = 2, 277 }; 278 279 /* 280 * Ingress Queue: T4 is producer, driver is consumer. 281 */ 282 struct sge_iq { 283 bus_dma_tag_t desc_tag; 284 bus_dmamap_t desc_map; 285 bus_addr_t ba; /* bus address of descriptor ring */ 286 uint32_t flags; 287 uint16_t abs_id; /* absolute SGE id for the iq */ 288 int8_t intr_pktc_idx; /* packet count threshold index */ 289 int8_t pad0; 290 __be64 *desc; /* KVA of descriptor ring */ 291 292 volatile int state; 293 struct adapter *adapter; 294 const __be64 *cdesc; /* current descriptor */ 295 uint8_t gen; /* generation bit */ 296 uint8_t intr_params; /* interrupt holdoff parameters */ 297 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 298 uint8_t esize; /* size (bytes) of each entry in the queue */ 299 uint16_t qsize; /* size (# of entries) of the queue */ 300 uint16_t cidx; /* consumer index */ 301 uint16_t cntxt_id; /* SGE context id for the iq */ 302 303 STAILQ_ENTRY(sge_iq) link; 304 }; 305 306 enum { 307 EQ_CTRL = 1, 308 EQ_ETH = 2, 309 #ifdef TCP_OFFLOAD 310 EQ_OFLD = 3, 311 #endif 312 313 /* eq flags */ 314 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 315 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 316 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 317 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 318 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 319 }; 320 321 /* Listed in order of preference. Update t4_sysctls too if you change these */ 322 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 323 324 /* 325 * Egress Queue: driver is producer, T4 is consumer. 326 * 327 * Note: A free list is an egress queue (driver produces the buffers and T4 328 * consumes them) but it's special enough to have its own struct (see sge_fl). 329 */ 330 struct sge_eq { 331 unsigned int flags; /* MUST be first */ 332 unsigned int cntxt_id; /* SGE context id for the eq */ 333 bus_dma_tag_t desc_tag; 334 bus_dmamap_t desc_map; 335 char lockname[16]; 336 struct mtx eq_lock; 337 338 struct tx_desc *desc; /* KVA of descriptor ring */ 339 bus_addr_t ba; /* bus address of descriptor ring */ 340 struct sge_qstat *spg; /* status page, for convenience */ 341 int doorbells; 342 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 343 u_int udb_qid; /* relative qid within the doorbell page */ 344 uint16_t cap; /* max # of desc, for convenience */ 345 uint16_t avail; /* available descriptors, for convenience */ 346 uint16_t qsize; /* size (# of entries) of the queue */ 347 uint16_t cidx; /* consumer idx (desc idx) */ 348 uint16_t pidx; /* producer idx (desc idx) */ 349 uint16_t pending; /* # of descriptors used since last doorbell */ 350 uint16_t iqid; /* iq that gets egr_update for the eq */ 351 uint8_t tx_chan; /* tx channel used by the eq */ 352 struct task tx_task; 353 struct callout tx_callout; 354 355 /* stats */ 356 357 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 358 uint32_t unstalled; /* recovered from stall */ 359 }; 360 361 enum { 362 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 363 FL_DOOMED = (1 << 1), /* about to be destroyed */ 364 }; 365 366 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 367 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 368 369 struct sge_fl { 370 bus_dma_tag_t desc_tag; 371 bus_dmamap_t desc_map; 372 bus_dma_tag_t tag[FL_BUF_SIZES]; 373 uint8_t tag_idx; 374 struct mtx fl_lock; 375 char lockname[16]; 376 int flags; 377 378 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 379 bus_addr_t ba; /* bus address of descriptor ring */ 380 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 381 uint32_t cap; /* max # of buffers, for convenience */ 382 uint16_t qsize; /* size (# of entries) of the queue */ 383 uint16_t cntxt_id; /* SGE context id for the freelist */ 384 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 385 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 386 uint32_t needed; /* # of buffers needed to fill up fl. */ 387 uint32_t lowat; /* # of buffers <= this means fl needs help */ 388 uint32_t pending; /* # of bufs allocated since last doorbell */ 389 unsigned int dmamap_failed; 390 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 391 }; 392 393 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 394 struct sge_txq { 395 struct sge_eq eq; /* MUST be first */ 396 397 struct ifnet *ifp; /* the interface this txq belongs to */ 398 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 399 struct buf_ring *br; /* tx buffer ring */ 400 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 401 struct mbuf *m; /* held up due to temporary resource shortage */ 402 403 struct tx_maps txmaps; 404 405 /* stats for common events first */ 406 407 uint64_t txcsum; /* # of times hardware assisted with checksum */ 408 uint64_t tso_wrs; /* # of TSO work requests */ 409 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 410 uint64_t imm_wrs; /* # of work requests with immediate data */ 411 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 412 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 413 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 414 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 415 416 /* stats for not-that-common events */ 417 418 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 419 uint32_t no_desc; /* out of hardware descriptors */ 420 } __aligned(CACHE_LINE_SIZE); 421 422 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 423 struct sge_rxq { 424 struct sge_iq iq; /* MUST be first */ 425 struct sge_fl fl; /* MUST follow iq */ 426 427 struct ifnet *ifp; /* the interface this rxq belongs to */ 428 #if defined(INET) || defined(INET6) 429 struct lro_ctrl lro; /* LRO state */ 430 #endif 431 432 /* stats for common events first */ 433 434 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 435 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 436 437 /* stats for not-that-common events */ 438 439 } __aligned(CACHE_LINE_SIZE); 440 441 static inline struct sge_rxq * 442 iq_to_rxq(struct sge_iq *iq) 443 { 444 445 return (__containerof(iq, struct sge_rxq, iq)); 446 } 447 448 449 #ifdef TCP_OFFLOAD 450 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 451 struct sge_ofld_rxq { 452 struct sge_iq iq; /* MUST be first */ 453 struct sge_fl fl; /* MUST follow iq */ 454 } __aligned(CACHE_LINE_SIZE); 455 456 static inline struct sge_ofld_rxq * 457 iq_to_ofld_rxq(struct sge_iq *iq) 458 { 459 460 return (__containerof(iq, struct sge_ofld_rxq, iq)); 461 } 462 #endif 463 464 struct wrqe { 465 STAILQ_ENTRY(wrqe) link; 466 struct sge_wrq *wrq; 467 int wr_len; 468 uint64_t wr[] __aligned(16); 469 }; 470 471 /* 472 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 473 * and offload tx queues are of this type. 474 */ 475 struct sge_wrq { 476 struct sge_eq eq; /* MUST be first */ 477 478 struct adapter *adapter; 479 480 /* List of WRs held up due to lack of tx descriptors */ 481 STAILQ_HEAD(, wrqe) wr_list; 482 483 /* stats for common events first */ 484 485 uint64_t tx_wrs; /* # of tx work requests */ 486 487 /* stats for not-that-common events */ 488 489 uint32_t no_desc; /* out of hardware descriptors */ 490 } __aligned(CACHE_LINE_SIZE); 491 492 struct sge { 493 int timer_val[SGE_NTIMERS]; 494 int counter_val[SGE_NCOUNTERS]; 495 int fl_starve_threshold; 496 int s_qpp; 497 498 int nrxq; /* total # of Ethernet rx queues */ 499 int ntxq; /* total # of Ethernet tx tx queues */ 500 #ifdef TCP_OFFLOAD 501 int nofldrxq; /* total # of TOE rx queues */ 502 int nofldtxq; /* total # of TOE tx queues */ 503 #endif 504 int niq; /* total # of ingress queues */ 505 int neq; /* total # of egress queues */ 506 507 struct sge_iq fwq; /* Firmware event queue */ 508 struct sge_wrq mgmtq; /* Management queue (control queue) */ 509 struct sge_wrq *ctrlq; /* Control queues */ 510 struct sge_txq *txq; /* NIC tx queues */ 511 struct sge_rxq *rxq; /* NIC rx queues */ 512 #ifdef TCP_OFFLOAD 513 struct sge_wrq *ofld_txq; /* TOE tx queues */ 514 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 515 #endif 516 517 uint16_t iq_start; 518 int eq_start; 519 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 520 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 521 }; 522 523 struct rss_header; 524 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 525 struct mbuf *); 526 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 527 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 528 529 struct adapter { 530 SLIST_ENTRY(adapter) link; 531 device_t dev; 532 struct cdev *cdev; 533 534 /* PCIe register resources */ 535 int regs_rid; 536 struct resource *regs_res; 537 int msix_rid; 538 struct resource *msix_res; 539 bus_space_handle_t bh; 540 bus_space_tag_t bt; 541 bus_size_t mmio_len; 542 int udbs_rid; 543 struct resource *udbs_res; 544 volatile uint8_t *udbs_base; 545 546 unsigned int pf; 547 unsigned int mbox; 548 549 /* Interrupt information */ 550 int intr_type; 551 int intr_count; 552 struct irq { 553 struct resource *res; 554 int rid; 555 void *tag; 556 } *irq; 557 558 bus_dma_tag_t dmat; /* Parent DMA tag */ 559 560 struct sge sge; 561 562 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 563 struct port_info *port[MAX_NPORTS]; 564 uint8_t chan_map[NCHAN]; 565 uint32_t filter_mode; 566 567 #ifdef TCP_OFFLOAD 568 void *tom_softc; /* (struct tom_data *) */ 569 struct tom_tunables tt; 570 #endif 571 struct l2t_data *l2t; /* L2 table */ 572 struct tid_info tids; 573 574 int doorbells; 575 int open_device_map; 576 #ifdef TCP_OFFLOAD 577 int offload_map; 578 #endif 579 int flags; 580 581 char fw_version[32]; 582 char cfg_file[32]; 583 u_int cfcsum; 584 struct adapter_params params; 585 struct t4_virt_res vres; 586 587 uint16_t linkcaps; 588 uint16_t niccaps; 589 uint16_t toecaps; 590 uint16_t rdmacaps; 591 uint16_t iscsicaps; 592 uint16_t fcoecaps; 593 594 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 595 596 struct mtx sc_lock; 597 char lockname[16]; 598 599 /* Starving free lists */ 600 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 601 TAILQ_HEAD(, sge_fl) sfl; 602 struct callout sfl_callout; 603 604 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 605 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 606 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 607 608 #ifdef INVARIANTS 609 const char *last_op; 610 const void *last_op_thr; 611 #endif 612 }; 613 614 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 615 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 616 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 617 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 618 619 /* XXX: not bulletproof, but much better than nothing */ 620 #define ASSERT_SYNCHRONIZED_OP(sc) \ 621 KASSERT(IS_BUSY(sc) && \ 622 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 623 ("%s: operation not synchronized.", __func__)) 624 625 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 626 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 627 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 628 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 629 630 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 631 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 632 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 633 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 634 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 635 636 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 637 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 638 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 639 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 640 641 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 642 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 643 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 644 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 645 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 646 647 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 648 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 649 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 650 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 651 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 652 653 #define for_each_txq(pi, iter, q) \ 654 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 655 iter < pi->ntxq; ++iter, ++q) 656 #define for_each_rxq(pi, iter, q) \ 657 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 658 iter < pi->nrxq; ++iter, ++q) 659 #define for_each_ofld_txq(pi, iter, q) \ 660 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 661 iter < pi->nofldtxq; ++iter, ++q) 662 #define for_each_ofld_rxq(pi, iter, q) \ 663 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 664 iter < pi->nofldrxq; ++iter, ++q) 665 666 /* One for errors, one for firmware events */ 667 #define T4_EXTRA_INTR 2 668 669 static inline uint32_t 670 t4_read_reg(struct adapter *sc, uint32_t reg) 671 { 672 673 return bus_space_read_4(sc->bt, sc->bh, reg); 674 } 675 676 static inline void 677 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 678 { 679 680 bus_space_write_4(sc->bt, sc->bh, reg, val); 681 } 682 683 static inline uint64_t 684 t4_read_reg64(struct adapter *sc, uint32_t reg) 685 { 686 687 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 688 } 689 690 static inline void 691 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 692 { 693 694 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 695 } 696 697 static inline void 698 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 699 { 700 701 *val = pci_read_config(sc->dev, reg, 1); 702 } 703 704 static inline void 705 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 706 { 707 708 pci_write_config(sc->dev, reg, val, 1); 709 } 710 711 static inline void 712 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 713 { 714 715 *val = pci_read_config(sc->dev, reg, 2); 716 } 717 718 static inline void 719 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 720 { 721 722 pci_write_config(sc->dev, reg, val, 2); 723 } 724 725 static inline void 726 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 727 { 728 729 *val = pci_read_config(sc->dev, reg, 4); 730 } 731 732 static inline void 733 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 734 { 735 736 pci_write_config(sc->dev, reg, val, 4); 737 } 738 739 static inline struct port_info * 740 adap2pinfo(struct adapter *sc, int idx) 741 { 742 743 return (sc->port[idx]); 744 } 745 746 static inline void 747 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 748 { 749 750 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 751 } 752 753 static inline bool 754 is_10G_port(const struct port_info *pi) 755 { 756 757 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 758 } 759 760 static inline int 761 tx_resume_threshold(struct sge_eq *eq) 762 { 763 764 return (eq->qsize / 4); 765 } 766 767 /* t4_main.c */ 768 void t4_tx_task(void *, int); 769 void t4_tx_callout(void *); 770 int t4_os_find_pci_capability(struct adapter *, int); 771 int t4_os_pci_save_state(struct adapter *); 772 int t4_os_pci_restore_state(struct adapter *); 773 void t4_os_portmod_changed(const struct adapter *, int); 774 void t4_os_link_changed(struct adapter *, int, int); 775 void t4_iterate(void (*)(struct adapter *, void *), void *); 776 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 777 int t4_register_an_handler(struct adapter *, an_handler_t); 778 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 779 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 780 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 781 void end_synchronized_op(struct adapter *, int); 782 783 /* t4_sge.c */ 784 void t4_sge_modload(void); 785 void t4_init_sge_cpl_handlers(struct adapter *); 786 void t4_tweak_chip_settings(struct adapter *); 787 int t4_read_chip_settings(struct adapter *); 788 int t4_create_dma_tag(struct adapter *); 789 int t4_destroy_dma_tag(struct adapter *); 790 int t4_setup_adapter_queues(struct adapter *); 791 int t4_teardown_adapter_queues(struct adapter *); 792 int t4_setup_port_queues(struct port_info *); 793 int t4_teardown_port_queues(struct port_info *); 794 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 795 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 796 void t4_intr_all(void *); 797 void t4_intr(void *); 798 void t4_intr_err(void *); 799 void t4_intr_evt(void *); 800 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 801 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 802 void t4_update_fl_bufsize(struct ifnet *); 803 int can_resume_tx(struct sge_eq *); 804 805 static inline struct wrqe * 806 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 807 { 808 int len = offsetof(struct wrqe, wr) + wr_len; 809 struct wrqe *wr; 810 811 wr = malloc(len, M_CXGBE, M_NOWAIT); 812 if (__predict_false(wr == NULL)) 813 return (NULL); 814 wr->wr_len = wr_len; 815 wr->wrq = wrq; 816 return (wr); 817 } 818 819 static inline void * 820 wrtod(struct wrqe *wr) 821 { 822 return (&wr->wr[0]); 823 } 824 825 static inline void 826 free_wrqe(struct wrqe *wr) 827 { 828 free(wr, M_CXGBE); 829 } 830 831 static inline void 832 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 833 { 834 struct sge_wrq *wrq = wr->wrq; 835 836 TXQ_LOCK(wrq); 837 t4_wrq_tx_locked(sc, wrq, wr); 838 TXQ_UNLOCK(wrq); 839 } 840 841 #endif 842