1 /************************************************************************** 2 3 Copyright (c) 2007-2008, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/pciio.h> 39 #include <sys/conf.h> 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/bus_dma.h> 43 #include <sys/ktr.h> 44 #include <sys/rman.h> 45 #include <sys/ioccom.h> 46 #include <sys/mbuf.h> 47 #include <sys/linker.h> 48 #include <sys/firmware.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/smp.h> 52 #include <sys/sysctl.h> 53 #include <sys/syslog.h> 54 #include <sys/queue.h> 55 #include <sys/taskqueue.h> 56 #include <sys/proc.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 #include <net/if_vlan_var.h> 66 67 #include <netinet/in_systm.h> 68 #include <netinet/in.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pci_private.h> 78 79 #ifdef CONFIG_DEFINED 80 #include <cxgb_include.h> 81 #else 82 #include <dev/cxgb/cxgb_include.h> 83 #endif 84 85 #ifdef PRIV_SUPPORTED 86 #include <sys/priv.h> 87 #endif 88 89 #ifdef IFNET_MULTIQUEUE 90 #include <machine/intr_machdep.h> 91 #endif 92 93 static int cxgb_setup_msix(adapter_t *, int); 94 static void cxgb_teardown_msix(adapter_t *); 95 static void cxgb_init(void *); 96 static void cxgb_init_locked(struct port_info *); 97 static void cxgb_stop_locked(struct port_info *); 98 static void cxgb_set_rxmode(struct port_info *); 99 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 100 static int cxgb_media_change(struct ifnet *); 101 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 102 static int setup_sge_qsets(adapter_t *); 103 static void cxgb_async_intr(void *); 104 static void cxgb_ext_intr_handler(void *, int); 105 static void cxgb_tick_handler(void *, int); 106 static void cxgb_down_locked(struct adapter *sc); 107 static void cxgb_tick(void *); 108 static void setup_rss(adapter_t *sc); 109 110 /* Attachment glue for the PCI controller end of the device. Each port of 111 * the device is attached separately, as defined later. 112 */ 113 static int cxgb_controller_probe(device_t); 114 static int cxgb_controller_attach(device_t); 115 static int cxgb_controller_detach(device_t); 116 static void cxgb_free(struct adapter *); 117 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 118 unsigned int end); 119 static void cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf); 120 static int cxgb_get_regs_len(void); 121 static int offload_open(struct port_info *pi); 122 static void touch_bars(device_t dev); 123 static int offload_close(struct t3cdev *tdev); 124 static void cxgb_link_start(struct port_info *p); 125 126 static device_method_t cxgb_controller_methods[] = { 127 DEVMETHOD(device_probe, cxgb_controller_probe), 128 DEVMETHOD(device_attach, cxgb_controller_attach), 129 DEVMETHOD(device_detach, cxgb_controller_detach), 130 131 /* bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 134 135 { 0, 0 } 136 }; 137 138 static driver_t cxgb_controller_driver = { 139 "cxgbc", 140 cxgb_controller_methods, 141 sizeof(struct adapter) 142 }; 143 144 static devclass_t cxgb_controller_devclass; 145 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 146 147 /* 148 * Attachment glue for the ports. Attachment is done directly to the 149 * controller device. 150 */ 151 static int cxgb_port_probe(device_t); 152 static int cxgb_port_attach(device_t); 153 static int cxgb_port_detach(device_t); 154 155 static device_method_t cxgb_port_methods[] = { 156 DEVMETHOD(device_probe, cxgb_port_probe), 157 DEVMETHOD(device_attach, cxgb_port_attach), 158 DEVMETHOD(device_detach, cxgb_port_detach), 159 { 0, 0 } 160 }; 161 162 static driver_t cxgb_port_driver = { 163 "cxgb", 164 cxgb_port_methods, 165 0 166 }; 167 168 static d_ioctl_t cxgb_extension_ioctl; 169 static d_open_t cxgb_extension_open; 170 static d_close_t cxgb_extension_close; 171 172 static struct cdevsw cxgb_cdevsw = { 173 .d_version = D_VERSION, 174 .d_flags = 0, 175 .d_open = cxgb_extension_open, 176 .d_close = cxgb_extension_close, 177 .d_ioctl = cxgb_extension_ioctl, 178 .d_name = "cxgb", 179 }; 180 181 static devclass_t cxgb_port_devclass; 182 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 183 184 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 185 186 /* 187 * The driver uses the best interrupt scheme available on a platform in the 188 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 189 * of these schemes the driver may consider as follows: 190 * 191 * msi = 2: choose from among all three options 192 * msi = 1 : only consider MSI and pin interrupts 193 * msi = 0: force pin interrupts 194 */ 195 static int msi_allowed = 2; 196 197 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 198 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 199 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 200 "MSI-X, MSI, INTx selector"); 201 202 /* 203 * The driver enables offload as a default. 204 * To disable it, use ofld_disable = 1. 205 */ 206 static int ofld_disable = 0; 207 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 208 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 209 "disable ULP offload"); 210 211 /* 212 * The driver uses an auto-queue algorithm by default. 213 * To disable it and force a single queue-set per port, use singleq = 1. 214 */ 215 static int singleq = 0; 216 TUNABLE_INT("hw.cxgb.singleq", &singleq); 217 SYSCTL_UINT(_hw_cxgb, OID_AUTO, singleq, CTLFLAG_RDTUN, &singleq, 0, 218 "use a single queue-set per port"); 219 220 221 /* 222 * The driver uses an auto-queue algorithm by default. 223 * To disable it and force a single queue-set per port, use singleq = 1. 224 */ 225 static int force_fw_update = 0; 226 TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 227 SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 228 "update firmware even if up to date"); 229 230 int cxgb_use_16k_clusters = 0; 231 TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 232 SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 233 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 234 235 enum { 236 MAX_TXQ_ENTRIES = 16384, 237 MAX_CTRL_TXQ_ENTRIES = 1024, 238 MAX_RSPQ_ENTRIES = 16384, 239 MAX_RX_BUFFERS = 16384, 240 MAX_RX_JUMBO_BUFFERS = 16384, 241 MIN_TXQ_ENTRIES = 4, 242 MIN_CTRL_TXQ_ENTRIES = 4, 243 MIN_RSPQ_ENTRIES = 32, 244 MIN_FL_ENTRIES = 32, 245 MIN_FL_JUMBO_ENTRIES = 32 246 }; 247 248 struct filter_info { 249 u32 sip; 250 u32 sip_mask; 251 u32 dip; 252 u16 sport; 253 u16 dport; 254 u32 vlan:12; 255 u32 vlan_prio:3; 256 u32 mac_hit:1; 257 u32 mac_idx:4; 258 u32 mac_vld:1; 259 u32 pkt_type:2; 260 u32 report_filter_id:1; 261 u32 pass:1; 262 u32 rss:1; 263 u32 qset:3; 264 u32 locked:1; 265 u32 valid:1; 266 }; 267 268 enum { FILTER_NO_VLAN_PRI = 7 }; 269 270 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 271 272 /* Table for probing the cards. The desc field isn't actually used */ 273 struct cxgb_ident { 274 uint16_t vendor; 275 uint16_t device; 276 int index; 277 char *desc; 278 } cxgb_identifiers[] = { 279 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 280 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 281 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 285 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 286 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 287 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 288 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 289 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 290 {0, 0, 0, NULL} 291 }; 292 293 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 294 295 296 void 297 cxgb_log_tcb(struct adapter *sc, unsigned int tid) 298 { 299 char buf[TCB_SIZE]; 300 uint64_t *tcb = (uint64_t *)buf; 301 int i, error; 302 struct mc7 *mem = &sc->cm; 303 304 error = t3_mc7_bd_read(mem, tid*TCB_SIZE/8, TCB_SIZE/8, tcb); 305 if (error) 306 printf("cxgb_tcb_log failed\n"); 307 308 CTR1(KTR_CXGB, "TCB tid=%u", tid); 309 for (i = 0; i < TCB_SIZE / 32; i++) { 310 CTR5(KTR_CXGB, "%1d: %08x %08x %08x %08x", 311 i, (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 312 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 313 tcb += 2; 314 CTR4(KTR_CXGB, " %08x %08x %08x %08x", 315 (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 316 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 317 tcb += 2; 318 } 319 } 320 321 static __inline char 322 t3rev2char(struct adapter *adapter) 323 { 324 char rev = 'z'; 325 326 switch(adapter->params.rev) { 327 case T3_REV_A: 328 rev = 'a'; 329 break; 330 case T3_REV_B: 331 case T3_REV_B2: 332 rev = 'b'; 333 break; 334 case T3_REV_C: 335 rev = 'c'; 336 break; 337 } 338 return rev; 339 } 340 341 static struct cxgb_ident * 342 cxgb_get_ident(device_t dev) 343 { 344 struct cxgb_ident *id; 345 346 for (id = cxgb_identifiers; id->desc != NULL; id++) { 347 if ((id->vendor == pci_get_vendor(dev)) && 348 (id->device == pci_get_device(dev))) { 349 return (id); 350 } 351 } 352 return (NULL); 353 } 354 355 static const struct adapter_info * 356 cxgb_get_adapter_info(device_t dev) 357 { 358 struct cxgb_ident *id; 359 const struct adapter_info *ai; 360 361 id = cxgb_get_ident(dev); 362 if (id == NULL) 363 return (NULL); 364 365 ai = t3_get_adapter_info(id->index); 366 367 return (ai); 368 } 369 370 static int 371 cxgb_controller_probe(device_t dev) 372 { 373 const struct adapter_info *ai; 374 char *ports, buf[80]; 375 int nports; 376 377 ai = cxgb_get_adapter_info(dev); 378 if (ai == NULL) 379 return (ENXIO); 380 381 nports = ai->nports0 + ai->nports1; 382 if (nports == 1) 383 ports = "port"; 384 else 385 ports = "ports"; 386 387 snprintf(buf, sizeof(buf), "%s RNIC, %d %s", ai->desc, nports, ports); 388 device_set_desc_copy(dev, buf); 389 return (BUS_PROBE_DEFAULT); 390 } 391 392 #define FW_FNAME "cxgb_t3fw" 393 #define TPEEPROM_NAME "t3b_tp_eeprom" 394 #define TPSRAM_NAME "t3b_protocol_sram" 395 396 static int 397 upgrade_fw(adapter_t *sc) 398 { 399 #ifdef FIRMWARE_LATEST 400 const struct firmware *fw; 401 #else 402 struct firmware *fw; 403 #endif 404 int status; 405 406 if ((fw = firmware_get(FW_FNAME)) == NULL) { 407 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 408 return (ENOENT); 409 } else 410 device_printf(sc->dev, "updating firmware on card\n"); 411 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 412 413 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 414 415 firmware_put(fw, FIRMWARE_UNLOAD); 416 417 return (status); 418 } 419 420 static int 421 cxgb_controller_attach(device_t dev) 422 { 423 device_t child; 424 const struct adapter_info *ai; 425 struct adapter *sc; 426 int i, error = 0; 427 uint32_t vers; 428 int port_qsets = 1; 429 #ifdef MSI_SUPPORTED 430 int msi_needed, reg; 431 #endif 432 int must_load = 0; 433 sc = device_get_softc(dev); 434 sc->dev = dev; 435 sc->msi_count = 0; 436 ai = cxgb_get_adapter_info(dev); 437 438 /* 439 * XXX not really related but a recent addition 440 */ 441 #ifdef MSI_SUPPORTED 442 /* find the PCIe link width and set max read request to 4KB*/ 443 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 444 uint16_t lnk, pectl; 445 lnk = pci_read_config(dev, reg + 0x12, 2); 446 sc->link_width = (lnk >> 4) & 0x3f; 447 448 pectl = pci_read_config(dev, reg + 0x8, 2); 449 pectl = (pectl & ~0x7000) | (5 << 12); 450 pci_write_config(dev, reg + 0x8, pectl, 2); 451 } 452 453 if (sc->link_width != 0 && sc->link_width <= 4 && 454 (ai->nports0 + ai->nports1) <= 2) { 455 device_printf(sc->dev, 456 "PCIe x%d Link, expect reduced performance\n", 457 sc->link_width); 458 } 459 #endif 460 touch_bars(dev); 461 pci_enable_busmaster(dev); 462 /* 463 * Allocate the registers and make them available to the driver. 464 * The registers that we care about for NIC mode are in BAR 0 465 */ 466 sc->regs_rid = PCIR_BAR(0); 467 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 468 &sc->regs_rid, RF_ACTIVE)) == NULL) { 469 device_printf(dev, "Cannot allocate BAR region 0\n"); 470 return (ENXIO); 471 } 472 sc->udbs_rid = PCIR_BAR(2); 473 if ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 474 &sc->udbs_rid, RF_ACTIVE)) == NULL) { 475 device_printf(dev, "Cannot allocate BAR region 1\n"); 476 error = ENXIO; 477 goto out; 478 } 479 480 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 481 device_get_unit(dev)); 482 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 483 484 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 485 device_get_unit(dev)); 486 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 487 device_get_unit(dev)); 488 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 489 device_get_unit(dev)); 490 491 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 492 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 493 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 494 495 sc->bt = rman_get_bustag(sc->regs_res); 496 sc->bh = rman_get_bushandle(sc->regs_res); 497 sc->mmio_len = rman_get_size(sc->regs_res); 498 499 if (t3_prep_adapter(sc, ai, 1) < 0) { 500 printf("prep adapter failed\n"); 501 error = ENODEV; 502 goto out; 503 } 504 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 505 * enough messages for the queue sets. If that fails, try falling 506 * back to MSI. If that fails, then try falling back to the legacy 507 * interrupt pin model. 508 */ 509 #ifdef MSI_SUPPORTED 510 511 sc->msix_regs_rid = 0x20; 512 if ((msi_allowed >= 2) && 513 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 514 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 515 516 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 517 518 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 519 (sc->msi_count != msi_needed)) { 520 device_printf(dev, "msix allocation failed - msi_count = %d" 521 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 522 msi_needed, error); 523 sc->msi_count = 0; 524 pci_release_msi(dev); 525 bus_release_resource(dev, SYS_RES_MEMORY, 526 sc->msix_regs_rid, sc->msix_regs_res); 527 sc->msix_regs_res = NULL; 528 } else { 529 sc->flags |= USING_MSIX; 530 sc->cxgb_intr = t3_intr_msix; 531 } 532 } 533 534 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 535 sc->msi_count = 1; 536 if (pci_alloc_msi(dev, &sc->msi_count)) { 537 device_printf(dev, "alloc msi failed - will try INTx\n"); 538 sc->msi_count = 0; 539 pci_release_msi(dev); 540 } else { 541 sc->flags |= USING_MSI; 542 sc->irq_rid = 1; 543 sc->cxgb_intr = t3_intr_msi; 544 } 545 } 546 #endif 547 if (sc->msi_count == 0) { 548 device_printf(dev, "using line interrupts\n"); 549 sc->irq_rid = 0; 550 sc->cxgb_intr = t3b_intr; 551 } 552 553 if ((sc->flags & USING_MSIX) && !singleq) 554 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 555 556 /* Create a private taskqueue thread for handling driver events */ 557 #ifdef TASKQUEUE_CURRENT 558 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 559 taskqueue_thread_enqueue, &sc->tq); 560 #else 561 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 562 taskqueue_thread_enqueue, &sc->tq); 563 #endif 564 if (sc->tq == NULL) { 565 device_printf(dev, "failed to allocate controller task queue\n"); 566 goto out; 567 } 568 569 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 570 device_get_nameunit(dev)); 571 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 572 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 573 574 575 /* Create a periodic callout for checking adapter status */ 576 callout_init(&sc->cxgb_tick_ch, TRUE); 577 578 if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) { 579 /* 580 * Warn user that a firmware update will be attempted in init. 581 */ 582 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 583 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 584 sc->flags &= ~FW_UPTODATE; 585 } else { 586 sc->flags |= FW_UPTODATE; 587 } 588 589 if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) { 590 /* 591 * Warn user that a firmware update will be attempted in init. 592 */ 593 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 594 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 595 sc->flags &= ~TPS_UPTODATE; 596 } else { 597 sc->flags |= TPS_UPTODATE; 598 } 599 600 /* 601 * Create a child device for each MAC. The ethernet attachment 602 * will be done in these children. 603 */ 604 for (i = 0; i < (sc)->params.nports; i++) { 605 struct port_info *pi; 606 607 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 608 device_printf(dev, "failed to add child port\n"); 609 error = EINVAL; 610 goto out; 611 } 612 pi = &sc->port[i]; 613 pi->adapter = sc; 614 pi->nqsets = port_qsets; 615 pi->first_qset = i*port_qsets; 616 pi->port_id = i; 617 pi->tx_chan = i >= ai->nports0; 618 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 619 sc->rxpkt_map[pi->txpkt_intf] = i; 620 sc->port[i].tx_chan = i >= ai->nports0; 621 sc->portdev[i] = child; 622 device_set_softc(child, pi); 623 } 624 if ((error = bus_generic_attach(dev)) != 0) 625 goto out; 626 627 /* 628 * XXX need to poll for link status 629 */ 630 sc->params.stats_update_period = 1; 631 632 /* initialize sge private state */ 633 t3_sge_init_adapter(sc); 634 635 t3_led_ready(sc); 636 637 cxgb_offload_init(); 638 if (is_offload(sc)) { 639 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 640 cxgb_adapter_ofld(sc); 641 } 642 error = t3_get_fw_version(sc, &vers); 643 if (error) 644 goto out; 645 646 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 647 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 648 G_FW_VERSION_MICRO(vers)); 649 650 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 651 callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); 652 t3_add_attach_sysctls(sc); 653 out: 654 if (error) 655 cxgb_free(sc); 656 657 return (error); 658 } 659 660 static int 661 cxgb_controller_detach(device_t dev) 662 { 663 struct adapter *sc; 664 665 sc = device_get_softc(dev); 666 667 cxgb_free(sc); 668 669 return (0); 670 } 671 672 static void 673 cxgb_free(struct adapter *sc) 674 { 675 int i; 676 677 ADAPTER_LOCK(sc); 678 sc->flags |= CXGB_SHUTDOWN; 679 ADAPTER_UNLOCK(sc); 680 cxgb_pcpu_shutdown_threads(sc); 681 ADAPTER_LOCK(sc); 682 683 /* 684 * drops the lock 685 */ 686 cxgb_down_locked(sc); 687 688 #ifdef MSI_SUPPORTED 689 if (sc->flags & (USING_MSI | USING_MSIX)) { 690 device_printf(sc->dev, "releasing msi message(s)\n"); 691 pci_release_msi(sc->dev); 692 } else { 693 device_printf(sc->dev, "no msi message to release\n"); 694 } 695 #endif 696 if (sc->msix_regs_res != NULL) { 697 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 698 sc->msix_regs_res); 699 } 700 701 t3_sge_deinit_sw(sc); 702 /* 703 * Wait for last callout 704 */ 705 706 DELAY(hz*100); 707 708 for (i = 0; i < (sc)->params.nports; ++i) { 709 if (sc->portdev[i] != NULL) 710 device_delete_child(sc->dev, sc->portdev[i]); 711 } 712 713 bus_generic_detach(sc->dev); 714 if (sc->tq != NULL) { 715 taskqueue_free(sc->tq); 716 sc->tq = NULL; 717 } 718 719 if (is_offload(sc)) { 720 cxgb_adapter_unofld(sc); 721 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 722 offload_close(&sc->tdev); 723 else 724 printf("cxgb_free: DEVMAP_BIT not set\n"); 725 } else 726 printf("not offloading set\n"); 727 #ifdef notyet 728 if (sc->flags & CXGB_OFLD_INIT) 729 cxgb_offload_deactivate(sc); 730 #endif 731 free(sc->filters, M_DEVBUF); 732 t3_sge_free(sc); 733 734 cxgb_offload_exit(); 735 736 if (sc->udbs_res != NULL) 737 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 738 sc->udbs_res); 739 740 if (sc->regs_res != NULL) 741 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 742 sc->regs_res); 743 744 MTX_DESTROY(&sc->mdio_lock); 745 MTX_DESTROY(&sc->sge.reg_lock); 746 MTX_DESTROY(&sc->elmer_lock); 747 ADAPTER_LOCK_DEINIT(sc); 748 } 749 750 /** 751 * setup_sge_qsets - configure SGE Tx/Rx/response queues 752 * @sc: the controller softc 753 * 754 * Determines how many sets of SGE queues to use and initializes them. 755 * We support multiple queue sets per port if we have MSI-X, otherwise 756 * just one queue set per port. 757 */ 758 static int 759 setup_sge_qsets(adapter_t *sc) 760 { 761 int i, j, err, irq_idx = 0, qset_idx = 0; 762 u_int ntxq = SGE_TXQ_PER_SET; 763 764 if ((err = t3_sge_alloc(sc)) != 0) { 765 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 766 return (err); 767 } 768 769 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 770 irq_idx = -1; 771 772 for (i = 0; i < (sc)->params.nports; i++) { 773 struct port_info *pi = &sc->port[i]; 774 775 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 776 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 777 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 778 &sc->params.sge.qset[qset_idx], ntxq, pi); 779 if (err) { 780 t3_free_sge_resources(sc); 781 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 782 err); 783 return (err); 784 } 785 } 786 } 787 788 return (0); 789 } 790 791 static void 792 cxgb_teardown_msix(adapter_t *sc) 793 { 794 int i, nqsets; 795 796 for (nqsets = i = 0; i < (sc)->params.nports; i++) 797 nqsets += sc->port[i].nqsets; 798 799 for (i = 0; i < nqsets; i++) { 800 if (sc->msix_intr_tag[i] != NULL) { 801 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 802 sc->msix_intr_tag[i]); 803 sc->msix_intr_tag[i] = NULL; 804 } 805 if (sc->msix_irq_res[i] != NULL) { 806 bus_release_resource(sc->dev, SYS_RES_IRQ, 807 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 808 sc->msix_irq_res[i] = NULL; 809 } 810 } 811 } 812 813 static int 814 cxgb_setup_msix(adapter_t *sc, int msix_count) 815 { 816 int i, j, k, nqsets, rid; 817 818 /* The first message indicates link changes and error conditions */ 819 sc->irq_rid = 1; 820 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 821 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 822 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 823 return (EINVAL); 824 } 825 826 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 827 #ifdef INTR_FILTERS 828 NULL, 829 #endif 830 cxgb_async_intr, sc, &sc->intr_tag)) { 831 device_printf(sc->dev, "Cannot set up interrupt\n"); 832 return (EINVAL); 833 } 834 for (i = k = 0; i < (sc)->params.nports; i++) { 835 nqsets = sc->port[i].nqsets; 836 for (j = 0; j < nqsets; j++, k++) { 837 struct sge_qset *qs = &sc->sge.qs[k]; 838 839 rid = k + 2; 840 if (cxgb_debug) 841 printf("rid=%d ", rid); 842 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 843 sc->dev, SYS_RES_IRQ, &rid, 844 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 845 device_printf(sc->dev, "Cannot allocate " 846 "interrupt for message %d\n", rid); 847 return (EINVAL); 848 } 849 sc->msix_irq_rid[k] = rid; 850 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 851 INTR_MPSAFE|INTR_TYPE_NET, 852 #ifdef INTR_FILTERS 853 NULL, 854 #endif 855 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 856 device_printf(sc->dev, "Cannot set up " 857 "interrupt for message %d\n", rid); 858 return (EINVAL); 859 } 860 #ifdef IFNET_MULTIQUEUE 861 if (singleq == 0) { 862 int vector = rman_get_start(sc->msix_irq_res[k]); 863 if (bootverbose) 864 device_printf(sc->dev, "binding vector=%d to cpu=%d\n", vector, k % mp_ncpus); 865 intr_bind(vector, k % mp_ncpus); 866 } 867 #endif 868 } 869 } 870 871 return (0); 872 } 873 874 static int 875 cxgb_port_probe(device_t dev) 876 { 877 struct port_info *p; 878 char buf[80]; 879 const char *desc; 880 881 p = device_get_softc(dev); 882 desc = p->phy.desc; 883 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 884 device_set_desc_copy(dev, buf); 885 return (0); 886 } 887 888 889 static int 890 cxgb_makedev(struct port_info *pi) 891 { 892 893 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 894 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 895 896 if (pi->port_cdev == NULL) 897 return (ENOMEM); 898 899 pi->port_cdev->si_drv1 = (void *)pi; 900 901 return (0); 902 } 903 904 905 #ifdef TSO_SUPPORTED 906 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU) 907 /* Don't enable TSO6 yet */ 908 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU) 909 #else 910 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 911 /* Don't enable TSO6 yet */ 912 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 913 #define IFCAP_TSO4 0x0 914 #define IFCAP_TSO6 0x0 915 #define CSUM_TSO 0x0 916 #endif 917 918 919 static int 920 cxgb_port_attach(device_t dev) 921 { 922 struct port_info *p; 923 struct ifnet *ifp; 924 int err, media_flags; 925 struct adapter *sc; 926 927 928 p = device_get_softc(dev); 929 sc = p->adapter; 930 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 931 device_get_unit(device_get_parent(dev)), p->port_id); 932 PORT_LOCK_INIT(p, p->lockbuf); 933 934 /* Allocate an ifnet object and set it up */ 935 ifp = p->ifp = if_alloc(IFT_ETHER); 936 if (ifp == NULL) { 937 device_printf(dev, "Cannot allocate ifnet\n"); 938 return (ENOMEM); 939 } 940 941 /* 942 * Note that there is currently no watchdog timer. 943 */ 944 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 945 ifp->if_init = cxgb_init; 946 ifp->if_softc = p; 947 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 948 ifp->if_ioctl = cxgb_ioctl; 949 ifp->if_start = cxgb_start; 950 951 #if 0 952 #ifdef IFNET_MULTIQUEUE 953 ifp->if_flags |= IFF_MULTIQ; 954 ifp->if_mq_start = cxgb_pcpu_start; 955 #endif 956 #endif 957 ifp->if_timer = 0; /* Disable ifnet watchdog */ 958 ifp->if_watchdog = NULL; 959 960 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 961 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 962 IFQ_SET_READY(&ifp->if_snd); 963 964 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 965 ifp->if_capabilities |= CXGB_CAP; 966 ifp->if_capenable |= CXGB_CAP_ENABLE; 967 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 968 /* 969 * disable TSO on 4-port - it isn't supported by the firmware yet 970 */ 971 if (p->adapter->params.nports > 2) { 972 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 973 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 974 ifp->if_hwassist &= ~CSUM_TSO; 975 } 976 977 ether_ifattach(ifp, p->hw_addr); 978 /* 979 * Only default to jumbo frames on 10GigE 980 */ 981 if (p->adapter->params.nports <= 2) 982 ifp->if_mtu = ETHERMTU_JUMBO; 983 if ((err = cxgb_makedev(p)) != 0) { 984 printf("makedev failed %d\n", err); 985 return (err); 986 } 987 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 988 cxgb_media_status); 989 990 if (!strcmp(p->phy.desc, "10GBASE-CX4")) { 991 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 992 } else if (!strcmp(p->phy.desc, "10GBASE-SR")) { 993 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 994 } else if (!strcmp(p->phy.desc, "10GBASE-R")) { 995 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 996 } else if (!strcmp(p->phy.desc, "10/100/1000BASE-T")) { 997 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 998 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 999 0, NULL); 1000 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 1001 0, NULL); 1002 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1003 0, NULL); 1004 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1005 0, NULL); 1006 media_flags = 0; 1007 } else { 1008 printf("unsupported media type %s\n", p->phy.desc); 1009 return (ENXIO); 1010 } 1011 if (media_flags) { 1012 ifmedia_add(&p->media, media_flags, 0, NULL); 1013 ifmedia_set(&p->media, media_flags); 1014 } else { 1015 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1016 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1017 } 1018 1019 1020 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id); 1021 #ifdef TASKQUEUE_CURRENT 1022 /* Create a port for handling TX without starvation */ 1023 p->tq = taskqueue_create(p->taskqbuf, M_NOWAIT, 1024 taskqueue_thread_enqueue, &p->tq); 1025 #else 1026 /* Create a port for handling TX without starvation */ 1027 p->tq = taskqueue_create_fast(p->taskqbuf, M_NOWAIT, 1028 taskqueue_thread_enqueue, &p->tq); 1029 #endif 1030 /* Get the latest mac address, User can use a LAA */ 1031 bcopy(IF_LLADDR(p->ifp), p->hw_addr, ETHER_ADDR_LEN); 1032 t3_sge_init_port(p); 1033 #if defined(LINK_ATTACH) 1034 cxgb_link_start(p); 1035 t3_link_changed(sc, p->port_id); 1036 #endif 1037 return (0); 1038 } 1039 1040 static int 1041 cxgb_port_detach(device_t dev) 1042 { 1043 struct port_info *p; 1044 1045 p = device_get_softc(dev); 1046 1047 PORT_LOCK(p); 1048 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1049 cxgb_stop_locked(p); 1050 PORT_UNLOCK(p); 1051 1052 if (p->tq != NULL) { 1053 taskqueue_drain(p->tq, &p->start_task); 1054 taskqueue_free(p->tq); 1055 p->tq = NULL; 1056 } 1057 1058 ether_ifdetach(p->ifp); 1059 printf("waiting for callout to stop ..."); 1060 DELAY(1000000); 1061 printf("done\n"); 1062 /* 1063 * the lock may be acquired in ifdetach 1064 */ 1065 PORT_LOCK_DEINIT(p); 1066 if_free(p->ifp); 1067 1068 if (p->port_cdev != NULL) 1069 destroy_dev(p->port_cdev); 1070 1071 return (0); 1072 } 1073 1074 void 1075 t3_fatal_err(struct adapter *sc) 1076 { 1077 u_int fw_status[4]; 1078 1079 if (sc->flags & FULL_INIT_DONE) { 1080 t3_sge_stop(sc); 1081 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1082 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1083 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1084 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1085 t3_intr_disable(sc); 1086 } 1087 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1088 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1089 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1090 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1091 } 1092 1093 int 1094 t3_os_find_pci_capability(adapter_t *sc, int cap) 1095 { 1096 device_t dev; 1097 struct pci_devinfo *dinfo; 1098 pcicfgregs *cfg; 1099 uint32_t status; 1100 uint8_t ptr; 1101 1102 dev = sc->dev; 1103 dinfo = device_get_ivars(dev); 1104 cfg = &dinfo->cfg; 1105 1106 status = pci_read_config(dev, PCIR_STATUS, 2); 1107 if (!(status & PCIM_STATUS_CAPPRESENT)) 1108 return (0); 1109 1110 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1111 case 0: 1112 case 1: 1113 ptr = PCIR_CAP_PTR; 1114 break; 1115 case 2: 1116 ptr = PCIR_CAP_PTR_2; 1117 break; 1118 default: 1119 return (0); 1120 break; 1121 } 1122 ptr = pci_read_config(dev, ptr, 1); 1123 1124 while (ptr != 0) { 1125 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1126 return (ptr); 1127 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1128 } 1129 1130 return (0); 1131 } 1132 1133 int 1134 t3_os_pci_save_state(struct adapter *sc) 1135 { 1136 device_t dev; 1137 struct pci_devinfo *dinfo; 1138 1139 dev = sc->dev; 1140 dinfo = device_get_ivars(dev); 1141 1142 pci_cfg_save(dev, dinfo, 0); 1143 return (0); 1144 } 1145 1146 int 1147 t3_os_pci_restore_state(struct adapter *sc) 1148 { 1149 device_t dev; 1150 struct pci_devinfo *dinfo; 1151 1152 dev = sc->dev; 1153 dinfo = device_get_ivars(dev); 1154 1155 pci_cfg_restore(dev, dinfo); 1156 return (0); 1157 } 1158 1159 /** 1160 * t3_os_link_changed - handle link status changes 1161 * @adapter: the adapter associated with the link change 1162 * @port_id: the port index whose limk status has changed 1163 * @link_status: the new status of the link 1164 * @speed: the new speed setting 1165 * @duplex: the new duplex setting 1166 * @fc: the new flow-control setting 1167 * 1168 * This is the OS-dependent handler for link status changes. The OS 1169 * neutral handler takes care of most of the processing for these events, 1170 * then calls this handler for any OS-specific processing. 1171 */ 1172 void 1173 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1174 int duplex, int fc) 1175 { 1176 struct port_info *pi = &adapter->port[port_id]; 1177 struct cmac *mac = &adapter->port[port_id].mac; 1178 1179 if (link_status) { 1180 DELAY(10); 1181 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1182 /* Clear errors created by MAC enable */ 1183 t3_set_reg_field(adapter, 1184 A_XGM_STAT_CTRL + pi->mac.offset, 1185 F_CLRSTATS, 1); 1186 if_link_state_change(pi->ifp, LINK_STATE_UP); 1187 1188 } else { 1189 pi->phy.ops->power_down(&pi->phy, 1); 1190 t3_mac_disable(mac, MAC_DIRECTION_RX); 1191 t3_link_start(&pi->phy, mac, &pi->link_config); 1192 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1193 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1194 } 1195 } 1196 1197 /* 1198 * Interrupt-context handler for external (PHY) interrupts. 1199 */ 1200 void 1201 t3_os_ext_intr_handler(adapter_t *sc) 1202 { 1203 if (cxgb_debug) 1204 printf("t3_os_ext_intr_handler\n"); 1205 /* 1206 * Schedule a task to handle external interrupts as they may be slow 1207 * and we use a mutex to protect MDIO registers. We disable PHY 1208 * interrupts in the meantime and let the task reenable them when 1209 * it's done. 1210 */ 1211 ADAPTER_LOCK(sc); 1212 if (sc->slow_intr_mask) { 1213 sc->slow_intr_mask &= ~F_T3DBG; 1214 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1215 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1216 } 1217 ADAPTER_UNLOCK(sc); 1218 } 1219 1220 void 1221 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1222 { 1223 1224 /* 1225 * The ifnet might not be allocated before this gets called, 1226 * as this is called early on in attach by t3_prep_adapter 1227 * save the address off in the port structure 1228 */ 1229 if (cxgb_debug) 1230 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1231 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1232 } 1233 1234 /** 1235 * link_start - enable a port 1236 * @p: the port to enable 1237 * 1238 * Performs the MAC and PHY actions needed to enable a port. 1239 */ 1240 static void 1241 cxgb_link_start(struct port_info *p) 1242 { 1243 struct ifnet *ifp; 1244 struct t3_rx_mode rm; 1245 struct cmac *mac = &p->mac; 1246 int mtu, hwtagging; 1247 1248 ifp = p->ifp; 1249 1250 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1251 1252 mtu = ifp->if_mtu; 1253 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1254 mtu += ETHER_VLAN_ENCAP_LEN; 1255 1256 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1257 1258 t3_init_rx_mode(&rm, p); 1259 if (!mac->multiport) 1260 t3_mac_reset(mac); 1261 t3_mac_set_mtu(mac, mtu); 1262 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1263 t3_mac_set_address(mac, 0, p->hw_addr); 1264 t3_mac_set_rx_mode(mac, &rm); 1265 t3_link_start(&p->phy, mac, &p->link_config); 1266 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1267 } 1268 1269 1270 static int 1271 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1272 unsigned long n) 1273 { 1274 int attempts = 5; 1275 1276 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1277 if (!--attempts) 1278 return (ETIMEDOUT); 1279 t3_os_sleep(10); 1280 } 1281 return 0; 1282 } 1283 1284 static int 1285 init_tp_parity(struct adapter *adap) 1286 { 1287 int i; 1288 struct mbuf *m; 1289 struct cpl_set_tcb_field *greq; 1290 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1291 1292 t3_tp_set_offload_mode(adap, 1); 1293 1294 for (i = 0; i < 16; i++) { 1295 struct cpl_smt_write_req *req; 1296 1297 m = m_gethdr(M_WAITOK, MT_DATA); 1298 req = mtod(m, struct cpl_smt_write_req *); 1299 m->m_len = m->m_pkthdr.len = sizeof(*req); 1300 memset(req, 0, sizeof(*req)); 1301 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1302 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1303 req->iff = i; 1304 t3_mgmt_tx(adap, m); 1305 } 1306 1307 for (i = 0; i < 2048; i++) { 1308 struct cpl_l2t_write_req *req; 1309 1310 m = m_gethdr(M_WAITOK, MT_DATA); 1311 req = mtod(m, struct cpl_l2t_write_req *); 1312 m->m_len = m->m_pkthdr.len = sizeof(*req); 1313 memset(req, 0, sizeof(*req)); 1314 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1315 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1316 req->params = htonl(V_L2T_W_IDX(i)); 1317 t3_mgmt_tx(adap, m); 1318 } 1319 1320 for (i = 0; i < 2048; i++) { 1321 struct cpl_rte_write_req *req; 1322 1323 m = m_gethdr(M_WAITOK, MT_DATA); 1324 req = mtod(m, struct cpl_rte_write_req *); 1325 m->m_len = m->m_pkthdr.len = sizeof(*req); 1326 memset(req, 0, sizeof(*req)); 1327 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1328 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1329 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1330 t3_mgmt_tx(adap, m); 1331 } 1332 1333 m = m_gethdr(M_WAITOK, MT_DATA); 1334 greq = mtod(m, struct cpl_set_tcb_field *); 1335 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1336 memset(greq, 0, sizeof(*greq)); 1337 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1338 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1339 greq->mask = htobe64(1); 1340 t3_mgmt_tx(adap, m); 1341 1342 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1343 t3_tp_set_offload_mode(adap, 0); 1344 return (i); 1345 } 1346 1347 /** 1348 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1349 * @adap: the adapter 1350 * 1351 * Sets up RSS to distribute packets to multiple receive queues. We 1352 * configure the RSS CPU lookup table to distribute to the number of HW 1353 * receive queues, and the response queue lookup table to narrow that 1354 * down to the response queues actually configured for each port. 1355 * We always configure the RSS mapping for two ports since the mapping 1356 * table has plenty of entries. 1357 */ 1358 static void 1359 setup_rss(adapter_t *adap) 1360 { 1361 int i; 1362 u_int nq[2]; 1363 uint8_t cpus[SGE_QSETS + 1]; 1364 uint16_t rspq_map[RSS_TABLE_SIZE]; 1365 1366 for (i = 0; i < SGE_QSETS; ++i) 1367 cpus[i] = i; 1368 cpus[SGE_QSETS] = 0xff; 1369 1370 nq[0] = nq[1] = 0; 1371 for_each_port(adap, i) { 1372 const struct port_info *pi = adap2pinfo(adap, i); 1373 1374 nq[pi->tx_chan] += pi->nqsets; 1375 } 1376 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1377 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1378 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1379 } 1380 /* Calculate the reverse RSS map table */ 1381 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1382 if (adap->rrss_map[rspq_map[i]] == 0xff) 1383 adap->rrss_map[rspq_map[i]] = i; 1384 1385 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1386 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1387 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1388 cpus, rspq_map); 1389 1390 } 1391 1392 /* 1393 * Sends an mbuf to an offload queue driver 1394 * after dealing with any active network taps. 1395 */ 1396 static inline int 1397 offload_tx(struct t3cdev *tdev, struct mbuf *m) 1398 { 1399 int ret; 1400 1401 ret = t3_offload_tx(tdev, m); 1402 return (ret); 1403 } 1404 1405 static int 1406 write_smt_entry(struct adapter *adapter, int idx) 1407 { 1408 struct port_info *pi = &adapter->port[idx]; 1409 struct cpl_smt_write_req *req; 1410 struct mbuf *m; 1411 1412 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1413 return (ENOMEM); 1414 1415 req = mtod(m, struct cpl_smt_write_req *); 1416 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1417 1418 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1419 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1420 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1421 req->iff = idx; 1422 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1423 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1424 1425 m_set_priority(m, 1); 1426 1427 offload_tx(&adapter->tdev, m); 1428 1429 return (0); 1430 } 1431 1432 static int 1433 init_smt(struct adapter *adapter) 1434 { 1435 int i; 1436 1437 for_each_port(adapter, i) 1438 write_smt_entry(adapter, i); 1439 return 0; 1440 } 1441 1442 static void 1443 init_port_mtus(adapter_t *adapter) 1444 { 1445 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1446 1447 if (adapter->port[1].ifp) 1448 mtus |= adapter->port[1].ifp->if_mtu << 16; 1449 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1450 } 1451 1452 static void 1453 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1454 int hi, int port) 1455 { 1456 struct mbuf *m; 1457 struct mngt_pktsched_wr *req; 1458 1459 m = m_gethdr(M_DONTWAIT, MT_DATA); 1460 if (m) { 1461 req = mtod(m, struct mngt_pktsched_wr *); 1462 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1463 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1464 req->sched = sched; 1465 req->idx = qidx; 1466 req->min = lo; 1467 req->max = hi; 1468 req->binding = port; 1469 m->m_len = m->m_pkthdr.len = sizeof(*req); 1470 t3_mgmt_tx(adap, m); 1471 } 1472 } 1473 1474 static void 1475 bind_qsets(adapter_t *sc) 1476 { 1477 int i, j; 1478 1479 cxgb_pcpu_startup_threads(sc); 1480 for (i = 0; i < (sc)->params.nports; ++i) { 1481 const struct port_info *pi = adap2pinfo(sc, i); 1482 1483 for (j = 0; j < pi->nqsets; ++j) { 1484 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1485 -1, pi->tx_chan); 1486 1487 } 1488 } 1489 } 1490 1491 static void 1492 update_tpeeprom(struct adapter *adap) 1493 { 1494 #ifdef FIRMWARE_LATEST 1495 const struct firmware *tpeeprom; 1496 #else 1497 struct firmware *tpeeprom; 1498 #endif 1499 1500 uint32_t version; 1501 unsigned int major, minor; 1502 int ret, len; 1503 char rev; 1504 1505 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1506 1507 major = G_TP_VERSION_MAJOR(version); 1508 minor = G_TP_VERSION_MINOR(version); 1509 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1510 return; 1511 1512 rev = t3rev2char(adap); 1513 1514 tpeeprom = firmware_get(TPEEPROM_NAME); 1515 if (tpeeprom == NULL) { 1516 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1517 TPEEPROM_NAME); 1518 return; 1519 } 1520 1521 len = tpeeprom->datasize - 4; 1522 1523 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1524 if (ret) 1525 goto release_tpeeprom; 1526 1527 if (len != TP_SRAM_LEN) { 1528 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", TPEEPROM_NAME, len, TP_SRAM_LEN); 1529 return; 1530 } 1531 1532 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1533 TP_SRAM_OFFSET); 1534 1535 if (!ret) { 1536 device_printf(adap->dev, 1537 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1538 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1539 } else 1540 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1541 1542 release_tpeeprom: 1543 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1544 1545 return; 1546 } 1547 1548 static int 1549 update_tpsram(struct adapter *adap) 1550 { 1551 #ifdef FIRMWARE_LATEST 1552 const struct firmware *tpsram; 1553 #else 1554 struct firmware *tpsram; 1555 #endif 1556 int ret; 1557 char rev; 1558 1559 rev = t3rev2char(adap); 1560 if (!rev) 1561 return 0; 1562 1563 update_tpeeprom(adap); 1564 1565 tpsram = firmware_get(TPSRAM_NAME); 1566 if (tpsram == NULL){ 1567 device_printf(adap->dev, "could not load TP SRAM\n"); 1568 return (EINVAL); 1569 } else 1570 device_printf(adap->dev, "updating TP SRAM\n"); 1571 1572 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1573 if (ret) 1574 goto release_tpsram; 1575 1576 ret = t3_set_proto_sram(adap, tpsram->data); 1577 if (ret) 1578 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1579 1580 release_tpsram: 1581 firmware_put(tpsram, FIRMWARE_UNLOAD); 1582 1583 return ret; 1584 } 1585 1586 /** 1587 * cxgb_up - enable the adapter 1588 * @adap: adapter being enabled 1589 * 1590 * Called when the first port is enabled, this function performs the 1591 * actions necessary to make an adapter operational, such as completing 1592 * the initialization of HW modules, and enabling interrupts. 1593 * 1594 */ 1595 static int 1596 cxgb_up(struct adapter *sc) 1597 { 1598 int err = 0; 1599 1600 if ((sc->flags & FULL_INIT_DONE) == 0) { 1601 1602 if ((sc->flags & FW_UPTODATE) == 0) 1603 if ((err = upgrade_fw(sc))) 1604 goto out; 1605 if ((sc->flags & TPS_UPTODATE) == 0) 1606 if ((err = update_tpsram(sc))) 1607 goto out; 1608 err = t3_init_hw(sc, 0); 1609 if (err) 1610 goto out; 1611 1612 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1613 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1614 1615 err = setup_sge_qsets(sc); 1616 if (err) 1617 goto out; 1618 1619 setup_rss(sc); 1620 t3_add_configured_sysctls(sc); 1621 sc->flags |= FULL_INIT_DONE; 1622 } 1623 1624 t3_intr_clear(sc); 1625 1626 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1627 if ((sc->flags & USING_MSIX) == 0) { 1628 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1629 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1630 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", 1631 sc->irq_rid); 1632 err = EINVAL; 1633 goto out; 1634 } 1635 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1636 1637 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1638 #ifdef INTR_FILTERS 1639 NULL, 1640 #endif 1641 sc->cxgb_intr, sc, &sc->intr_tag)) { 1642 device_printf(sc->dev, "Cannot set up interrupt\n"); 1643 err = EINVAL; 1644 goto irq_err; 1645 } 1646 } else { 1647 cxgb_setup_msix(sc, sc->msi_count); 1648 } 1649 1650 t3_sge_start(sc); 1651 t3_intr_enable(sc); 1652 1653 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1654 is_offload(sc) && init_tp_parity(sc) == 0) 1655 sc->flags |= TP_PARITY_INIT; 1656 1657 if (sc->flags & TP_PARITY_INIT) { 1658 t3_write_reg(sc, A_TP_INT_CAUSE, 1659 F_CMCACHEPERR | F_ARPLUTPERR); 1660 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1661 } 1662 1663 1664 if (!(sc->flags & QUEUES_BOUND)) { 1665 bind_qsets(sc); 1666 sc->flags |= QUEUES_BOUND; 1667 } 1668 out: 1669 return (err); 1670 irq_err: 1671 CH_ERR(sc, "request_irq failed, err %d\n", err); 1672 goto out; 1673 } 1674 1675 1676 /* 1677 * Release resources when all the ports and offloading have been stopped. 1678 */ 1679 static void 1680 cxgb_down_locked(struct adapter *sc) 1681 { 1682 1683 t3_sge_stop(sc); 1684 t3_intr_disable(sc); 1685 1686 if (sc->intr_tag != NULL) { 1687 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1688 sc->intr_tag = NULL; 1689 } 1690 if (sc->irq_res != NULL) { 1691 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1692 sc->irq_rid, sc->irq_res); 1693 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1694 sc->irq_res); 1695 sc->irq_res = NULL; 1696 } 1697 1698 if (sc->flags & USING_MSIX) 1699 cxgb_teardown_msix(sc); 1700 1701 callout_stop(&sc->cxgb_tick_ch); 1702 callout_stop(&sc->sge_timer_ch); 1703 callout_drain(&sc->cxgb_tick_ch); 1704 callout_drain(&sc->sge_timer_ch); 1705 1706 if (sc->tq != NULL) { 1707 printf("draining slow intr\n"); 1708 1709 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1710 printf("draining ext intr\n"); 1711 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1712 printf("draining tick task\n"); 1713 taskqueue_drain(sc->tq, &sc->tick_task); 1714 } 1715 ADAPTER_UNLOCK(sc); 1716 } 1717 1718 static int 1719 offload_open(struct port_info *pi) 1720 { 1721 struct adapter *adapter = pi->adapter; 1722 struct t3cdev *tdev = &adapter->tdev; 1723 #ifdef notyet 1724 T3CDEV(pi->ifp); 1725 #endif 1726 int adap_up = adapter->open_device_map & PORT_MASK; 1727 int err = 0; 1728 1729 CTR1(KTR_CXGB, "device_map=0x%x", adapter->open_device_map); 1730 if (atomic_cmpset_int(&adapter->open_device_map, 1731 (adapter->open_device_map & ~(1<<OFFLOAD_DEVMAP_BIT)), 1732 (adapter->open_device_map | (1<<OFFLOAD_DEVMAP_BIT))) == 0) 1733 return (0); 1734 1735 1736 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1737 printf("offload_open: DEVMAP_BIT did not get set 0x%x\n", adapter->open_device_map); 1738 ADAPTER_LOCK(pi->adapter); 1739 if (!adap_up) 1740 err = cxgb_up(adapter); 1741 ADAPTER_UNLOCK(pi->adapter); 1742 if (err) 1743 return (err); 1744 1745 t3_tp_set_offload_mode(adapter, 1); 1746 tdev->lldev = pi->ifp; 1747 1748 init_port_mtus(adapter); 1749 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1750 adapter->params.b_wnd, 1751 adapter->params.rev == 0 ? 1752 adapter->port[0].ifp->if_mtu : 0xffff); 1753 init_smt(adapter); 1754 1755 /* Call back all registered clients */ 1756 cxgb_add_clients(tdev); 1757 1758 1759 /* restore them in case the offload module has changed them */ 1760 if (err) { 1761 t3_tp_set_offload_mode(adapter, 0); 1762 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1763 cxgb_set_dummy_ops(tdev); 1764 } 1765 return (err); 1766 } 1767 1768 static int 1769 offload_close(struct t3cdev *tdev) 1770 { 1771 struct adapter *adapter = tdev2adap(tdev); 1772 1773 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1774 return (0); 1775 1776 /* Call back all registered clients */ 1777 cxgb_remove_clients(tdev); 1778 1779 tdev->lldev = NULL; 1780 cxgb_set_dummy_ops(tdev); 1781 t3_tp_set_offload_mode(adapter, 0); 1782 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1783 1784 ADAPTER_LOCK(adapter); 1785 if (!adapter->open_device_map) 1786 cxgb_down_locked(adapter); 1787 else 1788 ADAPTER_UNLOCK(adapter); 1789 return (0); 1790 } 1791 1792 1793 static void 1794 cxgb_init(void *arg) 1795 { 1796 struct port_info *p = arg; 1797 1798 PORT_LOCK(p); 1799 cxgb_init_locked(p); 1800 PORT_UNLOCK(p); 1801 } 1802 1803 static void 1804 cxgb_init_locked(struct port_info *p) 1805 { 1806 struct ifnet *ifp; 1807 adapter_t *sc = p->adapter; 1808 int err; 1809 1810 PORT_LOCK_ASSERT_OWNED(p); 1811 ifp = p->ifp; 1812 1813 ADAPTER_LOCK(p->adapter); 1814 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1815 ADAPTER_UNLOCK(p->adapter); 1816 cxgb_stop_locked(p); 1817 return; 1818 } 1819 if (p->adapter->open_device_map == 0) { 1820 t3_intr_clear(sc); 1821 } 1822 setbit(&p->adapter->open_device_map, p->port_id); 1823 ADAPTER_UNLOCK(p->adapter); 1824 1825 if (is_offload(sc) && !ofld_disable) { 1826 err = offload_open(p); 1827 if (err) 1828 log(LOG_WARNING, 1829 "Could not initialize offload capabilities\n"); 1830 } 1831 #if !defined(LINK_ATTACH) 1832 cxgb_link_start(p); 1833 t3_link_changed(sc, p->port_id); 1834 #endif 1835 ifp->if_baudrate = p->link_config.speed * 1000000; 1836 1837 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1838 t3_port_intr_enable(sc, p->port_id); 1839 1840 t3_sge_reset_adapter(sc); 1841 1842 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1843 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1844 } 1845 1846 static void 1847 cxgb_set_rxmode(struct port_info *p) 1848 { 1849 struct t3_rx_mode rm; 1850 struct cmac *mac = &p->mac; 1851 1852 t3_init_rx_mode(&rm, p); 1853 mtx_lock(&p->adapter->mdio_lock); 1854 t3_mac_set_rx_mode(mac, &rm); 1855 mtx_unlock(&p->adapter->mdio_lock); 1856 } 1857 1858 static void 1859 cxgb_stop_locked(struct port_info *pi) 1860 { 1861 struct ifnet *ifp; 1862 1863 PORT_LOCK_ASSERT_OWNED(pi); 1864 ADAPTER_LOCK_ASSERT_NOTOWNED(pi->adapter); 1865 1866 ifp = pi->ifp; 1867 t3_port_intr_disable(pi->adapter, pi->port_id); 1868 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1869 1870 /* disable pause frames */ 1871 t3_set_reg_field(pi->adapter, A_XGM_TX_CFG + pi->mac.offset, 1872 F_TXPAUSEEN, 0); 1873 1874 /* Reset RX FIFO HWM */ 1875 t3_set_reg_field(pi->adapter, A_XGM_RXFIFO_CFG + pi->mac.offset, 1876 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1877 1878 1879 ADAPTER_LOCK(pi->adapter); 1880 clrbit(&pi->adapter->open_device_map, pi->port_id); 1881 1882 if (pi->adapter->open_device_map == 0) { 1883 cxgb_down_locked(pi->adapter); 1884 } else 1885 ADAPTER_UNLOCK(pi->adapter); 1886 1887 #if !defined(LINK_ATTACH) 1888 DELAY(100); 1889 1890 /* Wait for TXFIFO empty */ 1891 t3_wait_op_done(pi->adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 1892 F_TXFIFO_EMPTY, 1, 20, 5); 1893 1894 DELAY(100); 1895 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1896 1897 pi->phy.ops->power_down(&pi->phy, 1); 1898 #endif 1899 1900 } 1901 1902 static int 1903 cxgb_set_mtu(struct port_info *p, int mtu) 1904 { 1905 struct ifnet *ifp = p->ifp; 1906 int error = 0; 1907 1908 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1909 error = EINVAL; 1910 else if (ifp->if_mtu != mtu) { 1911 PORT_LOCK(p); 1912 ifp->if_mtu = mtu; 1913 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1914 cxgb_stop_locked(p); 1915 cxgb_init_locked(p); 1916 } 1917 PORT_UNLOCK(p); 1918 } 1919 return (error); 1920 } 1921 1922 static int 1923 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1924 { 1925 struct port_info *p = ifp->if_softc; 1926 struct ifaddr *ifa = (struct ifaddr *)data; 1927 struct ifreq *ifr = (struct ifreq *)data; 1928 int flags, error = 0, reinit = 0; 1929 uint32_t mask; 1930 1931 /* 1932 * XXX need to check that we aren't in the middle of an unload 1933 */ 1934 switch (command) { 1935 case SIOCSIFMTU: 1936 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1937 break; 1938 case SIOCSIFADDR: 1939 if (ifa->ifa_addr->sa_family == AF_INET) { 1940 ifp->if_flags |= IFF_UP; 1941 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1942 PORT_LOCK(p); 1943 cxgb_init_locked(p); 1944 PORT_UNLOCK(p); 1945 } 1946 arp_ifinit(ifp, ifa); 1947 } else 1948 error = ether_ioctl(ifp, command, data); 1949 break; 1950 case SIOCSIFFLAGS: 1951 PORT_LOCK(p); 1952 if (ifp->if_flags & IFF_UP) { 1953 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1954 flags = p->if_flags; 1955 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1956 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1957 cxgb_set_rxmode(p); 1958 } else 1959 cxgb_init_locked(p); 1960 p->if_flags = ifp->if_flags; 1961 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1962 cxgb_stop_locked(p); 1963 1964 PORT_UNLOCK(p); 1965 break; 1966 case SIOCADDMULTI: 1967 case SIOCDELMULTI: 1968 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1969 cxgb_set_rxmode(p); 1970 } 1971 break; 1972 case SIOCSIFMEDIA: 1973 case SIOCGIFMEDIA: 1974 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1975 break; 1976 case SIOCSIFCAP: 1977 PORT_LOCK(p); 1978 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1979 if (mask & IFCAP_TXCSUM) { 1980 if (IFCAP_TXCSUM & ifp->if_capenable) { 1981 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 1982 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 1983 | CSUM_IP | CSUM_TSO); 1984 } else { 1985 ifp->if_capenable |= IFCAP_TXCSUM; 1986 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP 1987 | CSUM_IP); 1988 } 1989 } 1990 if (mask & IFCAP_RXCSUM) { 1991 ifp->if_capenable ^= IFCAP_RXCSUM; 1992 } 1993 if (mask & IFCAP_TSO4) { 1994 if (IFCAP_TSO4 & ifp->if_capenable) { 1995 ifp->if_capenable &= ~IFCAP_TSO4; 1996 ifp->if_hwassist &= ~CSUM_TSO; 1997 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 1998 ifp->if_capenable |= IFCAP_TSO4; 1999 ifp->if_hwassist |= CSUM_TSO; 2000 } else { 2001 if (cxgb_debug) 2002 printf("cxgb requires tx checksum offload" 2003 " be enabled to use TSO\n"); 2004 error = EINVAL; 2005 } 2006 } 2007 if (mask & IFCAP_VLAN_HWTAGGING) { 2008 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2009 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2010 } 2011 if (mask & IFCAP_VLAN_MTU) { 2012 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2013 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2014 } 2015 if (mask & IFCAP_VLAN_HWCSUM) { 2016 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2017 } 2018 if (reinit) { 2019 cxgb_stop_locked(p); 2020 cxgb_init_locked(p); 2021 } 2022 PORT_UNLOCK(p); 2023 2024 #ifdef VLAN_CAPABILITIES 2025 VLAN_CAPABILITIES(ifp); 2026 #endif 2027 break; 2028 default: 2029 error = ether_ioctl(ifp, command, data); 2030 break; 2031 } 2032 return (error); 2033 } 2034 2035 static int 2036 cxgb_media_change(struct ifnet *ifp) 2037 { 2038 if_printf(ifp, "media change not supported\n"); 2039 return (ENXIO); 2040 } 2041 2042 static void 2043 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2044 { 2045 struct port_info *p = ifp->if_softc; 2046 2047 ifmr->ifm_status = IFM_AVALID; 2048 ifmr->ifm_active = IFM_ETHER; 2049 2050 if (!p->link_config.link_ok) 2051 return; 2052 2053 ifmr->ifm_status |= IFM_ACTIVE; 2054 2055 switch (p->link_config.speed) { 2056 case 10: 2057 ifmr->ifm_active |= IFM_10_T; 2058 break; 2059 case 100: 2060 ifmr->ifm_active |= IFM_100_TX; 2061 break; 2062 case 1000: 2063 ifmr->ifm_active |= IFM_1000_T; 2064 break; 2065 } 2066 2067 if (p->link_config.duplex) 2068 ifmr->ifm_active |= IFM_FDX; 2069 else 2070 ifmr->ifm_active |= IFM_HDX; 2071 } 2072 2073 static void 2074 cxgb_async_intr(void *data) 2075 { 2076 adapter_t *sc = data; 2077 2078 if (cxgb_debug) 2079 device_printf(sc->dev, "cxgb_async_intr\n"); 2080 /* 2081 * May need to sleep - defer to taskqueue 2082 */ 2083 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2084 } 2085 2086 static void 2087 cxgb_ext_intr_handler(void *arg, int count) 2088 { 2089 adapter_t *sc = (adapter_t *)arg; 2090 2091 if (cxgb_debug) 2092 printf("cxgb_ext_intr_handler\n"); 2093 2094 t3_phy_intr_handler(sc); 2095 2096 /* Now reenable external interrupts */ 2097 ADAPTER_LOCK(sc); 2098 if (sc->slow_intr_mask) { 2099 sc->slow_intr_mask |= F_T3DBG; 2100 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2101 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2102 } 2103 ADAPTER_UNLOCK(sc); 2104 } 2105 2106 static void 2107 check_link_status(adapter_t *sc) 2108 { 2109 int i; 2110 2111 for (i = 0; i < (sc)->params.nports; ++i) { 2112 struct port_info *p = &sc->port[i]; 2113 2114 if (!(p->phy.caps & SUPPORTED_IRQ)) 2115 t3_link_changed(sc, i); 2116 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2117 } 2118 } 2119 2120 static void 2121 check_t3b2_mac(struct adapter *adapter) 2122 { 2123 int i; 2124 2125 if(adapter->flags & CXGB_SHUTDOWN) 2126 return; 2127 2128 for_each_port(adapter, i) { 2129 struct port_info *p = &adapter->port[i]; 2130 struct ifnet *ifp = p->ifp; 2131 int status; 2132 2133 if(adapter->flags & CXGB_SHUTDOWN) 2134 return; 2135 2136 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2137 continue; 2138 2139 status = 0; 2140 PORT_LOCK(p); 2141 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2142 status = t3b2_mac_watchdog_task(&p->mac); 2143 if (status == 1) 2144 p->mac.stats.num_toggled++; 2145 else if (status == 2) { 2146 struct cmac *mac = &p->mac; 2147 int mtu = ifp->if_mtu; 2148 2149 if (ifp->if_capenable & IFCAP_VLAN_MTU) 2150 mtu += ETHER_VLAN_ENCAP_LEN; 2151 t3_mac_set_mtu(mac, mtu); 2152 t3_mac_set_address(mac, 0, p->hw_addr); 2153 cxgb_set_rxmode(p); 2154 t3_link_start(&p->phy, mac, &p->link_config); 2155 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2156 t3_port_intr_enable(adapter, p->port_id); 2157 p->mac.stats.num_resets++; 2158 } 2159 PORT_UNLOCK(p); 2160 } 2161 } 2162 2163 static void 2164 cxgb_tick(void *arg) 2165 { 2166 adapter_t *sc = (adapter_t *)arg; 2167 2168 if(sc->flags & CXGB_SHUTDOWN) 2169 return; 2170 2171 taskqueue_enqueue(sc->tq, &sc->tick_task); 2172 callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); 2173 } 2174 2175 static void 2176 cxgb_tick_handler(void *arg, int count) 2177 { 2178 adapter_t *sc = (adapter_t *)arg; 2179 const struct adapter_params *p = &sc->params; 2180 2181 if(sc->flags & CXGB_SHUTDOWN) 2182 return; 2183 2184 ADAPTER_LOCK(sc); 2185 if (p->linkpoll_period) 2186 check_link_status(sc); 2187 2188 /* 2189 * adapter lock can currently only be acquired after the 2190 * port lock 2191 */ 2192 ADAPTER_UNLOCK(sc); 2193 2194 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2195 check_t3b2_mac(sc); 2196 } 2197 2198 static void 2199 touch_bars(device_t dev) 2200 { 2201 /* 2202 * Don't enable yet 2203 */ 2204 #if !defined(__LP64__) && 0 2205 u32 v; 2206 2207 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2208 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2209 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2210 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2211 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2212 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2213 #endif 2214 } 2215 2216 static int 2217 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2218 { 2219 uint8_t *buf; 2220 int err = 0; 2221 u32 aligned_offset, aligned_len, *p; 2222 struct adapter *adapter = pi->adapter; 2223 2224 2225 aligned_offset = offset & ~3; 2226 aligned_len = (len + (offset & 3) + 3) & ~3; 2227 2228 if (aligned_offset != offset || aligned_len != len) { 2229 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2230 if (!buf) 2231 return (ENOMEM); 2232 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2233 if (!err && aligned_len > 4) 2234 err = t3_seeprom_read(adapter, 2235 aligned_offset + aligned_len - 4, 2236 (u32 *)&buf[aligned_len - 4]); 2237 if (err) 2238 goto out; 2239 memcpy(buf + (offset & 3), data, len); 2240 } else 2241 buf = (uint8_t *)(uintptr_t)data; 2242 2243 err = t3_seeprom_wp(adapter, 0); 2244 if (err) 2245 goto out; 2246 2247 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2248 err = t3_seeprom_write(adapter, aligned_offset, *p); 2249 aligned_offset += 4; 2250 } 2251 2252 if (!err) 2253 err = t3_seeprom_wp(adapter, 1); 2254 out: 2255 if (buf != data) 2256 free(buf, M_DEVBUF); 2257 return err; 2258 } 2259 2260 2261 static int 2262 in_range(int val, int lo, int hi) 2263 { 2264 return val < 0 || (val <= hi && val >= lo); 2265 } 2266 2267 static int 2268 cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2269 { 2270 return (0); 2271 } 2272 2273 static int 2274 cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2275 { 2276 return (0); 2277 } 2278 2279 static int 2280 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2281 int fflag, struct thread *td) 2282 { 2283 int mmd, error = 0; 2284 struct port_info *pi = dev->si_drv1; 2285 adapter_t *sc = pi->adapter; 2286 2287 #ifdef PRIV_SUPPORTED 2288 if (priv_check(td, PRIV_DRIVER)) { 2289 if (cxgb_debug) 2290 printf("user does not have access to privileged ioctls\n"); 2291 return (EPERM); 2292 } 2293 #else 2294 if (suser(td)) { 2295 if (cxgb_debug) 2296 printf("user does not have access to privileged ioctls\n"); 2297 return (EPERM); 2298 } 2299 #endif 2300 2301 switch (cmd) { 2302 case SIOCGMIIREG: { 2303 uint32_t val; 2304 struct cphy *phy = &pi->phy; 2305 struct mii_data *mid = (struct mii_data *)data; 2306 2307 if (!phy->mdio_read) 2308 return (EOPNOTSUPP); 2309 if (is_10G(sc)) { 2310 mmd = mid->phy_id >> 8; 2311 if (!mmd) 2312 mmd = MDIO_DEV_PCS; 2313 else if (mmd > MDIO_DEV_XGXS) 2314 return (EINVAL); 2315 2316 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2317 mid->reg_num, &val); 2318 } else 2319 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2320 mid->reg_num & 0x1f, &val); 2321 if (error == 0) 2322 mid->val_out = val; 2323 break; 2324 } 2325 case SIOCSMIIREG: { 2326 struct cphy *phy = &pi->phy; 2327 struct mii_data *mid = (struct mii_data *)data; 2328 2329 if (!phy->mdio_write) 2330 return (EOPNOTSUPP); 2331 if (is_10G(sc)) { 2332 mmd = mid->phy_id >> 8; 2333 if (!mmd) 2334 mmd = MDIO_DEV_PCS; 2335 else if (mmd > MDIO_DEV_XGXS) 2336 return (EINVAL); 2337 2338 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2339 mmd, mid->reg_num, mid->val_in); 2340 } else 2341 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2342 mid->reg_num & 0x1f, 2343 mid->val_in); 2344 break; 2345 } 2346 case CHELSIO_SETREG: { 2347 struct ch_reg *edata = (struct ch_reg *)data; 2348 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2349 return (EFAULT); 2350 t3_write_reg(sc, edata->addr, edata->val); 2351 break; 2352 } 2353 case CHELSIO_GETREG: { 2354 struct ch_reg *edata = (struct ch_reg *)data; 2355 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2356 return (EFAULT); 2357 edata->val = t3_read_reg(sc, edata->addr); 2358 break; 2359 } 2360 case CHELSIO_GET_SGE_CONTEXT: { 2361 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2362 mtx_lock_spin(&sc->sge.reg_lock); 2363 switch (ecntxt->cntxt_type) { 2364 case CNTXT_TYPE_EGRESS: 2365 error = t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2366 ecntxt->data); 2367 break; 2368 case CNTXT_TYPE_FL: 2369 error = t3_sge_read_fl(sc, ecntxt->cntxt_id, 2370 ecntxt->data); 2371 break; 2372 case CNTXT_TYPE_RSP: 2373 error = t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2374 ecntxt->data); 2375 break; 2376 case CNTXT_TYPE_CQ: 2377 error = t3_sge_read_cq(sc, ecntxt->cntxt_id, 2378 ecntxt->data); 2379 break; 2380 default: 2381 error = EINVAL; 2382 break; 2383 } 2384 mtx_unlock_spin(&sc->sge.reg_lock); 2385 break; 2386 } 2387 case CHELSIO_GET_SGE_DESC: { 2388 struct ch_desc *edesc = (struct ch_desc *)data; 2389 int ret; 2390 if (edesc->queue_num >= SGE_QSETS * 6) 2391 return (EINVAL); 2392 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2393 edesc->queue_num % 6, edesc->idx, edesc->data); 2394 if (ret < 0) 2395 return (EINVAL); 2396 edesc->size = ret; 2397 break; 2398 } 2399 case CHELSIO_SET_QSET_PARAMS: { 2400 struct qset_params *q; 2401 struct ch_qset_params *t = (struct ch_qset_params *)data; 2402 int i; 2403 2404 if (t->qset_idx >= SGE_QSETS) 2405 return (EINVAL); 2406 if (!in_range(t->intr_lat, 0, M_NEWTIMER) || 2407 !in_range(t->cong_thres, 0, 255) || 2408 !in_range(t->txq_size[0], MIN_TXQ_ENTRIES, 2409 MAX_TXQ_ENTRIES) || 2410 !in_range(t->txq_size[1], MIN_TXQ_ENTRIES, 2411 MAX_TXQ_ENTRIES) || 2412 !in_range(t->txq_size[2], MIN_CTRL_TXQ_ENTRIES, 2413 MAX_CTRL_TXQ_ENTRIES) || 2414 !in_range(t->fl_size[0], MIN_FL_ENTRIES, MAX_RX_BUFFERS) || 2415 !in_range(t->fl_size[1], MIN_FL_ENTRIES, 2416 MAX_RX_JUMBO_BUFFERS) || 2417 !in_range(t->rspq_size, MIN_RSPQ_ENTRIES, MAX_RSPQ_ENTRIES)) 2418 return (EINVAL); 2419 2420 if ((sc->flags & FULL_INIT_DONE) && t->lro > 0) 2421 for_each_port(sc, i) { 2422 pi = adap2pinfo(sc, i); 2423 if (t->qset_idx >= pi->first_qset && 2424 t->qset_idx < pi->first_qset + pi->nqsets 2425 #if 0 2426 && !pi->rx_csum_offload 2427 #endif 2428 ) 2429 return -EINVAL; 2430 } 2431 if ((sc->flags & FULL_INIT_DONE) && 2432 (t->rspq_size >= 0 || t->fl_size[0] >= 0 || 2433 t->fl_size[1] >= 0 || t->txq_size[0] >= 0 || 2434 t->txq_size[1] >= 0 || t->txq_size[2] >= 0 || 2435 t->polling >= 0 || t->cong_thres >= 0)) 2436 return (EBUSY); 2437 2438 q = &sc->params.sge.qset[t->qset_idx]; 2439 2440 if (t->rspq_size >= 0) 2441 q->rspq_size = t->rspq_size; 2442 if (t->fl_size[0] >= 0) 2443 q->fl_size = t->fl_size[0]; 2444 if (t->fl_size[1] >= 0) 2445 q->jumbo_size = t->fl_size[1]; 2446 if (t->txq_size[0] >= 0) 2447 q->txq_size[0] = t->txq_size[0]; 2448 if (t->txq_size[1] >= 0) 2449 q->txq_size[1] = t->txq_size[1]; 2450 if (t->txq_size[2] >= 0) 2451 q->txq_size[2] = t->txq_size[2]; 2452 if (t->cong_thres >= 0) 2453 q->cong_thres = t->cong_thres; 2454 if (t->intr_lat >= 0) { 2455 struct sge_qset *qs = &sc->sge.qs[t->qset_idx]; 2456 2457 q->coalesce_usecs = t->intr_lat; 2458 t3_update_qset_coalesce(qs, q); 2459 } 2460 break; 2461 } 2462 case CHELSIO_GET_QSET_PARAMS: { 2463 struct qset_params *q; 2464 struct ch_qset_params *t = (struct ch_qset_params *)data; 2465 2466 if (t->qset_idx >= SGE_QSETS) 2467 return (EINVAL); 2468 2469 q = &(sc)->params.sge.qset[t->qset_idx]; 2470 t->rspq_size = q->rspq_size; 2471 t->txq_size[0] = q->txq_size[0]; 2472 t->txq_size[1] = q->txq_size[1]; 2473 t->txq_size[2] = q->txq_size[2]; 2474 t->fl_size[0] = q->fl_size; 2475 t->fl_size[1] = q->jumbo_size; 2476 t->polling = q->polling; 2477 t->intr_lat = q->coalesce_usecs; 2478 t->cong_thres = q->cong_thres; 2479 break; 2480 } 2481 case CHELSIO_SET_QSET_NUM: { 2482 struct ch_reg *edata = (struct ch_reg *)data; 2483 unsigned int port_idx = pi->port_id; 2484 2485 if (sc->flags & FULL_INIT_DONE) 2486 return (EBUSY); 2487 if (edata->val < 1 || 2488 (edata->val > 1 && !(sc->flags & USING_MSIX))) 2489 return (EINVAL); 2490 if (edata->val + sc->port[!port_idx].nqsets > SGE_QSETS) 2491 return (EINVAL); 2492 sc->port[port_idx].nqsets = edata->val; 2493 sc->port[0].first_qset = 0; 2494 /* 2495 * XXX hardcode ourselves to 2 ports just like LEEENUX 2496 */ 2497 sc->port[1].first_qset = sc->port[0].nqsets; 2498 break; 2499 } 2500 case CHELSIO_GET_QSET_NUM: { 2501 struct ch_reg *edata = (struct ch_reg *)data; 2502 edata->val = pi->nqsets; 2503 break; 2504 } 2505 #ifdef notyet 2506 case CHELSIO_LOAD_FW: 2507 case CHELSIO_GET_PM: 2508 case CHELSIO_SET_PM: 2509 return (EOPNOTSUPP); 2510 break; 2511 #endif 2512 case CHELSIO_SETMTUTAB: { 2513 struct ch_mtus *m = (struct ch_mtus *)data; 2514 int i; 2515 2516 if (!is_offload(sc)) 2517 return (EOPNOTSUPP); 2518 if (offload_running(sc)) 2519 return (EBUSY); 2520 if (m->nmtus != NMTUS) 2521 return (EINVAL); 2522 if (m->mtus[0] < 81) /* accommodate SACK */ 2523 return (EINVAL); 2524 2525 /* 2526 * MTUs must be in ascending order 2527 */ 2528 for (i = 1; i < NMTUS; ++i) 2529 if (m->mtus[i] < m->mtus[i - 1]) 2530 return (EINVAL); 2531 2532 memcpy(sc->params.mtus, m->mtus, 2533 sizeof(sc->params.mtus)); 2534 break; 2535 } 2536 case CHELSIO_GETMTUTAB: { 2537 struct ch_mtus *m = (struct ch_mtus *)data; 2538 2539 if (!is_offload(sc)) 2540 return (EOPNOTSUPP); 2541 2542 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2543 m->nmtus = NMTUS; 2544 break; 2545 } 2546 case CHELSIO_DEVUP: 2547 if (!is_offload(sc)) 2548 return (EOPNOTSUPP); 2549 return offload_open(pi); 2550 break; 2551 case CHELSIO_GET_MEM: { 2552 struct ch_mem_range *t = (struct ch_mem_range *)data; 2553 struct mc7 *mem; 2554 uint8_t *useraddr; 2555 u64 buf[32]; 2556 2557 if (!is_offload(sc)) 2558 return (EOPNOTSUPP); 2559 if (!(sc->flags & FULL_INIT_DONE)) 2560 return (EIO); /* need the memory controllers */ 2561 if ((t->addr & 0x7) || (t->len & 0x7)) 2562 return (EINVAL); 2563 if (t->mem_id == MEM_CM) 2564 mem = &sc->cm; 2565 else if (t->mem_id == MEM_PMRX) 2566 mem = &sc->pmrx; 2567 else if (t->mem_id == MEM_PMTX) 2568 mem = &sc->pmtx; 2569 else 2570 return (EINVAL); 2571 2572 /* 2573 * Version scheme: 2574 * bits 0..9: chip version 2575 * bits 10..15: chip revision 2576 */ 2577 t->version = 3 | (sc->params.rev << 10); 2578 2579 /* 2580 * Read 256 bytes at a time as len can be large and we don't 2581 * want to use huge intermediate buffers. 2582 */ 2583 useraddr = (uint8_t *)t->buf; 2584 while (t->len) { 2585 unsigned int chunk = min(t->len, sizeof(buf)); 2586 2587 error = t3_mc7_bd_read(mem, t->addr / 8, chunk / 8, buf); 2588 if (error) 2589 return (-error); 2590 if (copyout(buf, useraddr, chunk)) 2591 return (EFAULT); 2592 useraddr += chunk; 2593 t->addr += chunk; 2594 t->len -= chunk; 2595 } 2596 break; 2597 } 2598 case CHELSIO_READ_TCAM_WORD: { 2599 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2600 2601 if (!is_offload(sc)) 2602 return (EOPNOTSUPP); 2603 if (!(sc->flags & FULL_INIT_DONE)) 2604 return (EIO); /* need MC5 */ 2605 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2606 break; 2607 } 2608 case CHELSIO_SET_TRACE_FILTER: { 2609 struct ch_trace *t = (struct ch_trace *)data; 2610 const struct trace_params *tp; 2611 2612 tp = (const struct trace_params *)&t->sip; 2613 if (t->config_tx) 2614 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2615 t->trace_tx); 2616 if (t->config_rx) 2617 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2618 t->trace_rx); 2619 break; 2620 } 2621 case CHELSIO_SET_PKTSCHED: { 2622 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2623 if (sc->open_device_map == 0) 2624 return (EAGAIN); 2625 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2626 p->binding); 2627 break; 2628 } 2629 case CHELSIO_IFCONF_GETREGS: { 2630 struct ifconf_regs *regs = (struct ifconf_regs *)data; 2631 int reglen = cxgb_get_regs_len(); 2632 uint8_t *buf = malloc(REGDUMP_SIZE, M_DEVBUF, M_NOWAIT); 2633 if (buf == NULL) { 2634 return (ENOMEM); 2635 } if (regs->len > reglen) 2636 regs->len = reglen; 2637 else if (regs->len < reglen) { 2638 error = E2BIG; 2639 goto done; 2640 } 2641 cxgb_get_regs(sc, regs, buf); 2642 error = copyout(buf, regs->data, reglen); 2643 2644 done: 2645 free(buf, M_DEVBUF); 2646 2647 break; 2648 } 2649 case CHELSIO_SET_HW_SCHED: { 2650 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2651 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2652 2653 if ((sc->flags & FULL_INIT_DONE) == 0) 2654 return (EAGAIN); /* need TP to be initialized */ 2655 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2656 !in_range(t->channel, 0, 1) || 2657 !in_range(t->kbps, 0, 10000000) || 2658 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2659 !in_range(t->flow_ipg, 0, 2660 dack_ticks_to_usec(sc, 0x7ff))) 2661 return (EINVAL); 2662 2663 if (t->kbps >= 0) { 2664 error = t3_config_sched(sc, t->kbps, t->sched); 2665 if (error < 0) 2666 return (-error); 2667 } 2668 if (t->class_ipg >= 0) 2669 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2670 if (t->flow_ipg >= 0) { 2671 t->flow_ipg *= 1000; /* us -> ns */ 2672 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2673 } 2674 if (t->mode >= 0) { 2675 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2676 2677 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2678 bit, t->mode ? bit : 0); 2679 } 2680 if (t->channel >= 0) 2681 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2682 1 << t->sched, t->channel << t->sched); 2683 break; 2684 } 2685 default: 2686 return (EOPNOTSUPP); 2687 break; 2688 } 2689 2690 return (error); 2691 } 2692 2693 static __inline void 2694 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2695 unsigned int end) 2696 { 2697 uint32_t *p = (uint32_t *)buf + start; 2698 2699 for ( ; start <= end; start += sizeof(uint32_t)) 2700 *p++ = t3_read_reg(ap, start); 2701 } 2702 2703 #define T3_REGMAP_SIZE (3 * 1024) 2704 static int 2705 cxgb_get_regs_len(void) 2706 { 2707 return T3_REGMAP_SIZE; 2708 } 2709 #undef T3_REGMAP_SIZE 2710 2711 static void 2712 cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf) 2713 { 2714 2715 /* 2716 * Version scheme: 2717 * bits 0..9: chip version 2718 * bits 10..15: chip revision 2719 * bit 31: set for PCIe cards 2720 */ 2721 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2722 2723 /* 2724 * We skip the MAC statistics registers because they are clear-on-read. 2725 * Also reading multi-register stats would need to synchronize with the 2726 * periodic mac stats accumulation. Hard to justify the complexity. 2727 */ 2728 memset(buf, 0, REGDUMP_SIZE); 2729 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2730 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2731 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2732 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2733 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2734 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2735 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2736 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2737 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2738 } 2739 2740 2741 MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 2742