1 /************************************************************************** 2 3 Copyright (c) 2007-2008, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/pciio.h> 39 #include <sys/conf.h> 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/bus_dma.h> 43 #include <sys/ktr.h> 44 #include <sys/rman.h> 45 #include <sys/ioccom.h> 46 #include <sys/mbuf.h> 47 #include <sys/linker.h> 48 #include <sys/firmware.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/smp.h> 52 #include <sys/sysctl.h> 53 #include <sys/syslog.h> 54 #include <sys/queue.h> 55 #include <sys/taskqueue.h> 56 #include <sys/proc.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 #include <net/if_vlan_var.h> 66 67 #include <netinet/in_systm.h> 68 #include <netinet/in.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pci_private.h> 78 79 #include <cxgb_include.h> 80 81 #ifdef PRIV_SUPPORTED 82 #include <sys/priv.h> 83 #endif 84 85 static int cxgb_setup_msix(adapter_t *, int); 86 static void cxgb_teardown_msix(adapter_t *); 87 static void cxgb_init(void *); 88 static void cxgb_init_locked(struct port_info *); 89 static void cxgb_stop_locked(struct port_info *); 90 static void cxgb_set_rxmode(struct port_info *); 91 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 92 static int cxgb_media_change(struct ifnet *); 93 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 94 static int setup_sge_qsets(adapter_t *); 95 static void cxgb_async_intr(void *); 96 static void cxgb_ext_intr_handler(void *, int); 97 static void cxgb_tick_handler(void *, int); 98 static void cxgb_down_locked(struct adapter *sc); 99 static void cxgb_tick(void *); 100 static void setup_rss(adapter_t *sc); 101 102 /* Attachment glue for the PCI controller end of the device. Each port of 103 * the device is attached separately, as defined later. 104 */ 105 static int cxgb_controller_probe(device_t); 106 static int cxgb_controller_attach(device_t); 107 static int cxgb_controller_detach(device_t); 108 static void cxgb_free(struct adapter *); 109 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 110 unsigned int end); 111 static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); 112 static int cxgb_get_regs_len(void); 113 static int offload_open(struct port_info *pi); 114 static void touch_bars(device_t dev); 115 static int offload_close(struct t3cdev *tdev); 116 static void cxgb_link_start(struct port_info *p); 117 118 static device_method_t cxgb_controller_methods[] = { 119 DEVMETHOD(device_probe, cxgb_controller_probe), 120 DEVMETHOD(device_attach, cxgb_controller_attach), 121 DEVMETHOD(device_detach, cxgb_controller_detach), 122 123 /* bus interface */ 124 DEVMETHOD(bus_print_child, bus_generic_print_child), 125 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 126 127 { 0, 0 } 128 }; 129 130 static driver_t cxgb_controller_driver = { 131 "cxgbc", 132 cxgb_controller_methods, 133 sizeof(struct adapter) 134 }; 135 136 static devclass_t cxgb_controller_devclass; 137 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 138 139 /* 140 * Attachment glue for the ports. Attachment is done directly to the 141 * controller device. 142 */ 143 static int cxgb_port_probe(device_t); 144 static int cxgb_port_attach(device_t); 145 static int cxgb_port_detach(device_t); 146 147 static device_method_t cxgb_port_methods[] = { 148 DEVMETHOD(device_probe, cxgb_port_probe), 149 DEVMETHOD(device_attach, cxgb_port_attach), 150 DEVMETHOD(device_detach, cxgb_port_detach), 151 { 0, 0 } 152 }; 153 154 static driver_t cxgb_port_driver = { 155 "cxgb", 156 cxgb_port_methods, 157 0 158 }; 159 160 static d_ioctl_t cxgb_extension_ioctl; 161 static d_open_t cxgb_extension_open; 162 static d_close_t cxgb_extension_close; 163 164 static struct cdevsw cxgb_cdevsw = { 165 .d_version = D_VERSION, 166 .d_flags = 0, 167 .d_open = cxgb_extension_open, 168 .d_close = cxgb_extension_close, 169 .d_ioctl = cxgb_extension_ioctl, 170 .d_name = "cxgb", 171 }; 172 173 static devclass_t cxgb_port_devclass; 174 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 175 176 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 177 178 /* 179 * The driver uses the best interrupt scheme available on a platform in the 180 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 181 * of these schemes the driver may consider as follows: 182 * 183 * msi = 2: choose from among all three options 184 * msi = 1 : only consider MSI and pin interrupts 185 * msi = 0: force pin interrupts 186 */ 187 static int msi_allowed = 2; 188 189 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 190 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 191 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 192 "MSI-X, MSI, INTx selector"); 193 194 /* 195 * The driver enables offload as a default. 196 * To disable it, use ofld_disable = 1. 197 */ 198 static int ofld_disable = 0; 199 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 200 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 201 "disable ULP offload"); 202 203 /* 204 * The driver uses an auto-queue algorithm by default. 205 * To disable it and force a single queue-set per port, use multiq = 0 206 */ 207 static int multiq = 1; 208 TUNABLE_INT("hw.cxgb.multiq", &multiq); 209 SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0, 210 "use min(ncpus/ports, 8) queue-sets per port"); 211 212 /* 213 * By default the driver will not update the firmware unless 214 * it was compiled against a newer version 215 * 216 */ 217 static int force_fw_update = 0; 218 TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 219 SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 220 "update firmware even if up to date"); 221 222 int cxgb_use_16k_clusters = 1; 223 TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 224 SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 225 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 226 227 enum { 228 MAX_TXQ_ENTRIES = 16384, 229 MAX_CTRL_TXQ_ENTRIES = 1024, 230 MAX_RSPQ_ENTRIES = 16384, 231 MAX_RX_BUFFERS = 16384, 232 MAX_RX_JUMBO_BUFFERS = 16384, 233 MIN_TXQ_ENTRIES = 4, 234 MIN_CTRL_TXQ_ENTRIES = 4, 235 MIN_RSPQ_ENTRIES = 32, 236 MIN_FL_ENTRIES = 32, 237 MIN_FL_JUMBO_ENTRIES = 32 238 }; 239 240 struct filter_info { 241 u32 sip; 242 u32 sip_mask; 243 u32 dip; 244 u16 sport; 245 u16 dport; 246 u32 vlan:12; 247 u32 vlan_prio:3; 248 u32 mac_hit:1; 249 u32 mac_idx:4; 250 u32 mac_vld:1; 251 u32 pkt_type:2; 252 u32 report_filter_id:1; 253 u32 pass:1; 254 u32 rss:1; 255 u32 qset:3; 256 u32 locked:1; 257 u32 valid:1; 258 }; 259 260 enum { FILTER_NO_VLAN_PRI = 7 }; 261 262 #define EEPROM_MAGIC 0x38E2F10C 263 264 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 265 266 /* Table for probing the cards. The desc field isn't actually used */ 267 struct cxgb_ident { 268 uint16_t vendor; 269 uint16_t device; 270 int index; 271 char *desc; 272 } cxgb_identifiers[] = { 273 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 274 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 275 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 276 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 277 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 278 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 279 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 280 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 281 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "N310E"}, 285 {0, 0, 0, NULL} 286 }; 287 288 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 289 290 291 static __inline char 292 t3rev2char(struct adapter *adapter) 293 { 294 char rev = 'z'; 295 296 switch(adapter->params.rev) { 297 case T3_REV_A: 298 rev = 'a'; 299 break; 300 case T3_REV_B: 301 case T3_REV_B2: 302 rev = 'b'; 303 break; 304 case T3_REV_C: 305 rev = 'c'; 306 break; 307 } 308 return rev; 309 } 310 311 static struct cxgb_ident * 312 cxgb_get_ident(device_t dev) 313 { 314 struct cxgb_ident *id; 315 316 for (id = cxgb_identifiers; id->desc != NULL; id++) { 317 if ((id->vendor == pci_get_vendor(dev)) && 318 (id->device == pci_get_device(dev))) { 319 return (id); 320 } 321 } 322 return (NULL); 323 } 324 325 static const struct adapter_info * 326 cxgb_get_adapter_info(device_t dev) 327 { 328 struct cxgb_ident *id; 329 const struct adapter_info *ai; 330 331 id = cxgb_get_ident(dev); 332 if (id == NULL) 333 return (NULL); 334 335 ai = t3_get_adapter_info(id->index); 336 337 return (ai); 338 } 339 340 static int 341 cxgb_controller_probe(device_t dev) 342 { 343 const struct adapter_info *ai; 344 char *ports, buf[80]; 345 int nports; 346 struct adapter *sc = device_get_softc(dev); 347 348 ai = cxgb_get_adapter_info(dev); 349 if (ai == NULL) 350 return (ENXIO); 351 352 nports = ai->nports0 + ai->nports1; 353 if (nports == 1) 354 ports = "port"; 355 else 356 ports = "ports"; 357 358 snprintf(buf, sizeof(buf), "%s %sNIC, rev: %d nports: %d %s", 359 ai->desc, is_offload(sc) ? "R" : "", 360 sc->params.rev, nports, ports); 361 device_set_desc_copy(dev, buf); 362 return (BUS_PROBE_DEFAULT); 363 } 364 365 #define FW_FNAME "cxgb_t3fw" 366 #define TPEEPROM_NAME "t3b_tp_eeprom" 367 #define TPSRAM_NAME "t3b_protocol_sram" 368 369 static int 370 upgrade_fw(adapter_t *sc) 371 { 372 #ifdef FIRMWARE_LATEST 373 const struct firmware *fw; 374 #else 375 struct firmware *fw; 376 #endif 377 int status; 378 379 if ((fw = firmware_get(FW_FNAME)) == NULL) { 380 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 381 return (ENOENT); 382 } else 383 device_printf(sc->dev, "updating firmware on card\n"); 384 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 385 386 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 387 388 firmware_put(fw, FIRMWARE_UNLOAD); 389 390 return (status); 391 } 392 393 static int 394 cxgb_controller_attach(device_t dev) 395 { 396 device_t child; 397 const struct adapter_info *ai; 398 struct adapter *sc; 399 int i, error = 0; 400 uint32_t vers; 401 int port_qsets = 1; 402 #ifdef MSI_SUPPORTED 403 int msi_needed, reg; 404 #endif 405 int must_load = 0; 406 char buf[80]; 407 408 sc = device_get_softc(dev); 409 sc->dev = dev; 410 sc->msi_count = 0; 411 ai = cxgb_get_adapter_info(dev); 412 413 /* 414 * XXX not really related but a recent addition 415 */ 416 #ifdef MSI_SUPPORTED 417 /* find the PCIe link width and set max read request to 4KB*/ 418 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 419 uint16_t lnk, pectl; 420 lnk = pci_read_config(dev, reg + 0x12, 2); 421 sc->link_width = (lnk >> 4) & 0x3f; 422 423 pectl = pci_read_config(dev, reg + 0x8, 2); 424 pectl = (pectl & ~0x7000) | (5 << 12); 425 pci_write_config(dev, reg + 0x8, pectl, 2); 426 } 427 428 if (sc->link_width != 0 && sc->link_width <= 4 && 429 (ai->nports0 + ai->nports1) <= 2) { 430 device_printf(sc->dev, 431 "PCIe x%d Link, expect reduced performance\n", 432 sc->link_width); 433 } 434 #endif 435 touch_bars(dev); 436 pci_enable_busmaster(dev); 437 /* 438 * Allocate the registers and make them available to the driver. 439 * The registers that we care about for NIC mode are in BAR 0 440 */ 441 sc->regs_rid = PCIR_BAR(0); 442 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 443 &sc->regs_rid, RF_ACTIVE)) == NULL) { 444 device_printf(dev, "Cannot allocate BAR region 0\n"); 445 return (ENXIO); 446 } 447 sc->udbs_rid = PCIR_BAR(2); 448 sc->udbs_res = NULL; 449 if (is_offload(sc) && 450 ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 451 &sc->udbs_rid, RF_ACTIVE)) == NULL)) { 452 device_printf(dev, "Cannot allocate BAR region 1\n"); 453 error = ENXIO; 454 goto out; 455 } 456 457 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 458 device_get_unit(dev)); 459 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 460 461 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 462 device_get_unit(dev)); 463 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 464 device_get_unit(dev)); 465 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 466 device_get_unit(dev)); 467 468 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 469 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 470 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 471 472 sc->bt = rman_get_bustag(sc->regs_res); 473 sc->bh = rman_get_bushandle(sc->regs_res); 474 sc->mmio_len = rman_get_size(sc->regs_res); 475 476 if (t3_prep_adapter(sc, ai, 1) < 0) { 477 printf("prep adapter failed\n"); 478 error = ENODEV; 479 goto out; 480 } 481 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 482 * enough messages for the queue sets. If that fails, try falling 483 * back to MSI. If that fails, then try falling back to the legacy 484 * interrupt pin model. 485 */ 486 #ifdef MSI_SUPPORTED 487 488 sc->msix_regs_rid = 0x20; 489 if ((msi_allowed >= 2) && 490 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 491 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 492 493 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 494 495 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 496 (sc->msi_count != msi_needed)) { 497 device_printf(dev, "msix allocation failed - msi_count = %d" 498 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 499 msi_needed, error); 500 sc->msi_count = 0; 501 pci_release_msi(dev); 502 bus_release_resource(dev, SYS_RES_MEMORY, 503 sc->msix_regs_rid, sc->msix_regs_res); 504 sc->msix_regs_res = NULL; 505 } else { 506 sc->flags |= USING_MSIX; 507 sc->cxgb_intr = t3_intr_msix; 508 } 509 } 510 511 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 512 sc->msi_count = 1; 513 if (pci_alloc_msi(dev, &sc->msi_count)) { 514 device_printf(dev, "alloc msi failed - will try INTx\n"); 515 sc->msi_count = 0; 516 pci_release_msi(dev); 517 } else { 518 sc->flags |= USING_MSI; 519 sc->irq_rid = 1; 520 sc->cxgb_intr = t3_intr_msi; 521 } 522 } 523 #endif 524 if (sc->msi_count == 0) { 525 device_printf(dev, "using line interrupts\n"); 526 sc->irq_rid = 0; 527 sc->cxgb_intr = t3b_intr; 528 } 529 530 if ((sc->flags & USING_MSIX) && multiq) 531 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 532 533 /* Create a private taskqueue thread for handling driver events */ 534 #ifdef TASKQUEUE_CURRENT 535 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 536 taskqueue_thread_enqueue, &sc->tq); 537 #else 538 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 539 taskqueue_thread_enqueue, &sc->tq); 540 #endif 541 if (sc->tq == NULL) { 542 device_printf(dev, "failed to allocate controller task queue\n"); 543 goto out; 544 } 545 546 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 547 device_get_nameunit(dev)); 548 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 549 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 550 551 552 /* Create a periodic callout for checking adapter status */ 553 callout_init(&sc->cxgb_tick_ch, TRUE); 554 555 if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) { 556 /* 557 * Warn user that a firmware update will be attempted in init. 558 */ 559 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 560 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 561 sc->flags &= ~FW_UPTODATE; 562 } else { 563 sc->flags |= FW_UPTODATE; 564 } 565 566 if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) { 567 /* 568 * Warn user that a firmware update will be attempted in init. 569 */ 570 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 571 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 572 sc->flags &= ~TPS_UPTODATE; 573 } else { 574 sc->flags |= TPS_UPTODATE; 575 } 576 577 /* 578 * Create a child device for each MAC. The ethernet attachment 579 * will be done in these children. 580 */ 581 for (i = 0; i < (sc)->params.nports; i++) { 582 struct port_info *pi; 583 584 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 585 device_printf(dev, "failed to add child port\n"); 586 error = EINVAL; 587 goto out; 588 } 589 pi = &sc->port[i]; 590 pi->adapter = sc; 591 pi->nqsets = port_qsets; 592 pi->first_qset = i*port_qsets; 593 pi->port_id = i; 594 pi->tx_chan = i >= ai->nports0; 595 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 596 sc->rxpkt_map[pi->txpkt_intf] = i; 597 sc->port[i].tx_chan = i >= ai->nports0; 598 sc->portdev[i] = child; 599 device_set_softc(child, pi); 600 } 601 if ((error = bus_generic_attach(dev)) != 0) 602 goto out; 603 604 /* initialize sge private state */ 605 t3_sge_init_adapter(sc); 606 607 t3_led_ready(sc); 608 609 cxgb_offload_init(); 610 if (is_offload(sc)) { 611 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 612 cxgb_adapter_ofld(sc); 613 } 614 error = t3_get_fw_version(sc, &vers); 615 if (error) 616 goto out; 617 618 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 619 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 620 G_FW_VERSION_MICRO(vers)); 621 622 snprintf(buf, sizeof(buf), "%s\t E/C: %s S/N: %s", 623 ai->desc, 624 sc->params.vpd.ec, sc->params.vpd.sn); 625 device_set_desc_copy(dev, buf); 626 627 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 628 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 629 t3_add_attach_sysctls(sc); 630 out: 631 if (error) 632 cxgb_free(sc); 633 634 return (error); 635 } 636 637 static int 638 cxgb_controller_detach(device_t dev) 639 { 640 struct adapter *sc; 641 642 sc = device_get_softc(dev); 643 644 cxgb_free(sc); 645 646 return (0); 647 } 648 649 static void 650 cxgb_free(struct adapter *sc) 651 { 652 int i; 653 654 ADAPTER_LOCK(sc); 655 sc->flags |= CXGB_SHUTDOWN; 656 ADAPTER_UNLOCK(sc); 657 cxgb_pcpu_shutdown_threads(sc); 658 ADAPTER_LOCK(sc); 659 660 /* 661 * drops the lock 662 */ 663 cxgb_down_locked(sc); 664 665 #ifdef MSI_SUPPORTED 666 if (sc->flags & (USING_MSI | USING_MSIX)) { 667 device_printf(sc->dev, "releasing msi message(s)\n"); 668 pci_release_msi(sc->dev); 669 } else { 670 device_printf(sc->dev, "no msi message to release\n"); 671 } 672 #endif 673 if (sc->msix_regs_res != NULL) { 674 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 675 sc->msix_regs_res); 676 } 677 678 t3_sge_deinit_sw(sc); 679 /* 680 * Wait for last callout 681 */ 682 683 DELAY(hz*100); 684 685 for (i = 0; i < (sc)->params.nports; ++i) { 686 if (sc->portdev[i] != NULL) 687 device_delete_child(sc->dev, sc->portdev[i]); 688 } 689 690 bus_generic_detach(sc->dev); 691 if (sc->tq != NULL) { 692 taskqueue_free(sc->tq); 693 sc->tq = NULL; 694 } 695 696 if (is_offload(sc)) { 697 cxgb_adapter_unofld(sc); 698 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 699 offload_close(&sc->tdev); 700 else 701 printf("cxgb_free: DEVMAP_BIT not set\n"); 702 } else 703 printf("not offloading set\n"); 704 #ifdef notyet 705 if (sc->flags & CXGB_OFLD_INIT) 706 cxgb_offload_deactivate(sc); 707 #endif 708 free(sc->filters, M_DEVBUF); 709 t3_sge_free(sc); 710 711 cxgb_offload_exit(); 712 713 if (sc->udbs_res != NULL) 714 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 715 sc->udbs_res); 716 717 if (sc->regs_res != NULL) 718 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 719 sc->regs_res); 720 721 MTX_DESTROY(&sc->mdio_lock); 722 MTX_DESTROY(&sc->sge.reg_lock); 723 MTX_DESTROY(&sc->elmer_lock); 724 ADAPTER_LOCK_DEINIT(sc); 725 } 726 727 /** 728 * setup_sge_qsets - configure SGE Tx/Rx/response queues 729 * @sc: the controller softc 730 * 731 * Determines how many sets of SGE queues to use and initializes them. 732 * We support multiple queue sets per port if we have MSI-X, otherwise 733 * just one queue set per port. 734 */ 735 static int 736 setup_sge_qsets(adapter_t *sc) 737 { 738 int i, j, err, irq_idx = 0, qset_idx = 0; 739 u_int ntxq = SGE_TXQ_PER_SET; 740 741 if ((err = t3_sge_alloc(sc)) != 0) { 742 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 743 return (err); 744 } 745 746 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 747 irq_idx = -1; 748 749 for (i = 0; i < (sc)->params.nports; i++) { 750 struct port_info *pi = &sc->port[i]; 751 752 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 753 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 754 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 755 &sc->params.sge.qset[qset_idx], ntxq, pi); 756 if (err) { 757 t3_free_sge_resources(sc); 758 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 759 err); 760 return (err); 761 } 762 } 763 } 764 765 return (0); 766 } 767 768 static void 769 cxgb_teardown_msix(adapter_t *sc) 770 { 771 int i, nqsets; 772 773 for (nqsets = i = 0; i < (sc)->params.nports; i++) 774 nqsets += sc->port[i].nqsets; 775 776 for (i = 0; i < nqsets; i++) { 777 if (sc->msix_intr_tag[i] != NULL) { 778 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 779 sc->msix_intr_tag[i]); 780 sc->msix_intr_tag[i] = NULL; 781 } 782 if (sc->msix_irq_res[i] != NULL) { 783 bus_release_resource(sc->dev, SYS_RES_IRQ, 784 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 785 sc->msix_irq_res[i] = NULL; 786 } 787 } 788 } 789 790 static int 791 cxgb_setup_msix(adapter_t *sc, int msix_count) 792 { 793 int i, j, k, nqsets, rid; 794 795 /* The first message indicates link changes and error conditions */ 796 sc->irq_rid = 1; 797 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 798 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 799 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 800 return (EINVAL); 801 } 802 803 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 804 #ifdef INTR_FILTERS 805 NULL, 806 #endif 807 cxgb_async_intr, sc, &sc->intr_tag)) { 808 device_printf(sc->dev, "Cannot set up interrupt\n"); 809 return (EINVAL); 810 } 811 for (i = k = 0; i < (sc)->params.nports; i++) { 812 nqsets = sc->port[i].nqsets; 813 for (j = 0; j < nqsets; j++, k++) { 814 struct sge_qset *qs = &sc->sge.qs[k]; 815 816 rid = k + 2; 817 if (cxgb_debug) 818 printf("rid=%d ", rid); 819 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 820 sc->dev, SYS_RES_IRQ, &rid, 821 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 822 device_printf(sc->dev, "Cannot allocate " 823 "interrupt for message %d\n", rid); 824 return (EINVAL); 825 } 826 sc->msix_irq_rid[k] = rid; 827 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 828 INTR_MPSAFE|INTR_TYPE_NET, 829 #ifdef INTR_FILTERS 830 NULL, 831 #endif 832 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 833 device_printf(sc->dev, "Cannot set up " 834 "interrupt for message %d\n", rid); 835 return (EINVAL); 836 837 } 838 #if 0 839 #ifdef IFNET_MULTIQUEUE 840 if (multiq) { 841 int vector = rman_get_start(sc->msix_irq_res[k]); 842 if (bootverbose) 843 device_printf(sc->dev, "binding vector=%d to cpu=%d\n", vector, k % mp_ncpus); 844 intr_bind(vector, k % mp_ncpus); 845 } 846 #endif 847 #endif 848 } 849 } 850 851 return (0); 852 } 853 854 static int 855 cxgb_port_probe(device_t dev) 856 { 857 struct port_info *p; 858 char buf[80]; 859 const char *desc; 860 861 p = device_get_softc(dev); 862 desc = p->phy.desc; 863 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 864 device_set_desc_copy(dev, buf); 865 return (0); 866 } 867 868 869 static int 870 cxgb_makedev(struct port_info *pi) 871 { 872 873 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 874 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 875 876 if (pi->port_cdev == NULL) 877 return (ENOMEM); 878 879 pi->port_cdev->si_drv1 = (void *)pi; 880 881 return (0); 882 } 883 884 #ifndef LRO_SUPPORTED 885 #ifdef IFCAP_LRO 886 #undef IFCAP_LRO 887 #endif 888 #define IFCAP_LRO 0x0 889 #endif 890 891 #ifdef TSO_SUPPORTED 892 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO) 893 /* Don't enable TSO6 yet */ 894 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO) 895 #else 896 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 897 /* Don't enable TSO6 yet */ 898 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 899 #define IFCAP_TSO4 0x0 900 #define IFCAP_TSO6 0x0 901 #define CSUM_TSO 0x0 902 #endif 903 904 905 static int 906 cxgb_port_attach(device_t dev) 907 { 908 struct port_info *p; 909 struct ifnet *ifp; 910 int err, media_flags; 911 struct adapter *sc; 912 913 914 p = device_get_softc(dev); 915 sc = p->adapter; 916 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 917 device_get_unit(device_get_parent(dev)), p->port_id); 918 PORT_LOCK_INIT(p, p->lockbuf); 919 920 /* Allocate an ifnet object and set it up */ 921 ifp = p->ifp = if_alloc(IFT_ETHER); 922 if (ifp == NULL) { 923 device_printf(dev, "Cannot allocate ifnet\n"); 924 return (ENOMEM); 925 } 926 927 /* 928 * Note that there is currently no watchdog timer. 929 */ 930 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 931 ifp->if_init = cxgb_init; 932 ifp->if_softc = p; 933 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 934 ifp->if_ioctl = cxgb_ioctl; 935 ifp->if_start = cxgb_start; 936 937 938 ifp->if_timer = 0; /* Disable ifnet watchdog */ 939 ifp->if_watchdog = NULL; 940 941 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 942 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 943 IFQ_SET_READY(&ifp->if_snd); 944 945 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 946 ifp->if_capabilities |= CXGB_CAP; 947 ifp->if_capenable |= CXGB_CAP_ENABLE; 948 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 949 /* 950 * disable TSO on 4-port - it isn't supported by the firmware yet 951 */ 952 if (p->adapter->params.nports > 2) { 953 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 954 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 955 ifp->if_hwassist &= ~CSUM_TSO; 956 } 957 958 ether_ifattach(ifp, p->hw_addr); 959 #ifdef IFNET_MULTIQUEUE 960 ifp->if_transmit = cxgb_pcpu_transmit; 961 #endif 962 /* 963 * Only default to jumbo frames on 10GigE 964 */ 965 if (p->adapter->params.nports <= 2) 966 ifp->if_mtu = ETHERMTU_JUMBO; 967 if ((err = cxgb_makedev(p)) != 0) { 968 printf("makedev failed %d\n", err); 969 return (err); 970 } 971 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 972 cxgb_media_status); 973 974 if (!strcmp(p->phy.desc, "10GBASE-CX4")) { 975 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 976 } else if (!strcmp(p->phy.desc, "10GBASE-SR")) { 977 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 978 } else if (!strcmp(p->phy.desc, "10GBASE-R")) { 979 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 980 } else if (!strcmp(p->phy.desc, "10/100/1000BASE-T")) { 981 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 982 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 983 0, NULL); 984 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 985 0, NULL); 986 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 987 0, NULL); 988 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 989 0, NULL); 990 media_flags = 0; 991 } else if (!strcmp(p->phy.desc, "1000BASE-X")) { 992 /* 993 * XXX: This is not very accurate. Fix when common code 994 * returns more specific value - eg 1000BASE-SX, LX, etc. 995 */ 996 media_flags = IFM_ETHER | IFM_1000_SX | IFM_FDX; 997 } else { 998 printf("unsupported media type %s\n", p->phy.desc); 999 return (ENXIO); 1000 } 1001 if (media_flags) { 1002 ifmedia_add(&p->media, media_flags, 0, NULL); 1003 ifmedia_set(&p->media, media_flags); 1004 } else { 1005 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1006 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1007 } 1008 1009 /* Get the latest mac address, User can use a LAA */ 1010 bcopy(IF_LLADDR(p->ifp), p->hw_addr, ETHER_ADDR_LEN); 1011 t3_sge_init_port(p); 1012 #if defined(LINK_ATTACH) 1013 cxgb_link_start(p); 1014 t3_link_changed(sc, p->port_id); 1015 #endif 1016 return (0); 1017 } 1018 1019 static int 1020 cxgb_port_detach(device_t dev) 1021 { 1022 struct port_info *p; 1023 1024 p = device_get_softc(dev); 1025 1026 PORT_LOCK(p); 1027 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1028 cxgb_stop_locked(p); 1029 PORT_UNLOCK(p); 1030 1031 ether_ifdetach(p->ifp); 1032 printf("waiting for callout to stop ..."); 1033 DELAY(1000000); 1034 printf("done\n"); 1035 /* 1036 * the lock may be acquired in ifdetach 1037 */ 1038 PORT_LOCK_DEINIT(p); 1039 if_free(p->ifp); 1040 1041 if (p->port_cdev != NULL) 1042 destroy_dev(p->port_cdev); 1043 1044 return (0); 1045 } 1046 1047 void 1048 t3_fatal_err(struct adapter *sc) 1049 { 1050 u_int fw_status[4]; 1051 1052 if (sc->flags & FULL_INIT_DONE) { 1053 t3_sge_stop(sc); 1054 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1055 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1056 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1057 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1058 t3_intr_disable(sc); 1059 } 1060 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1061 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1062 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1063 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1064 } 1065 1066 int 1067 t3_os_find_pci_capability(adapter_t *sc, int cap) 1068 { 1069 device_t dev; 1070 struct pci_devinfo *dinfo; 1071 pcicfgregs *cfg; 1072 uint32_t status; 1073 uint8_t ptr; 1074 1075 dev = sc->dev; 1076 dinfo = device_get_ivars(dev); 1077 cfg = &dinfo->cfg; 1078 1079 status = pci_read_config(dev, PCIR_STATUS, 2); 1080 if (!(status & PCIM_STATUS_CAPPRESENT)) 1081 return (0); 1082 1083 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1084 case 0: 1085 case 1: 1086 ptr = PCIR_CAP_PTR; 1087 break; 1088 case 2: 1089 ptr = PCIR_CAP_PTR_2; 1090 break; 1091 default: 1092 return (0); 1093 break; 1094 } 1095 ptr = pci_read_config(dev, ptr, 1); 1096 1097 while (ptr != 0) { 1098 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1099 return (ptr); 1100 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1101 } 1102 1103 return (0); 1104 } 1105 1106 int 1107 t3_os_pci_save_state(struct adapter *sc) 1108 { 1109 device_t dev; 1110 struct pci_devinfo *dinfo; 1111 1112 dev = sc->dev; 1113 dinfo = device_get_ivars(dev); 1114 1115 pci_cfg_save(dev, dinfo, 0); 1116 return (0); 1117 } 1118 1119 int 1120 t3_os_pci_restore_state(struct adapter *sc) 1121 { 1122 device_t dev; 1123 struct pci_devinfo *dinfo; 1124 1125 dev = sc->dev; 1126 dinfo = device_get_ivars(dev); 1127 1128 pci_cfg_restore(dev, dinfo); 1129 return (0); 1130 } 1131 1132 /** 1133 * t3_os_link_changed - handle link status changes 1134 * @adapter: the adapter associated with the link change 1135 * @port_id: the port index whose limk status has changed 1136 * @link_status: the new status of the link 1137 * @speed: the new speed setting 1138 * @duplex: the new duplex setting 1139 * @fc: the new flow-control setting 1140 * 1141 * This is the OS-dependent handler for link status changes. The OS 1142 * neutral handler takes care of most of the processing for these events, 1143 * then calls this handler for any OS-specific processing. 1144 */ 1145 void 1146 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1147 int duplex, int fc) 1148 { 1149 struct port_info *pi = &adapter->port[port_id]; 1150 struct cmac *mac = &adapter->port[port_id].mac; 1151 1152 if (link_status) { 1153 DELAY(10); 1154 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1155 /* Clear errors created by MAC enable */ 1156 t3_set_reg_field(adapter, 1157 A_XGM_STAT_CTRL + pi->mac.offset, 1158 F_CLRSTATS, 1); 1159 if_link_state_change(pi->ifp, LINK_STATE_UP); 1160 1161 } else { 1162 pi->phy.ops->power_down(&pi->phy, 1); 1163 t3_mac_disable(mac, MAC_DIRECTION_RX); 1164 t3_link_start(&pi->phy, mac, &pi->link_config); 1165 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1166 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1167 } 1168 } 1169 1170 /** 1171 * t3_os_phymod_changed - handle PHY module changes 1172 * @phy: the PHY reporting the module change 1173 * @mod_type: new module type 1174 * 1175 * This is the OS-dependent handler for PHY module changes. It is 1176 * invoked when a PHY module is removed or inserted for any OS-specific 1177 * processing. 1178 */ 1179 void t3_os_phymod_changed(struct adapter *adap, int port_id) 1180 { 1181 static const char *mod_str[] = { 1182 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" 1183 }; 1184 1185 struct port_info *pi = &adap->port[port_id]; 1186 1187 if (pi->phy.modtype == phy_modtype_none) 1188 device_printf(adap->dev, "PHY module unplugged\n"); 1189 else { 1190 KASSERT(pi->phy.modtype < ARRAY_SIZE(mod_str), 1191 ("invalid PHY module type %d", pi->phy.modtype)); 1192 device_printf(adap->dev, "%s PHY module inserted\n", 1193 mod_str[pi->phy.modtype]); 1194 } 1195 } 1196 1197 /* 1198 * Interrupt-context handler for external (PHY) interrupts. 1199 */ 1200 void 1201 t3_os_ext_intr_handler(adapter_t *sc) 1202 { 1203 if (cxgb_debug) 1204 printf("t3_os_ext_intr_handler\n"); 1205 /* 1206 * Schedule a task to handle external interrupts as they may be slow 1207 * and we use a mutex to protect MDIO registers. We disable PHY 1208 * interrupts in the meantime and let the task reenable them when 1209 * it's done. 1210 */ 1211 ADAPTER_LOCK(sc); 1212 if (sc->slow_intr_mask) { 1213 sc->slow_intr_mask &= ~F_T3DBG; 1214 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1215 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1216 } 1217 ADAPTER_UNLOCK(sc); 1218 } 1219 1220 void 1221 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1222 { 1223 1224 /* 1225 * The ifnet might not be allocated before this gets called, 1226 * as this is called early on in attach by t3_prep_adapter 1227 * save the address off in the port structure 1228 */ 1229 if (cxgb_debug) 1230 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1231 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1232 } 1233 1234 /** 1235 * link_start - enable a port 1236 * @p: the port to enable 1237 * 1238 * Performs the MAC and PHY actions needed to enable a port. 1239 */ 1240 static void 1241 cxgb_link_start(struct port_info *p) 1242 { 1243 struct ifnet *ifp; 1244 struct t3_rx_mode rm; 1245 struct cmac *mac = &p->mac; 1246 int mtu, hwtagging; 1247 1248 ifp = p->ifp; 1249 1250 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1251 1252 mtu = ifp->if_mtu; 1253 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1254 mtu += ETHER_VLAN_ENCAP_LEN; 1255 1256 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1257 1258 t3_init_rx_mode(&rm, p); 1259 if (!mac->multiport) 1260 t3_mac_reset(mac); 1261 t3_mac_set_mtu(mac, mtu); 1262 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1263 t3_mac_set_address(mac, 0, p->hw_addr); 1264 t3_mac_set_rx_mode(mac, &rm); 1265 t3_link_start(&p->phy, mac, &p->link_config); 1266 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1267 } 1268 1269 1270 static int 1271 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1272 unsigned long n) 1273 { 1274 int attempts = 5; 1275 1276 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1277 if (!--attempts) 1278 return (ETIMEDOUT); 1279 t3_os_sleep(10); 1280 } 1281 return 0; 1282 } 1283 1284 static int 1285 init_tp_parity(struct adapter *adap) 1286 { 1287 int i; 1288 struct mbuf *m; 1289 struct cpl_set_tcb_field *greq; 1290 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1291 1292 t3_tp_set_offload_mode(adap, 1); 1293 1294 for (i = 0; i < 16; i++) { 1295 struct cpl_smt_write_req *req; 1296 1297 m = m_gethdr(M_WAITOK, MT_DATA); 1298 req = mtod(m, struct cpl_smt_write_req *); 1299 m->m_len = m->m_pkthdr.len = sizeof(*req); 1300 memset(req, 0, sizeof(*req)); 1301 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1302 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1303 req->iff = i; 1304 t3_mgmt_tx(adap, m); 1305 } 1306 1307 for (i = 0; i < 2048; i++) { 1308 struct cpl_l2t_write_req *req; 1309 1310 m = m_gethdr(M_WAITOK, MT_DATA); 1311 req = mtod(m, struct cpl_l2t_write_req *); 1312 m->m_len = m->m_pkthdr.len = sizeof(*req); 1313 memset(req, 0, sizeof(*req)); 1314 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1315 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1316 req->params = htonl(V_L2T_W_IDX(i)); 1317 t3_mgmt_tx(adap, m); 1318 } 1319 1320 for (i = 0; i < 2048; i++) { 1321 struct cpl_rte_write_req *req; 1322 1323 m = m_gethdr(M_WAITOK, MT_DATA); 1324 req = mtod(m, struct cpl_rte_write_req *); 1325 m->m_len = m->m_pkthdr.len = sizeof(*req); 1326 memset(req, 0, sizeof(*req)); 1327 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1328 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1329 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1330 t3_mgmt_tx(adap, m); 1331 } 1332 1333 m = m_gethdr(M_WAITOK, MT_DATA); 1334 greq = mtod(m, struct cpl_set_tcb_field *); 1335 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1336 memset(greq, 0, sizeof(*greq)); 1337 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1338 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1339 greq->mask = htobe64(1); 1340 t3_mgmt_tx(adap, m); 1341 1342 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1343 t3_tp_set_offload_mode(adap, 0); 1344 return (i); 1345 } 1346 1347 /** 1348 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1349 * @adap: the adapter 1350 * 1351 * Sets up RSS to distribute packets to multiple receive queues. We 1352 * configure the RSS CPU lookup table to distribute to the number of HW 1353 * receive queues, and the response queue lookup table to narrow that 1354 * down to the response queues actually configured for each port. 1355 * We always configure the RSS mapping for two ports since the mapping 1356 * table has plenty of entries. 1357 */ 1358 static void 1359 setup_rss(adapter_t *adap) 1360 { 1361 int i; 1362 u_int nq[2]; 1363 uint8_t cpus[SGE_QSETS + 1]; 1364 uint16_t rspq_map[RSS_TABLE_SIZE]; 1365 1366 for (i = 0; i < SGE_QSETS; ++i) 1367 cpus[i] = i; 1368 cpus[SGE_QSETS] = 0xff; 1369 1370 nq[0] = nq[1] = 0; 1371 for_each_port(adap, i) { 1372 const struct port_info *pi = adap2pinfo(adap, i); 1373 1374 nq[pi->tx_chan] += pi->nqsets; 1375 } 1376 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1377 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1378 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1379 } 1380 /* Calculate the reverse RSS map table */ 1381 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1382 if (adap->rrss_map[rspq_map[i]] == 0xff) 1383 adap->rrss_map[rspq_map[i]] = i; 1384 1385 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1386 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1387 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1388 cpus, rspq_map); 1389 1390 } 1391 1392 /* 1393 * Sends an mbuf to an offload queue driver 1394 * after dealing with any active network taps. 1395 */ 1396 static inline int 1397 offload_tx(struct t3cdev *tdev, struct mbuf *m) 1398 { 1399 int ret; 1400 1401 ret = t3_offload_tx(tdev, m); 1402 return (ret); 1403 } 1404 1405 static int 1406 write_smt_entry(struct adapter *adapter, int idx) 1407 { 1408 struct port_info *pi = &adapter->port[idx]; 1409 struct cpl_smt_write_req *req; 1410 struct mbuf *m; 1411 1412 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1413 return (ENOMEM); 1414 1415 req = mtod(m, struct cpl_smt_write_req *); 1416 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1417 1418 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1419 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1420 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1421 req->iff = idx; 1422 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1423 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1424 1425 m_set_priority(m, 1); 1426 1427 offload_tx(&adapter->tdev, m); 1428 1429 return (0); 1430 } 1431 1432 static int 1433 init_smt(struct adapter *adapter) 1434 { 1435 int i; 1436 1437 for_each_port(adapter, i) 1438 write_smt_entry(adapter, i); 1439 return 0; 1440 } 1441 1442 static void 1443 init_port_mtus(adapter_t *adapter) 1444 { 1445 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1446 1447 if (adapter->port[1].ifp) 1448 mtus |= adapter->port[1].ifp->if_mtu << 16; 1449 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1450 } 1451 1452 static void 1453 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1454 int hi, int port) 1455 { 1456 struct mbuf *m; 1457 struct mngt_pktsched_wr *req; 1458 1459 m = m_gethdr(M_DONTWAIT, MT_DATA); 1460 if (m) { 1461 req = mtod(m, struct mngt_pktsched_wr *); 1462 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1463 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1464 req->sched = sched; 1465 req->idx = qidx; 1466 req->min = lo; 1467 req->max = hi; 1468 req->binding = port; 1469 m->m_len = m->m_pkthdr.len = sizeof(*req); 1470 t3_mgmt_tx(adap, m); 1471 } 1472 } 1473 1474 static void 1475 bind_qsets(adapter_t *sc) 1476 { 1477 int i, j; 1478 1479 cxgb_pcpu_startup_threads(sc); 1480 for (i = 0; i < (sc)->params.nports; ++i) { 1481 const struct port_info *pi = adap2pinfo(sc, i); 1482 1483 for (j = 0; j < pi->nqsets; ++j) { 1484 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1485 -1, pi->tx_chan); 1486 1487 } 1488 } 1489 } 1490 1491 static void 1492 update_tpeeprom(struct adapter *adap) 1493 { 1494 #ifdef FIRMWARE_LATEST 1495 const struct firmware *tpeeprom; 1496 #else 1497 struct firmware *tpeeprom; 1498 #endif 1499 1500 uint32_t version; 1501 unsigned int major, minor; 1502 int ret, len; 1503 char rev; 1504 1505 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1506 1507 major = G_TP_VERSION_MAJOR(version); 1508 minor = G_TP_VERSION_MINOR(version); 1509 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1510 return; 1511 1512 rev = t3rev2char(adap); 1513 1514 tpeeprom = firmware_get(TPEEPROM_NAME); 1515 if (tpeeprom == NULL) { 1516 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1517 TPEEPROM_NAME); 1518 return; 1519 } 1520 1521 len = tpeeprom->datasize - 4; 1522 1523 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1524 if (ret) 1525 goto release_tpeeprom; 1526 1527 if (len != TP_SRAM_LEN) { 1528 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", TPEEPROM_NAME, len, TP_SRAM_LEN); 1529 return; 1530 } 1531 1532 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1533 TP_SRAM_OFFSET); 1534 1535 if (!ret) { 1536 device_printf(adap->dev, 1537 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1538 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1539 } else 1540 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1541 1542 release_tpeeprom: 1543 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1544 1545 return; 1546 } 1547 1548 static int 1549 update_tpsram(struct adapter *adap) 1550 { 1551 #ifdef FIRMWARE_LATEST 1552 const struct firmware *tpsram; 1553 #else 1554 struct firmware *tpsram; 1555 #endif 1556 int ret; 1557 char rev; 1558 1559 rev = t3rev2char(adap); 1560 if (!rev) 1561 return 0; 1562 1563 update_tpeeprom(adap); 1564 1565 tpsram = firmware_get(TPSRAM_NAME); 1566 if (tpsram == NULL){ 1567 device_printf(adap->dev, "could not load TP SRAM\n"); 1568 return (EINVAL); 1569 } else 1570 device_printf(adap->dev, "updating TP SRAM\n"); 1571 1572 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1573 if (ret) 1574 goto release_tpsram; 1575 1576 ret = t3_set_proto_sram(adap, tpsram->data); 1577 if (ret) 1578 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1579 1580 release_tpsram: 1581 firmware_put(tpsram, FIRMWARE_UNLOAD); 1582 1583 return ret; 1584 } 1585 1586 /** 1587 * cxgb_up - enable the adapter 1588 * @adap: adapter being enabled 1589 * 1590 * Called when the first port is enabled, this function performs the 1591 * actions necessary to make an adapter operational, such as completing 1592 * the initialization of HW modules, and enabling interrupts. 1593 * 1594 */ 1595 static int 1596 cxgb_up(struct adapter *sc) 1597 { 1598 int err = 0; 1599 1600 if ((sc->flags & FULL_INIT_DONE) == 0) { 1601 1602 if ((sc->flags & FW_UPTODATE) == 0) 1603 if ((err = upgrade_fw(sc))) 1604 goto out; 1605 if ((sc->flags & TPS_UPTODATE) == 0) 1606 if ((err = update_tpsram(sc))) 1607 goto out; 1608 err = t3_init_hw(sc, 0); 1609 if (err) 1610 goto out; 1611 1612 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1613 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1614 1615 err = setup_sge_qsets(sc); 1616 if (err) 1617 goto out; 1618 1619 setup_rss(sc); 1620 t3_add_configured_sysctls(sc); 1621 sc->flags |= FULL_INIT_DONE; 1622 } 1623 1624 t3_intr_clear(sc); 1625 1626 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1627 if ((sc->flags & USING_MSIX) == 0) { 1628 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1629 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1630 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", 1631 sc->irq_rid); 1632 err = EINVAL; 1633 goto out; 1634 } 1635 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1636 1637 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1638 #ifdef INTR_FILTERS 1639 NULL, 1640 #endif 1641 sc->cxgb_intr, sc, &sc->intr_tag)) { 1642 device_printf(sc->dev, "Cannot set up interrupt\n"); 1643 err = EINVAL; 1644 goto irq_err; 1645 } 1646 } else { 1647 cxgb_setup_msix(sc, sc->msi_count); 1648 } 1649 1650 t3_sge_start(sc); 1651 t3_intr_enable(sc); 1652 1653 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1654 is_offload(sc) && init_tp_parity(sc) == 0) 1655 sc->flags |= TP_PARITY_INIT; 1656 1657 if (sc->flags & TP_PARITY_INIT) { 1658 t3_write_reg(sc, A_TP_INT_CAUSE, 1659 F_CMCACHEPERR | F_ARPLUTPERR); 1660 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1661 } 1662 1663 1664 if (!(sc->flags & QUEUES_BOUND)) { 1665 bind_qsets(sc); 1666 sc->flags |= QUEUES_BOUND; 1667 } 1668 out: 1669 return (err); 1670 irq_err: 1671 CH_ERR(sc, "request_irq failed, err %d\n", err); 1672 goto out; 1673 } 1674 1675 1676 /* 1677 * Release resources when all the ports and offloading have been stopped. 1678 */ 1679 static void 1680 cxgb_down_locked(struct adapter *sc) 1681 { 1682 1683 t3_sge_stop(sc); 1684 t3_intr_disable(sc); 1685 1686 if (sc->intr_tag != NULL) { 1687 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1688 sc->intr_tag = NULL; 1689 } 1690 if (sc->irq_res != NULL) { 1691 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1692 sc->irq_rid, sc->irq_res); 1693 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1694 sc->irq_res); 1695 sc->irq_res = NULL; 1696 } 1697 1698 if (sc->flags & USING_MSIX) 1699 cxgb_teardown_msix(sc); 1700 1701 callout_stop(&sc->cxgb_tick_ch); 1702 callout_stop(&sc->sge_timer_ch); 1703 callout_drain(&sc->cxgb_tick_ch); 1704 callout_drain(&sc->sge_timer_ch); 1705 1706 if (sc->tq != NULL) { 1707 printf("draining slow intr\n"); 1708 1709 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1710 printf("draining ext intr\n"); 1711 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1712 printf("draining tick task\n"); 1713 taskqueue_drain(sc->tq, &sc->tick_task); 1714 } 1715 ADAPTER_UNLOCK(sc); 1716 } 1717 1718 static int 1719 offload_open(struct port_info *pi) 1720 { 1721 struct adapter *adapter = pi->adapter; 1722 struct t3cdev *tdev = &adapter->tdev; 1723 1724 int adap_up = adapter->open_device_map & PORT_MASK; 1725 int err = 0; 1726 1727 if (atomic_cmpset_int(&adapter->open_device_map, 1728 (adapter->open_device_map & ~(1<<OFFLOAD_DEVMAP_BIT)), 1729 (adapter->open_device_map | (1<<OFFLOAD_DEVMAP_BIT))) == 0) 1730 return (0); 1731 1732 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1733 printf("offload_open: DEVMAP_BIT did not get set 0x%x\n", 1734 adapter->open_device_map); 1735 ADAPTER_LOCK(pi->adapter); 1736 if (!adap_up) 1737 err = cxgb_up(adapter); 1738 ADAPTER_UNLOCK(pi->adapter); 1739 if (err) 1740 return (err); 1741 1742 t3_tp_set_offload_mode(adapter, 1); 1743 tdev->lldev = pi->ifp; 1744 1745 init_port_mtus(adapter); 1746 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1747 adapter->params.b_wnd, 1748 adapter->params.rev == 0 ? 1749 adapter->port[0].ifp->if_mtu : 0xffff); 1750 init_smt(adapter); 1751 /* Call back all registered clients */ 1752 cxgb_add_clients(tdev); 1753 1754 /* restore them in case the offload module has changed them */ 1755 if (err) { 1756 t3_tp_set_offload_mode(adapter, 0); 1757 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1758 cxgb_set_dummy_ops(tdev); 1759 } 1760 return (err); 1761 } 1762 1763 static int 1764 offload_close(struct t3cdev *tdev) 1765 { 1766 struct adapter *adapter = tdev2adap(tdev); 1767 1768 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1769 return (0); 1770 1771 /* Call back all registered clients */ 1772 cxgb_remove_clients(tdev); 1773 1774 tdev->lldev = NULL; 1775 cxgb_set_dummy_ops(tdev); 1776 t3_tp_set_offload_mode(adapter, 0); 1777 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1778 1779 ADAPTER_LOCK(adapter); 1780 if (!adapter->open_device_map) 1781 cxgb_down_locked(adapter); 1782 else 1783 ADAPTER_UNLOCK(adapter); 1784 return (0); 1785 } 1786 1787 1788 static void 1789 cxgb_init(void *arg) 1790 { 1791 struct port_info *p = arg; 1792 1793 PORT_LOCK(p); 1794 cxgb_init_locked(p); 1795 PORT_UNLOCK(p); 1796 } 1797 1798 static void 1799 cxgb_init_locked(struct port_info *p) 1800 { 1801 struct ifnet *ifp; 1802 adapter_t *sc = p->adapter; 1803 int err; 1804 1805 PORT_LOCK_ASSERT_OWNED(p); 1806 ifp = p->ifp; 1807 1808 ADAPTER_LOCK(p->adapter); 1809 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1810 ADAPTER_UNLOCK(p->adapter); 1811 cxgb_stop_locked(p); 1812 return; 1813 } 1814 if (p->adapter->open_device_map == 0) { 1815 t3_intr_clear(sc); 1816 } 1817 setbit(&p->adapter->open_device_map, p->port_id); 1818 ADAPTER_UNLOCK(p->adapter); 1819 1820 if (is_offload(sc) && !ofld_disable) { 1821 err = offload_open(p); 1822 if (err) 1823 log(LOG_WARNING, 1824 "Could not initialize offload capabilities\n"); 1825 } 1826 #if !defined(LINK_ATTACH) 1827 cxgb_link_start(p); 1828 t3_link_changed(sc, p->port_id); 1829 #endif 1830 ifp->if_baudrate = p->link_config.speed * 1000000; 1831 1832 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1833 t3_port_intr_enable(sc, p->port_id); 1834 1835 t3_sge_reset_adapter(sc); 1836 1837 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1838 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1839 } 1840 1841 static void 1842 cxgb_set_rxmode(struct port_info *p) 1843 { 1844 struct t3_rx_mode rm; 1845 struct cmac *mac = &p->mac; 1846 1847 t3_init_rx_mode(&rm, p); 1848 mtx_lock(&p->adapter->mdio_lock); 1849 t3_mac_set_rx_mode(mac, &rm); 1850 mtx_unlock(&p->adapter->mdio_lock); 1851 } 1852 1853 static void 1854 cxgb_stop_locked(struct port_info *pi) 1855 { 1856 struct ifnet *ifp; 1857 1858 PORT_LOCK_ASSERT_OWNED(pi); 1859 ADAPTER_LOCK_ASSERT_NOTOWNED(pi->adapter); 1860 1861 ifp = pi->ifp; 1862 t3_port_intr_disable(pi->adapter, pi->port_id); 1863 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1864 1865 /* disable pause frames */ 1866 t3_set_reg_field(pi->adapter, A_XGM_TX_CFG + pi->mac.offset, 1867 F_TXPAUSEEN, 0); 1868 1869 /* Reset RX FIFO HWM */ 1870 t3_set_reg_field(pi->adapter, A_XGM_RXFIFO_CFG + pi->mac.offset, 1871 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1872 1873 1874 ADAPTER_LOCK(pi->adapter); 1875 clrbit(&pi->adapter->open_device_map, pi->port_id); 1876 1877 if (pi->adapter->open_device_map == 0) { 1878 cxgb_down_locked(pi->adapter); 1879 } else 1880 ADAPTER_UNLOCK(pi->adapter); 1881 1882 #if !defined(LINK_ATTACH) 1883 DELAY(100); 1884 1885 /* Wait for TXFIFO empty */ 1886 t3_wait_op_done(pi->adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 1887 F_TXFIFO_EMPTY, 1, 20, 5); 1888 1889 DELAY(100); 1890 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1891 1892 pi->phy.ops->power_down(&pi->phy, 1); 1893 #endif 1894 1895 } 1896 1897 static int 1898 cxgb_set_mtu(struct port_info *p, int mtu) 1899 { 1900 struct ifnet *ifp = p->ifp; 1901 int error = 0; 1902 1903 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1904 error = EINVAL; 1905 else if (ifp->if_mtu != mtu) { 1906 PORT_LOCK(p); 1907 ifp->if_mtu = mtu; 1908 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1909 cxgb_stop_locked(p); 1910 cxgb_init_locked(p); 1911 } 1912 PORT_UNLOCK(p); 1913 } 1914 return (error); 1915 } 1916 1917 #ifdef LRO_SUPPORTED 1918 /* 1919 * Mark lro enabled or disabled in all qsets for this port 1920 */ 1921 static int 1922 cxgb_set_lro(struct port_info *p, int enabled) 1923 { 1924 int i; 1925 struct adapter *adp = p->adapter; 1926 struct sge_qset *q; 1927 1928 PORT_LOCK_ASSERT_OWNED(p); 1929 for (i = 0; i < p->nqsets; i++) { 1930 q = &adp->sge.qs[p->first_qset + i]; 1931 q->lro.enabled = (enabled != 0); 1932 } 1933 return (0); 1934 } 1935 #endif 1936 1937 static int 1938 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1939 { 1940 struct port_info *p = ifp->if_softc; 1941 #ifdef INET 1942 struct ifaddr *ifa = (struct ifaddr *)data; 1943 #endif 1944 struct ifreq *ifr = (struct ifreq *)data; 1945 int flags, error = 0, reinit = 0; 1946 uint32_t mask; 1947 1948 /* 1949 * XXX need to check that we aren't in the middle of an unload 1950 */ 1951 switch (command) { 1952 case SIOCSIFMTU: 1953 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1954 break; 1955 case SIOCSIFADDR: 1956 #ifdef INET 1957 if (ifa->ifa_addr->sa_family == AF_INET) { 1958 ifp->if_flags |= IFF_UP; 1959 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1960 PORT_LOCK(p); 1961 cxgb_init_locked(p); 1962 PORT_UNLOCK(p); 1963 } 1964 arp_ifinit(ifp, ifa); 1965 } else 1966 #endif 1967 error = ether_ioctl(ifp, command, data); 1968 break; 1969 case SIOCSIFFLAGS: 1970 PORT_LOCK(p); 1971 if (ifp->if_flags & IFF_UP) { 1972 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1973 flags = p->if_flags; 1974 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1975 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1976 cxgb_set_rxmode(p); 1977 } else 1978 cxgb_init_locked(p); 1979 p->if_flags = ifp->if_flags; 1980 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1981 cxgb_stop_locked(p); 1982 1983 PORT_UNLOCK(p); 1984 break; 1985 case SIOCADDMULTI: 1986 case SIOCDELMULTI: 1987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1988 cxgb_set_rxmode(p); 1989 } 1990 break; 1991 case SIOCSIFMEDIA: 1992 case SIOCGIFMEDIA: 1993 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1994 break; 1995 case SIOCSIFCAP: 1996 PORT_LOCK(p); 1997 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1998 if (mask & IFCAP_TXCSUM) { 1999 if (IFCAP_TXCSUM & ifp->if_capenable) { 2000 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 2001 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 2002 | CSUM_IP | CSUM_TSO); 2003 } else { 2004 ifp->if_capenable |= IFCAP_TXCSUM; 2005 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP 2006 | CSUM_IP); 2007 } 2008 } 2009 if (mask & IFCAP_RXCSUM) { 2010 ifp->if_capenable ^= IFCAP_RXCSUM; 2011 } 2012 if (mask & IFCAP_TSO4) { 2013 if (IFCAP_TSO4 & ifp->if_capenable) { 2014 ifp->if_capenable &= ~IFCAP_TSO4; 2015 ifp->if_hwassist &= ~CSUM_TSO; 2016 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 2017 ifp->if_capenable |= IFCAP_TSO4; 2018 ifp->if_hwassist |= CSUM_TSO; 2019 } else { 2020 if (cxgb_debug) 2021 printf("cxgb requires tx checksum offload" 2022 " be enabled to use TSO\n"); 2023 error = EINVAL; 2024 } 2025 } 2026 #ifdef LRO_SUPPORTED 2027 if (mask & IFCAP_LRO) { 2028 ifp->if_capenable ^= IFCAP_LRO; 2029 2030 /* Safe to do this even if cxgb_up not called yet */ 2031 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); 2032 } 2033 #endif 2034 if (mask & IFCAP_VLAN_HWTAGGING) { 2035 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2036 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2037 } 2038 if (mask & IFCAP_VLAN_MTU) { 2039 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2040 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2041 } 2042 if (mask & IFCAP_VLAN_HWCSUM) { 2043 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2044 } 2045 if (reinit) { 2046 cxgb_stop_locked(p); 2047 cxgb_init_locked(p); 2048 } 2049 PORT_UNLOCK(p); 2050 2051 #ifdef VLAN_CAPABILITIES 2052 VLAN_CAPABILITIES(ifp); 2053 #endif 2054 break; 2055 default: 2056 error = ether_ioctl(ifp, command, data); 2057 break; 2058 } 2059 return (error); 2060 } 2061 2062 static int 2063 cxgb_media_change(struct ifnet *ifp) 2064 { 2065 if_printf(ifp, "media change not supported\n"); 2066 return (ENXIO); 2067 } 2068 2069 static void 2070 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2071 { 2072 struct port_info *p = ifp->if_softc; 2073 2074 ifmr->ifm_status = IFM_AVALID; 2075 ifmr->ifm_active = IFM_ETHER; 2076 2077 if (!p->link_config.link_ok) 2078 return; 2079 2080 ifmr->ifm_status |= IFM_ACTIVE; 2081 2082 switch (p->link_config.speed) { 2083 case 10: 2084 ifmr->ifm_active |= IFM_10_T; 2085 break; 2086 case 100: 2087 ifmr->ifm_active |= IFM_100_TX; 2088 break; 2089 case 1000: 2090 ifmr->ifm_active |= IFM_1000_T; 2091 break; 2092 } 2093 2094 if (p->link_config.duplex) 2095 ifmr->ifm_active |= IFM_FDX; 2096 else 2097 ifmr->ifm_active |= IFM_HDX; 2098 } 2099 2100 static void 2101 cxgb_async_intr(void *data) 2102 { 2103 adapter_t *sc = data; 2104 2105 if (cxgb_debug) 2106 device_printf(sc->dev, "cxgb_async_intr\n"); 2107 /* 2108 * May need to sleep - defer to taskqueue 2109 */ 2110 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2111 } 2112 2113 static void 2114 cxgb_ext_intr_handler(void *arg, int count) 2115 { 2116 adapter_t *sc = (adapter_t *)arg; 2117 2118 if (cxgb_debug) 2119 printf("cxgb_ext_intr_handler\n"); 2120 2121 t3_phy_intr_handler(sc); 2122 2123 /* Now reenable external interrupts */ 2124 ADAPTER_LOCK(sc); 2125 if (sc->slow_intr_mask) { 2126 sc->slow_intr_mask |= F_T3DBG; 2127 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2128 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2129 } 2130 ADAPTER_UNLOCK(sc); 2131 } 2132 2133 static void 2134 check_link_status(adapter_t *sc) 2135 { 2136 int i; 2137 2138 for (i = 0; i < (sc)->params.nports; ++i) { 2139 struct port_info *p = &sc->port[i]; 2140 2141 if (!(p->phy.caps & SUPPORTED_IRQ)) 2142 t3_link_changed(sc, i); 2143 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2144 } 2145 } 2146 2147 static void 2148 check_t3b2_mac(struct adapter *adapter) 2149 { 2150 int i; 2151 2152 if(adapter->flags & CXGB_SHUTDOWN) 2153 return; 2154 2155 for_each_port(adapter, i) { 2156 struct port_info *p = &adapter->port[i]; 2157 struct ifnet *ifp = p->ifp; 2158 int status; 2159 2160 if(adapter->flags & CXGB_SHUTDOWN) 2161 return; 2162 2163 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2164 continue; 2165 2166 status = 0; 2167 PORT_LOCK(p); 2168 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2169 status = t3b2_mac_watchdog_task(&p->mac); 2170 if (status == 1) 2171 p->mac.stats.num_toggled++; 2172 else if (status == 2) { 2173 struct cmac *mac = &p->mac; 2174 int mtu = ifp->if_mtu; 2175 2176 if (ifp->if_capenable & IFCAP_VLAN_MTU) 2177 mtu += ETHER_VLAN_ENCAP_LEN; 2178 t3_mac_set_mtu(mac, mtu); 2179 t3_mac_set_address(mac, 0, p->hw_addr); 2180 cxgb_set_rxmode(p); 2181 t3_link_start(&p->phy, mac, &p->link_config); 2182 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2183 t3_port_intr_enable(adapter, p->port_id); 2184 p->mac.stats.num_resets++; 2185 } 2186 PORT_UNLOCK(p); 2187 } 2188 } 2189 2190 static void 2191 cxgb_tick(void *arg) 2192 { 2193 adapter_t *sc = (adapter_t *)arg; 2194 2195 if(sc->flags & CXGB_SHUTDOWN) 2196 return; 2197 2198 taskqueue_enqueue(sc->tq, &sc->tick_task); 2199 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 2200 } 2201 2202 static void 2203 cxgb_tick_handler(void *arg, int count) 2204 { 2205 adapter_t *sc = (adapter_t *)arg; 2206 const struct adapter_params *p = &sc->params; 2207 int i; 2208 2209 if(sc->flags & CXGB_SHUTDOWN) 2210 return; 2211 2212 ADAPTER_LOCK(sc); 2213 if (p->linkpoll_period) 2214 check_link_status(sc); 2215 2216 2217 sc->check_task_cnt++; 2218 2219 /* 2220 * adapter lock can currently only be acquired after the 2221 * port lock 2222 */ 2223 ADAPTER_UNLOCK(sc); 2224 2225 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2226 check_t3b2_mac(sc); 2227 2228 for (i = 0; i < sc->params.nports; i++) { 2229 struct port_info *pi = &sc->port[i]; 2230 struct ifnet *ifp = pi->ifp; 2231 struct mac_stats *mstats = &pi->mac.stats; 2232 PORT_LOCK(pi); 2233 t3_mac_update_stats(&pi->mac); 2234 PORT_UNLOCK(pi); 2235 2236 2237 ifp->if_opackets = 2238 mstats->tx_frames_64 + 2239 mstats->tx_frames_65_127 + 2240 mstats->tx_frames_128_255 + 2241 mstats->tx_frames_256_511 + 2242 mstats->tx_frames_512_1023 + 2243 mstats->tx_frames_1024_1518 + 2244 mstats->tx_frames_1519_max; 2245 2246 ifp->if_ipackets = 2247 mstats->rx_frames_64 + 2248 mstats->rx_frames_65_127 + 2249 mstats->rx_frames_128_255 + 2250 mstats->rx_frames_256_511 + 2251 mstats->rx_frames_512_1023 + 2252 mstats->rx_frames_1024_1518 + 2253 mstats->rx_frames_1519_max; 2254 2255 ifp->if_obytes = mstats->tx_octets; 2256 ifp->if_ibytes = mstats->rx_octets; 2257 ifp->if_omcasts = mstats->tx_mcast_frames; 2258 ifp->if_imcasts = mstats->rx_mcast_frames; 2259 2260 ifp->if_collisions = 2261 mstats->tx_total_collisions; 2262 2263 ifp->if_iqdrops = mstats->rx_cong_drops; 2264 2265 ifp->if_oerrors = 2266 mstats->tx_excess_collisions + 2267 mstats->tx_underrun + 2268 mstats->tx_len_errs + 2269 mstats->tx_mac_internal_errs + 2270 mstats->tx_excess_deferral + 2271 mstats->tx_fcs_errs; 2272 ifp->if_ierrors = 2273 mstats->rx_jabber + 2274 mstats->rx_data_errs + 2275 mstats->rx_sequence_errs + 2276 mstats->rx_runt + 2277 mstats->rx_too_long + 2278 mstats->rx_mac_internal_errs + 2279 mstats->rx_short + 2280 mstats->rx_fcs_errs; 2281 } 2282 } 2283 2284 static void 2285 touch_bars(device_t dev) 2286 { 2287 /* 2288 * Don't enable yet 2289 */ 2290 #if !defined(__LP64__) && 0 2291 u32 v; 2292 2293 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2294 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2295 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2296 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2297 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2298 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2299 #endif 2300 } 2301 2302 static int 2303 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2304 { 2305 uint8_t *buf; 2306 int err = 0; 2307 u32 aligned_offset, aligned_len, *p; 2308 struct adapter *adapter = pi->adapter; 2309 2310 2311 aligned_offset = offset & ~3; 2312 aligned_len = (len + (offset & 3) + 3) & ~3; 2313 2314 if (aligned_offset != offset || aligned_len != len) { 2315 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2316 if (!buf) 2317 return (ENOMEM); 2318 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2319 if (!err && aligned_len > 4) 2320 err = t3_seeprom_read(adapter, 2321 aligned_offset + aligned_len - 4, 2322 (u32 *)&buf[aligned_len - 4]); 2323 if (err) 2324 goto out; 2325 memcpy(buf + (offset & 3), data, len); 2326 } else 2327 buf = (uint8_t *)(uintptr_t)data; 2328 2329 err = t3_seeprom_wp(adapter, 0); 2330 if (err) 2331 goto out; 2332 2333 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2334 err = t3_seeprom_write(adapter, aligned_offset, *p); 2335 aligned_offset += 4; 2336 } 2337 2338 if (!err) 2339 err = t3_seeprom_wp(adapter, 1); 2340 out: 2341 if (buf != data) 2342 free(buf, M_DEVBUF); 2343 return err; 2344 } 2345 2346 2347 static int 2348 in_range(int val, int lo, int hi) 2349 { 2350 return val < 0 || (val <= hi && val >= lo); 2351 } 2352 2353 static int 2354 cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2355 { 2356 return (0); 2357 } 2358 2359 static int 2360 cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2361 { 2362 return (0); 2363 } 2364 2365 static int 2366 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2367 int fflag, struct thread *td) 2368 { 2369 int mmd, error = 0; 2370 struct port_info *pi = dev->si_drv1; 2371 adapter_t *sc = pi->adapter; 2372 2373 #ifdef PRIV_SUPPORTED 2374 if (priv_check(td, PRIV_DRIVER)) { 2375 if (cxgb_debug) 2376 printf("user does not have access to privileged ioctls\n"); 2377 return (EPERM); 2378 } 2379 #else 2380 if (suser(td)) { 2381 if (cxgb_debug) 2382 printf("user does not have access to privileged ioctls\n"); 2383 return (EPERM); 2384 } 2385 #endif 2386 2387 switch (cmd) { 2388 case CHELSIO_GET_MIIREG: { 2389 uint32_t val; 2390 struct cphy *phy = &pi->phy; 2391 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2392 2393 if (!phy->mdio_read) 2394 return (EOPNOTSUPP); 2395 if (is_10G(sc)) { 2396 mmd = mid->phy_id >> 8; 2397 if (!mmd) 2398 mmd = MDIO_DEV_PCS; 2399 else if (mmd > MDIO_DEV_XGXS) 2400 return (EINVAL); 2401 2402 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2403 mid->reg_num, &val); 2404 } else 2405 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2406 mid->reg_num & 0x1f, &val); 2407 if (error == 0) 2408 mid->val_out = val; 2409 break; 2410 } 2411 case CHELSIO_SET_MIIREG: { 2412 struct cphy *phy = &pi->phy; 2413 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2414 2415 if (!phy->mdio_write) 2416 return (EOPNOTSUPP); 2417 if (is_10G(sc)) { 2418 mmd = mid->phy_id >> 8; 2419 if (!mmd) 2420 mmd = MDIO_DEV_PCS; 2421 else if (mmd > MDIO_DEV_XGXS) 2422 return (EINVAL); 2423 2424 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2425 mmd, mid->reg_num, mid->val_in); 2426 } else 2427 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2428 mid->reg_num & 0x1f, 2429 mid->val_in); 2430 break; 2431 } 2432 case CHELSIO_SETREG: { 2433 struct ch_reg *edata = (struct ch_reg *)data; 2434 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2435 return (EFAULT); 2436 t3_write_reg(sc, edata->addr, edata->val); 2437 break; 2438 } 2439 case CHELSIO_GETREG: { 2440 struct ch_reg *edata = (struct ch_reg *)data; 2441 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2442 return (EFAULT); 2443 edata->val = t3_read_reg(sc, edata->addr); 2444 break; 2445 } 2446 case CHELSIO_GET_SGE_CONTEXT: { 2447 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2448 mtx_lock_spin(&sc->sge.reg_lock); 2449 switch (ecntxt->cntxt_type) { 2450 case CNTXT_TYPE_EGRESS: 2451 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2452 ecntxt->data); 2453 break; 2454 case CNTXT_TYPE_FL: 2455 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, 2456 ecntxt->data); 2457 break; 2458 case CNTXT_TYPE_RSP: 2459 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2460 ecntxt->data); 2461 break; 2462 case CNTXT_TYPE_CQ: 2463 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, 2464 ecntxt->data); 2465 break; 2466 default: 2467 error = EINVAL; 2468 break; 2469 } 2470 mtx_unlock_spin(&sc->sge.reg_lock); 2471 break; 2472 } 2473 case CHELSIO_GET_SGE_DESC: { 2474 struct ch_desc *edesc = (struct ch_desc *)data; 2475 int ret; 2476 if (edesc->queue_num >= SGE_QSETS * 6) 2477 return (EINVAL); 2478 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2479 edesc->queue_num % 6, edesc->idx, edesc->data); 2480 if (ret < 0) 2481 return (EINVAL); 2482 edesc->size = ret; 2483 break; 2484 } 2485 case CHELSIO_GET_QSET_PARAMS: { 2486 struct qset_params *q; 2487 struct ch_qset_params *t = (struct ch_qset_params *)data; 2488 int q1 = pi->first_qset; 2489 int nqsets = pi->nqsets; 2490 int i; 2491 2492 if (t->qset_idx >= nqsets) 2493 return EINVAL; 2494 2495 i = q1 + t->qset_idx; 2496 q = &sc->params.sge.qset[i]; 2497 t->rspq_size = q->rspq_size; 2498 t->txq_size[0] = q->txq_size[0]; 2499 t->txq_size[1] = q->txq_size[1]; 2500 t->txq_size[2] = q->txq_size[2]; 2501 t->fl_size[0] = q->fl_size; 2502 t->fl_size[1] = q->jumbo_size; 2503 t->polling = q->polling; 2504 t->lro = q->lro; 2505 t->intr_lat = q->coalesce_usecs; 2506 t->cong_thres = q->cong_thres; 2507 t->qnum = i; 2508 2509 if (sc->flags & USING_MSIX) 2510 t->vector = rman_get_start(sc->msix_irq_res[i]); 2511 else 2512 t->vector = rman_get_start(sc->irq_res); 2513 2514 break; 2515 } 2516 case CHELSIO_GET_QSET_NUM: { 2517 struct ch_reg *edata = (struct ch_reg *)data; 2518 edata->val = pi->nqsets; 2519 break; 2520 } 2521 case CHELSIO_LOAD_FW: { 2522 uint8_t *fw_data; 2523 uint32_t vers; 2524 struct ch_mem_range *t = (struct ch_mem_range *)data; 2525 2526 /* 2527 * You're allowed to load a firmware only before FULL_INIT_DONE 2528 * 2529 * FW_UPTODATE is also set so the rest of the initialization 2530 * will not overwrite what was loaded here. This gives you the 2531 * flexibility to load any firmware (and maybe shoot yourself in 2532 * the foot). 2533 */ 2534 2535 ADAPTER_LOCK(sc); 2536 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { 2537 ADAPTER_UNLOCK(sc); 2538 return (EBUSY); 2539 } 2540 2541 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2542 if (!fw_data) 2543 error = ENOMEM; 2544 else 2545 error = copyin(t->buf, fw_data, t->len); 2546 2547 if (!error) 2548 error = -t3_load_fw(sc, fw_data, t->len); 2549 2550 if (t3_get_fw_version(sc, &vers) == 0) { 2551 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), 2552 "%d.%d.%d", G_FW_VERSION_MAJOR(vers), 2553 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); 2554 } 2555 2556 if (!error) 2557 sc->flags |= FW_UPTODATE; 2558 2559 free(fw_data, M_DEVBUF); 2560 ADAPTER_UNLOCK(sc); 2561 break; 2562 } 2563 case CHELSIO_LOAD_BOOT: { 2564 uint8_t *boot_data; 2565 struct ch_mem_range *t = (struct ch_mem_range *)data; 2566 2567 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2568 if (!boot_data) 2569 return ENOMEM; 2570 2571 error = copyin(t->buf, boot_data, t->len); 2572 if (!error) 2573 error = -t3_load_boot(sc, boot_data, t->len); 2574 2575 free(boot_data, M_DEVBUF); 2576 break; 2577 } 2578 case CHELSIO_GET_PM: { 2579 struct ch_pm *m = (struct ch_pm *)data; 2580 struct tp_params *p = &sc->params.tp; 2581 2582 if (!is_offload(sc)) 2583 return (EOPNOTSUPP); 2584 2585 m->tx_pg_sz = p->tx_pg_size; 2586 m->tx_num_pg = p->tx_num_pgs; 2587 m->rx_pg_sz = p->rx_pg_size; 2588 m->rx_num_pg = p->rx_num_pgs; 2589 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2590 2591 break; 2592 } 2593 case CHELSIO_SET_PM: { 2594 struct ch_pm *m = (struct ch_pm *)data; 2595 struct tp_params *p = &sc->params.tp; 2596 2597 if (!is_offload(sc)) 2598 return (EOPNOTSUPP); 2599 if (sc->flags & FULL_INIT_DONE) 2600 return (EBUSY); 2601 2602 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || 2603 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) 2604 return (EINVAL); /* not power of 2 */ 2605 if (!(m->rx_pg_sz & 0x14000)) 2606 return (EINVAL); /* not 16KB or 64KB */ 2607 if (!(m->tx_pg_sz & 0x1554000)) 2608 return (EINVAL); 2609 if (m->tx_num_pg == -1) 2610 m->tx_num_pg = p->tx_num_pgs; 2611 if (m->rx_num_pg == -1) 2612 m->rx_num_pg = p->rx_num_pgs; 2613 if (m->tx_num_pg % 24 || m->rx_num_pg % 24) 2614 return (EINVAL); 2615 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || 2616 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) 2617 return (EINVAL); 2618 2619 p->rx_pg_size = m->rx_pg_sz; 2620 p->tx_pg_size = m->tx_pg_sz; 2621 p->rx_num_pgs = m->rx_num_pg; 2622 p->tx_num_pgs = m->tx_num_pg; 2623 break; 2624 } 2625 case CHELSIO_SETMTUTAB: { 2626 struct ch_mtus *m = (struct ch_mtus *)data; 2627 int i; 2628 2629 if (!is_offload(sc)) 2630 return (EOPNOTSUPP); 2631 if (offload_running(sc)) 2632 return (EBUSY); 2633 if (m->nmtus != NMTUS) 2634 return (EINVAL); 2635 if (m->mtus[0] < 81) /* accommodate SACK */ 2636 return (EINVAL); 2637 2638 /* 2639 * MTUs must be in ascending order 2640 */ 2641 for (i = 1; i < NMTUS; ++i) 2642 if (m->mtus[i] < m->mtus[i - 1]) 2643 return (EINVAL); 2644 2645 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); 2646 break; 2647 } 2648 case CHELSIO_GETMTUTAB: { 2649 struct ch_mtus *m = (struct ch_mtus *)data; 2650 2651 if (!is_offload(sc)) 2652 return (EOPNOTSUPP); 2653 2654 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2655 m->nmtus = NMTUS; 2656 break; 2657 } 2658 case CHELSIO_GET_MEM: { 2659 struct ch_mem_range *t = (struct ch_mem_range *)data; 2660 struct mc7 *mem; 2661 uint8_t *useraddr; 2662 u64 buf[32]; 2663 2664 /* 2665 * Use these to avoid modifying len/addr in the the return 2666 * struct 2667 */ 2668 uint32_t len = t->len, addr = t->addr; 2669 2670 if (!is_offload(sc)) 2671 return (EOPNOTSUPP); 2672 if (!(sc->flags & FULL_INIT_DONE)) 2673 return (EIO); /* need the memory controllers */ 2674 if ((addr & 0x7) || (len & 0x7)) 2675 return (EINVAL); 2676 if (t->mem_id == MEM_CM) 2677 mem = &sc->cm; 2678 else if (t->mem_id == MEM_PMRX) 2679 mem = &sc->pmrx; 2680 else if (t->mem_id == MEM_PMTX) 2681 mem = &sc->pmtx; 2682 else 2683 return (EINVAL); 2684 2685 /* 2686 * Version scheme: 2687 * bits 0..9: chip version 2688 * bits 10..15: chip revision 2689 */ 2690 t->version = 3 | (sc->params.rev << 10); 2691 2692 /* 2693 * Read 256 bytes at a time as len can be large and we don't 2694 * want to use huge intermediate buffers. 2695 */ 2696 useraddr = (uint8_t *)t->buf; 2697 while (len) { 2698 unsigned int chunk = min(len, sizeof(buf)); 2699 2700 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); 2701 if (error) 2702 return (-error); 2703 if (copyout(buf, useraddr, chunk)) 2704 return (EFAULT); 2705 useraddr += chunk; 2706 addr += chunk; 2707 len -= chunk; 2708 } 2709 break; 2710 } 2711 case CHELSIO_READ_TCAM_WORD: { 2712 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2713 2714 if (!is_offload(sc)) 2715 return (EOPNOTSUPP); 2716 if (!(sc->flags & FULL_INIT_DONE)) 2717 return (EIO); /* need MC5 */ 2718 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2719 break; 2720 } 2721 case CHELSIO_SET_TRACE_FILTER: { 2722 struct ch_trace *t = (struct ch_trace *)data; 2723 const struct trace_params *tp; 2724 2725 tp = (const struct trace_params *)&t->sip; 2726 if (t->config_tx) 2727 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2728 t->trace_tx); 2729 if (t->config_rx) 2730 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2731 t->trace_rx); 2732 break; 2733 } 2734 case CHELSIO_SET_PKTSCHED: { 2735 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2736 if (sc->open_device_map == 0) 2737 return (EAGAIN); 2738 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2739 p->binding); 2740 break; 2741 } 2742 case CHELSIO_IFCONF_GETREGS: { 2743 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; 2744 int reglen = cxgb_get_regs_len(); 2745 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); 2746 if (buf == NULL) { 2747 return (ENOMEM); 2748 } 2749 if (regs->len > reglen) 2750 regs->len = reglen; 2751 else if (regs->len < reglen) 2752 error = E2BIG; 2753 2754 if (!error) { 2755 cxgb_get_regs(sc, regs, buf); 2756 error = copyout(buf, regs->data, reglen); 2757 } 2758 free(buf, M_DEVBUF); 2759 2760 break; 2761 } 2762 case CHELSIO_SET_HW_SCHED: { 2763 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2764 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2765 2766 if ((sc->flags & FULL_INIT_DONE) == 0) 2767 return (EAGAIN); /* need TP to be initialized */ 2768 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2769 !in_range(t->channel, 0, 1) || 2770 !in_range(t->kbps, 0, 10000000) || 2771 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2772 !in_range(t->flow_ipg, 0, 2773 dack_ticks_to_usec(sc, 0x7ff))) 2774 return (EINVAL); 2775 2776 if (t->kbps >= 0) { 2777 error = t3_config_sched(sc, t->kbps, t->sched); 2778 if (error < 0) 2779 return (-error); 2780 } 2781 if (t->class_ipg >= 0) 2782 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2783 if (t->flow_ipg >= 0) { 2784 t->flow_ipg *= 1000; /* us -> ns */ 2785 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2786 } 2787 if (t->mode >= 0) { 2788 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2789 2790 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2791 bit, t->mode ? bit : 0); 2792 } 2793 if (t->channel >= 0) 2794 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2795 1 << t->sched, t->channel << t->sched); 2796 break; 2797 } 2798 case CHELSIO_GET_EEPROM: { 2799 int i; 2800 struct ch_eeprom *e = (struct ch_eeprom *)data; 2801 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); 2802 2803 if (buf == NULL) { 2804 return (ENOMEM); 2805 } 2806 e->magic = EEPROM_MAGIC; 2807 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) 2808 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); 2809 2810 if (!error) 2811 error = copyout(buf + e->offset, e->data, e->len); 2812 2813 free(buf, M_DEVBUF); 2814 break; 2815 } 2816 case CHELSIO_CLEAR_STATS: { 2817 if (!(sc->flags & FULL_INIT_DONE)) 2818 return EAGAIN; 2819 2820 PORT_LOCK(pi); 2821 t3_mac_update_stats(&pi->mac); 2822 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); 2823 PORT_UNLOCK(pi); 2824 break; 2825 } 2826 default: 2827 return (EOPNOTSUPP); 2828 break; 2829 } 2830 2831 return (error); 2832 } 2833 2834 static __inline void 2835 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2836 unsigned int end) 2837 { 2838 uint32_t *p = (uint32_t *)(buf + start); 2839 2840 for ( ; start <= end; start += sizeof(uint32_t)) 2841 *p++ = t3_read_reg(ap, start); 2842 } 2843 2844 #define T3_REGMAP_SIZE (3 * 1024) 2845 static int 2846 cxgb_get_regs_len(void) 2847 { 2848 return T3_REGMAP_SIZE; 2849 } 2850 2851 static void 2852 cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) 2853 { 2854 2855 /* 2856 * Version scheme: 2857 * bits 0..9: chip version 2858 * bits 10..15: chip revision 2859 * bit 31: set for PCIe cards 2860 */ 2861 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2862 2863 /* 2864 * We skip the MAC statistics registers because they are clear-on-read. 2865 * Also reading multi-register stats would need to synchronize with the 2866 * periodic mac stats accumulation. Hard to justify the complexity. 2867 */ 2868 memset(buf, 0, cxgb_get_regs_len()); 2869 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2870 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2871 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2872 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2873 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2874 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2875 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2876 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2877 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2878 } 2879 2880 2881 MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 2882