1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/pciio.h> 39 #include <sys/conf.h> 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/bus_dma.h> 43 #include <sys/ktr.h> 44 #include <sys/rman.h> 45 #include <sys/ioccom.h> 46 #include <sys/mbuf.h> 47 #include <sys/linker.h> 48 #include <sys/firmware.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/smp.h> 52 #include <sys/sysctl.h> 53 #include <sys/syslog.h> 54 #include <sys/queue.h> 55 #include <sys/taskqueue.h> 56 #include <sys/proc.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 66 #include <netinet/in_systm.h> 67 #include <netinet/in.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pci_private.h> 77 78 #ifdef CONFIG_DEFINED 79 #include <cxgb_include.h> 80 #else 81 #include <dev/cxgb/cxgb_include.h> 82 #endif 83 84 #ifdef PRIV_SUPPORTED 85 #include <sys/priv.h> 86 #endif 87 88 #ifdef IFNET_MULTIQUEUE 89 #include <machine/intr_machdep.h> 90 #endif 91 92 static int cxgb_setup_msix(adapter_t *, int); 93 static void cxgb_teardown_msix(adapter_t *); 94 static void cxgb_init(void *); 95 static void cxgb_init_locked(struct port_info *); 96 static void cxgb_stop_locked(struct port_info *); 97 static void cxgb_set_rxmode(struct port_info *); 98 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 99 static int cxgb_media_change(struct ifnet *); 100 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 101 static int setup_sge_qsets(adapter_t *); 102 static void cxgb_async_intr(void *); 103 static void cxgb_ext_intr_handler(void *, int); 104 static void cxgb_tick_handler(void *, int); 105 static void cxgb_down_locked(struct adapter *sc); 106 static void cxgb_tick(void *); 107 static void setup_rss(adapter_t *sc); 108 109 /* Attachment glue for the PCI controller end of the device. Each port of 110 * the device is attached separately, as defined later. 111 */ 112 static int cxgb_controller_probe(device_t); 113 static int cxgb_controller_attach(device_t); 114 static int cxgb_controller_detach(device_t); 115 static void cxgb_free(struct adapter *); 116 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 117 unsigned int end); 118 static void cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf); 119 static int cxgb_get_regs_len(void); 120 static int offload_open(struct port_info *pi); 121 static void touch_bars(device_t dev); 122 static int offload_close(struct t3cdev *tdev); 123 static void cxgb_link_start(struct port_info *p); 124 125 static device_method_t cxgb_controller_methods[] = { 126 DEVMETHOD(device_probe, cxgb_controller_probe), 127 DEVMETHOD(device_attach, cxgb_controller_attach), 128 DEVMETHOD(device_detach, cxgb_controller_detach), 129 130 /* bus interface */ 131 DEVMETHOD(bus_print_child, bus_generic_print_child), 132 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 133 134 { 0, 0 } 135 }; 136 137 static driver_t cxgb_controller_driver = { 138 "cxgbc", 139 cxgb_controller_methods, 140 sizeof(struct adapter) 141 }; 142 143 static devclass_t cxgb_controller_devclass; 144 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 145 146 /* 147 * Attachment glue for the ports. Attachment is done directly to the 148 * controller device. 149 */ 150 static int cxgb_port_probe(device_t); 151 static int cxgb_port_attach(device_t); 152 static int cxgb_port_detach(device_t); 153 154 static device_method_t cxgb_port_methods[] = { 155 DEVMETHOD(device_probe, cxgb_port_probe), 156 DEVMETHOD(device_attach, cxgb_port_attach), 157 DEVMETHOD(device_detach, cxgb_port_detach), 158 { 0, 0 } 159 }; 160 161 static driver_t cxgb_port_driver = { 162 "cxgb", 163 cxgb_port_methods, 164 0 165 }; 166 167 static d_ioctl_t cxgb_extension_ioctl; 168 static d_open_t cxgb_extension_open; 169 static d_close_t cxgb_extension_close; 170 171 static struct cdevsw cxgb_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = cxgb_extension_open, 175 .d_close = cxgb_extension_close, 176 .d_ioctl = cxgb_extension_ioctl, 177 .d_name = "cxgb", 178 }; 179 180 static devclass_t cxgb_port_devclass; 181 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 182 183 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 184 185 /* 186 * The driver uses the best interrupt scheme available on a platform in the 187 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 188 * of these schemes the driver may consider as follows: 189 * 190 * msi = 2: choose from among all three options 191 * msi = 1 : only consider MSI and pin interrupts 192 * msi = 0: force pin interrupts 193 */ 194 static int msi_allowed = 2; 195 196 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 197 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 198 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 199 "MSI-X, MSI, INTx selector"); 200 201 /* 202 * The driver enables offload as a default. 203 * To disable it, use ofld_disable = 1. 204 */ 205 static int ofld_disable = 0; 206 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 207 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 208 "disable ULP offload"); 209 210 /* 211 * The driver uses an auto-queue algorithm by default. 212 * To disable it and force a single queue-set per port, use singleq = 1. 213 */ 214 static int singleq = 0; 215 TUNABLE_INT("hw.cxgb.singleq", &singleq); 216 SYSCTL_UINT(_hw_cxgb, OID_AUTO, singleq, CTLFLAG_RDTUN, &singleq, 0, 217 "use a single queue-set per port"); 218 219 220 /* 221 * The driver uses an auto-queue algorithm by default. 222 * To disable it and force a single queue-set per port, use singleq = 1. 223 */ 224 static int force_fw_update = 0; 225 TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 226 SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 227 "update firmware even if up to date"); 228 229 int cxgb_use_16k_clusters = 0; 230 TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 231 SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 232 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 233 234 enum { 235 MAX_TXQ_ENTRIES = 16384, 236 MAX_CTRL_TXQ_ENTRIES = 1024, 237 MAX_RSPQ_ENTRIES = 16384, 238 MAX_RX_BUFFERS = 16384, 239 MAX_RX_JUMBO_BUFFERS = 16384, 240 MIN_TXQ_ENTRIES = 4, 241 MIN_CTRL_TXQ_ENTRIES = 4, 242 MIN_RSPQ_ENTRIES = 32, 243 MIN_FL_ENTRIES = 32, 244 MIN_FL_JUMBO_ENTRIES = 32 245 }; 246 247 struct filter_info { 248 u32 sip; 249 u32 sip_mask; 250 u32 dip; 251 u16 sport; 252 u16 dport; 253 u32 vlan:12; 254 u32 vlan_prio:3; 255 u32 mac_hit:1; 256 u32 mac_idx:4; 257 u32 mac_vld:1; 258 u32 pkt_type:2; 259 u32 report_filter_id:1; 260 u32 pass:1; 261 u32 rss:1; 262 u32 qset:3; 263 u32 locked:1; 264 u32 valid:1; 265 }; 266 267 enum { FILTER_NO_VLAN_PRI = 7 }; 268 269 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 270 271 /* Table for probing the cards. The desc field isn't actually used */ 272 struct cxgb_ident { 273 uint16_t vendor; 274 uint16_t device; 275 int index; 276 char *desc; 277 } cxgb_identifiers[] = { 278 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 279 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 280 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 281 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 285 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 286 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 287 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 288 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 289 {0, 0, 0, NULL} 290 }; 291 292 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 293 294 295 void 296 cxgb_log_tcb(struct adapter *sc, unsigned int tid) 297 { 298 char buf[TCB_SIZE]; 299 uint64_t *tcb = (uint64_t *)buf; 300 int i, error; 301 struct mc7 *mem = &sc->cm; 302 303 error = t3_mc7_bd_read(mem, tid*TCB_SIZE/8, TCB_SIZE/8, tcb); 304 if (error) 305 printf("cxgb_tcb_log failed\n"); 306 307 CTR1(KTR_CXGB, "TCB tid=%u", tid); 308 for (i = 0; i < TCB_SIZE / 32; i++) { 309 CTR5(KTR_CXGB, "%1d: %08x %08x %08x %08x", 310 i, (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 311 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 312 tcb += 2; 313 CTR4(KTR_CXGB, " %08x %08x %08x %08x", 314 (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 315 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 316 tcb += 2; 317 } 318 } 319 320 static __inline char 321 t3rev2char(struct adapter *adapter) 322 { 323 char rev = 'z'; 324 325 switch(adapter->params.rev) { 326 case T3_REV_A: 327 rev = 'a'; 328 break; 329 case T3_REV_B: 330 case T3_REV_B2: 331 rev = 'b'; 332 break; 333 case T3_REV_C: 334 rev = 'c'; 335 break; 336 } 337 return rev; 338 } 339 340 static struct cxgb_ident * 341 cxgb_get_ident(device_t dev) 342 { 343 struct cxgb_ident *id; 344 345 for (id = cxgb_identifiers; id->desc != NULL; id++) { 346 if ((id->vendor == pci_get_vendor(dev)) && 347 (id->device == pci_get_device(dev))) { 348 return (id); 349 } 350 } 351 return (NULL); 352 } 353 354 static const struct adapter_info * 355 cxgb_get_adapter_info(device_t dev) 356 { 357 struct cxgb_ident *id; 358 const struct adapter_info *ai; 359 360 id = cxgb_get_ident(dev); 361 if (id == NULL) 362 return (NULL); 363 364 ai = t3_get_adapter_info(id->index); 365 366 return (ai); 367 } 368 369 static int 370 cxgb_controller_probe(device_t dev) 371 { 372 const struct adapter_info *ai; 373 char *ports, buf[80]; 374 int nports; 375 376 ai = cxgb_get_adapter_info(dev); 377 if (ai == NULL) 378 return (ENXIO); 379 380 nports = ai->nports0 + ai->nports1; 381 if (nports == 1) 382 ports = "port"; 383 else 384 ports = "ports"; 385 386 snprintf(buf, sizeof(buf), "%s RNIC, %d %s", ai->desc, nports, ports); 387 device_set_desc_copy(dev, buf); 388 return (BUS_PROBE_DEFAULT); 389 } 390 391 #define FW_FNAME "cxgb_t3fw" 392 #define TPEEPROM_NAME "t3b_tp_eeprom" 393 #define TPSRAM_NAME "t3b_protocol_sram" 394 395 static int 396 upgrade_fw(adapter_t *sc) 397 { 398 #ifdef FIRMWARE_LATEST 399 const struct firmware *fw; 400 #else 401 struct firmware *fw; 402 #endif 403 int status; 404 405 if ((fw = firmware_get(FW_FNAME)) == NULL) { 406 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 407 return (ENOENT); 408 } else 409 device_printf(sc->dev, "updating firmware on card\n"); 410 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 411 412 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 413 414 firmware_put(fw, FIRMWARE_UNLOAD); 415 416 return (status); 417 } 418 419 static int 420 cxgb_controller_attach(device_t dev) 421 { 422 device_t child; 423 const struct adapter_info *ai; 424 struct adapter *sc; 425 int i, error = 0; 426 uint32_t vers; 427 int port_qsets = 1; 428 #ifdef MSI_SUPPORTED 429 int msi_needed, reg; 430 #endif 431 int must_load = 0; 432 sc = device_get_softc(dev); 433 sc->dev = dev; 434 sc->msi_count = 0; 435 ai = cxgb_get_adapter_info(dev); 436 437 /* 438 * XXX not really related but a recent addition 439 */ 440 #ifdef MSI_SUPPORTED 441 /* find the PCIe link width and set max read request to 4KB*/ 442 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 443 uint16_t lnk, pectl; 444 lnk = pci_read_config(dev, reg + 0x12, 2); 445 sc->link_width = (lnk >> 4) & 0x3f; 446 447 pectl = pci_read_config(dev, reg + 0x8, 2); 448 pectl = (pectl & ~0x7000) | (5 << 12); 449 pci_write_config(dev, reg + 0x8, pectl, 2); 450 } 451 452 if (sc->link_width != 0 && sc->link_width <= 4 && 453 (ai->nports0 + ai->nports1) <= 2) { 454 device_printf(sc->dev, 455 "PCIe x%d Link, expect reduced performance\n", 456 sc->link_width); 457 } 458 #endif 459 touch_bars(dev); 460 pci_enable_busmaster(dev); 461 /* 462 * Allocate the registers and make them available to the driver. 463 * The registers that we care about for NIC mode are in BAR 0 464 */ 465 sc->regs_rid = PCIR_BAR(0); 466 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 467 &sc->regs_rid, RF_ACTIVE)) == NULL) { 468 device_printf(dev, "Cannot allocate BAR region 0\n"); 469 return (ENXIO); 470 } 471 sc->udbs_rid = PCIR_BAR(2); 472 if ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 473 &sc->udbs_rid, RF_ACTIVE)) == NULL) { 474 device_printf(dev, "Cannot allocate BAR region 1\n"); 475 error = ENXIO; 476 goto out; 477 } 478 479 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 480 device_get_unit(dev)); 481 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 482 483 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 484 device_get_unit(dev)); 485 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 486 device_get_unit(dev)); 487 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 488 device_get_unit(dev)); 489 490 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 491 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 492 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 493 494 sc->bt = rman_get_bustag(sc->regs_res); 495 sc->bh = rman_get_bushandle(sc->regs_res); 496 sc->mmio_len = rman_get_size(sc->regs_res); 497 498 if (t3_prep_adapter(sc, ai, 1) < 0) { 499 printf("prep adapter failed\n"); 500 error = ENODEV; 501 goto out; 502 } 503 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 504 * enough messages for the queue sets. If that fails, try falling 505 * back to MSI. If that fails, then try falling back to the legacy 506 * interrupt pin model. 507 */ 508 #ifdef MSI_SUPPORTED 509 510 sc->msix_regs_rid = 0x20; 511 if ((msi_allowed >= 2) && 512 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 513 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 514 515 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 516 517 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 518 (sc->msi_count != msi_needed)) { 519 device_printf(dev, "msix allocation failed - msi_count = %d" 520 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 521 msi_needed, error); 522 sc->msi_count = 0; 523 pci_release_msi(dev); 524 bus_release_resource(dev, SYS_RES_MEMORY, 525 sc->msix_regs_rid, sc->msix_regs_res); 526 sc->msix_regs_res = NULL; 527 } else { 528 sc->flags |= USING_MSIX; 529 sc->cxgb_intr = t3_intr_msix; 530 } 531 } 532 533 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 534 sc->msi_count = 1; 535 if (pci_alloc_msi(dev, &sc->msi_count)) { 536 device_printf(dev, "alloc msi failed - will try INTx\n"); 537 sc->msi_count = 0; 538 pci_release_msi(dev); 539 } else { 540 sc->flags |= USING_MSI; 541 sc->irq_rid = 1; 542 sc->cxgb_intr = t3_intr_msi; 543 } 544 } 545 #endif 546 if (sc->msi_count == 0) { 547 device_printf(dev, "using line interrupts\n"); 548 sc->irq_rid = 0; 549 sc->cxgb_intr = t3b_intr; 550 } 551 552 553 /* Create a private taskqueue thread for handling driver events */ 554 #ifdef TASKQUEUE_CURRENT 555 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 556 taskqueue_thread_enqueue, &sc->tq); 557 #else 558 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 559 taskqueue_thread_enqueue, &sc->tq); 560 #endif 561 if (sc->tq == NULL) { 562 device_printf(dev, "failed to allocate controller task queue\n"); 563 goto out; 564 } 565 566 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 567 device_get_nameunit(dev)); 568 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 569 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 570 571 572 /* Create a periodic callout for checking adapter status */ 573 callout_init(&sc->cxgb_tick_ch, TRUE); 574 575 if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) { 576 /* 577 * Warn user that a firmware update will be attempted in init. 578 */ 579 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 580 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 581 sc->flags &= ~FW_UPTODATE; 582 } else { 583 sc->flags |= FW_UPTODATE; 584 } 585 586 if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) { 587 /* 588 * Warn user that a firmware update will be attempted in init. 589 */ 590 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 591 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 592 sc->flags &= ~TPS_UPTODATE; 593 } else { 594 sc->flags |= TPS_UPTODATE; 595 } 596 597 if ((sc->flags & USING_MSIX) && !singleq) 598 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 599 600 /* 601 * Create a child device for each MAC. The ethernet attachment 602 * will be done in these children. 603 */ 604 for (i = 0; i < (sc)->params.nports; i++) { 605 struct port_info *pi; 606 607 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 608 device_printf(dev, "failed to add child port\n"); 609 error = EINVAL; 610 goto out; 611 } 612 pi = &sc->port[i]; 613 pi->adapter = sc; 614 pi->nqsets = port_qsets; 615 pi->first_qset = i*port_qsets; 616 pi->port_id = i; 617 pi->tx_chan = i >= ai->nports0; 618 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 619 sc->rxpkt_map[pi->txpkt_intf] = i; 620 sc->port[i].tx_chan = i >= ai->nports0; 621 sc->portdev[i] = child; 622 device_set_softc(child, pi); 623 } 624 if ((error = bus_generic_attach(dev)) != 0) 625 goto out; 626 627 /* 628 * XXX need to poll for link status 629 */ 630 sc->params.stats_update_period = 1; 631 632 /* initialize sge private state */ 633 t3_sge_init_adapter(sc); 634 635 t3_led_ready(sc); 636 637 cxgb_offload_init(); 638 if (is_offload(sc)) { 639 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 640 cxgb_adapter_ofld(sc); 641 } 642 error = t3_get_fw_version(sc, &vers); 643 if (error) 644 goto out; 645 646 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 647 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 648 G_FW_VERSION_MICRO(vers)); 649 650 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 651 callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); 652 t3_add_attach_sysctls(sc); 653 out: 654 if (error) 655 cxgb_free(sc); 656 657 return (error); 658 } 659 660 static int 661 cxgb_controller_detach(device_t dev) 662 { 663 struct adapter *sc; 664 665 sc = device_get_softc(dev); 666 667 cxgb_free(sc); 668 669 return (0); 670 } 671 672 static void 673 cxgb_free(struct adapter *sc) 674 { 675 int i; 676 677 ADAPTER_LOCK(sc); 678 sc->flags |= CXGB_SHUTDOWN; 679 ADAPTER_UNLOCK(sc); 680 cxgb_pcpu_shutdown_threads(sc); 681 ADAPTER_LOCK(sc); 682 683 /* 684 * drops the lock 685 */ 686 cxgb_down_locked(sc); 687 688 #ifdef MSI_SUPPORTED 689 if (sc->flags & (USING_MSI | USING_MSIX)) { 690 device_printf(sc->dev, "releasing msi message(s)\n"); 691 pci_release_msi(sc->dev); 692 } else { 693 device_printf(sc->dev, "no msi message to release\n"); 694 } 695 #endif 696 if (sc->msix_regs_res != NULL) { 697 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 698 sc->msix_regs_res); 699 } 700 701 t3_sge_deinit_sw(sc); 702 /* 703 * Wait for last callout 704 */ 705 706 DELAY(hz*100); 707 708 for (i = 0; i < (sc)->params.nports; ++i) { 709 if (sc->portdev[i] != NULL) 710 device_delete_child(sc->dev, sc->portdev[i]); 711 } 712 713 bus_generic_detach(sc->dev); 714 if (sc->tq != NULL) { 715 taskqueue_free(sc->tq); 716 sc->tq = NULL; 717 } 718 719 if (is_offload(sc)) { 720 cxgb_adapter_unofld(sc); 721 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 722 offload_close(&sc->tdev); 723 else 724 printf("cxgb_free: DEVMAP_BIT not set\n"); 725 } else 726 printf("not offloading set\n"); 727 728 if (sc->flags & CXGB_OFLD_INIT) 729 cxgb_offload_deactivate(sc); 730 free(sc->filters, M_DEVBUF); 731 t3_sge_free(sc); 732 733 cxgb_offload_exit(); 734 735 if (sc->udbs_res != NULL) 736 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 737 sc->udbs_res); 738 739 if (sc->regs_res != NULL) 740 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 741 sc->regs_res); 742 743 MTX_DESTROY(&sc->mdio_lock); 744 MTX_DESTROY(&sc->sge.reg_lock); 745 MTX_DESTROY(&sc->elmer_lock); 746 ADAPTER_LOCK_DEINIT(sc); 747 } 748 749 /** 750 * setup_sge_qsets - configure SGE Tx/Rx/response queues 751 * @sc: the controller softc 752 * 753 * Determines how many sets of SGE queues to use and initializes them. 754 * We support multiple queue sets per port if we have MSI-X, otherwise 755 * just one queue set per port. 756 */ 757 static int 758 setup_sge_qsets(adapter_t *sc) 759 { 760 int i, j, err, irq_idx = 0, qset_idx = 0; 761 u_int ntxq = SGE_TXQ_PER_SET; 762 763 if ((err = t3_sge_alloc(sc)) != 0) { 764 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 765 return (err); 766 } 767 768 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 769 irq_idx = -1; 770 771 for (i = 0; i < (sc)->params.nports; i++) { 772 struct port_info *pi = &sc->port[i]; 773 774 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 775 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 776 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 777 &sc->params.sge.qset[qset_idx], ntxq, pi); 778 if (err) { 779 t3_free_sge_resources(sc); 780 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 781 err); 782 return (err); 783 } 784 } 785 } 786 787 return (0); 788 } 789 790 static void 791 cxgb_teardown_msix(adapter_t *sc) 792 { 793 int i, nqsets; 794 795 for (nqsets = i = 0; i < (sc)->params.nports; i++) 796 nqsets += sc->port[i].nqsets; 797 798 for (i = 0; i < nqsets; i++) { 799 if (sc->msix_intr_tag[i] != NULL) { 800 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 801 sc->msix_intr_tag[i]); 802 sc->msix_intr_tag[i] = NULL; 803 } 804 if (sc->msix_irq_res[i] != NULL) { 805 bus_release_resource(sc->dev, SYS_RES_IRQ, 806 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 807 sc->msix_irq_res[i] = NULL; 808 } 809 } 810 } 811 812 static int 813 cxgb_setup_msix(adapter_t *sc, int msix_count) 814 { 815 int i, j, k, nqsets, rid; 816 817 /* The first message indicates link changes and error conditions */ 818 sc->irq_rid = 1; 819 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 820 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 821 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 822 return (EINVAL); 823 } 824 825 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 826 #ifdef INTR_FILTERS 827 NULL, 828 #endif 829 cxgb_async_intr, sc, &sc->intr_tag)) { 830 device_printf(sc->dev, "Cannot set up interrupt\n"); 831 return (EINVAL); 832 } 833 for (i = k = 0; i < (sc)->params.nports; i++) { 834 nqsets = sc->port[i].nqsets; 835 for (j = 0; j < nqsets; j++, k++) { 836 struct sge_qset *qs = &sc->sge.qs[k]; 837 838 rid = k + 2; 839 if (cxgb_debug) 840 printf("rid=%d ", rid); 841 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 842 sc->dev, SYS_RES_IRQ, &rid, 843 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 844 device_printf(sc->dev, "Cannot allocate " 845 "interrupt for message %d\n", rid); 846 return (EINVAL); 847 } 848 sc->msix_irq_rid[k] = rid; 849 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 850 INTR_MPSAFE|INTR_TYPE_NET, 851 #ifdef INTR_FILTERS 852 NULL, 853 #endif 854 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 855 device_printf(sc->dev, "Cannot set up " 856 "interrupt for message %d\n", rid); 857 return (EINVAL); 858 } 859 #ifdef IFNET_MULTIQUEUE 860 if (singleq == 0) { 861 int vector = rman_get_start(sc->msix_irq_res[k]); 862 if (bootverbose) 863 device_printf(sc->dev, "binding vector=%d to cpu=%d\n", vector, k % mp_ncpus); 864 intr_bind(vector, k % mp_ncpus); 865 } 866 #endif 867 } 868 } 869 870 return (0); 871 } 872 873 static int 874 cxgb_port_probe(device_t dev) 875 { 876 struct port_info *p; 877 char buf[80]; 878 const char *desc; 879 880 p = device_get_softc(dev); 881 desc = p->phy.desc; 882 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 883 device_set_desc_copy(dev, buf); 884 return (0); 885 } 886 887 888 static int 889 cxgb_makedev(struct port_info *pi) 890 { 891 892 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 893 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 894 895 if (pi->port_cdev == NULL) 896 return (ENOMEM); 897 898 pi->port_cdev->si_drv1 = (void *)pi; 899 900 return (0); 901 } 902 903 904 #ifdef TSO_SUPPORTED 905 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU) 906 /* Don't enable TSO6 yet */ 907 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU) 908 #else 909 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 910 /* Don't enable TSO6 yet */ 911 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 912 #define IFCAP_TSO4 0x0 913 #define IFCAP_TSO6 0x0 914 #define CSUM_TSO 0x0 915 #endif 916 917 918 static int 919 cxgb_port_attach(device_t dev) 920 { 921 struct port_info *p; 922 struct ifnet *ifp; 923 int err, media_flags; 924 struct adapter *sc; 925 926 927 p = device_get_softc(dev); 928 sc = p->adapter; 929 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 930 device_get_unit(device_get_parent(dev)), p->port_id); 931 PORT_LOCK_INIT(p, p->lockbuf); 932 933 /* Allocate an ifnet object and set it up */ 934 ifp = p->ifp = if_alloc(IFT_ETHER); 935 if (ifp == NULL) { 936 device_printf(dev, "Cannot allocate ifnet\n"); 937 return (ENOMEM); 938 } 939 940 /* 941 * Note that there is currently no watchdog timer. 942 */ 943 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 944 ifp->if_init = cxgb_init; 945 ifp->if_softc = p; 946 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 947 ifp->if_ioctl = cxgb_ioctl; 948 ifp->if_start = cxgb_start; 949 950 #if 0 951 #ifdef IFNET_MULTIQUEUE 952 ifp->if_flags |= IFF_MULTIQ; 953 ifp->if_mq_start = cxgb_pcpu_start; 954 #endif 955 #endif 956 ifp->if_timer = 0; /* Disable ifnet watchdog */ 957 ifp->if_watchdog = NULL; 958 959 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 960 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 961 IFQ_SET_READY(&ifp->if_snd); 962 963 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 964 ifp->if_capabilities |= CXGB_CAP; 965 ifp->if_capenable |= CXGB_CAP_ENABLE; 966 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 967 /* 968 * disable TSO on 4-port - it isn't supported by the firmware yet 969 */ 970 if (p->adapter->params.nports > 2) { 971 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 972 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 973 ifp->if_hwassist &= ~CSUM_TSO; 974 } 975 976 ether_ifattach(ifp, p->hw_addr); 977 /* 978 * Only default to jumbo frames on 10GigE 979 */ 980 if (p->adapter->params.nports <= 2) 981 ifp->if_mtu = 9000; 982 if ((err = cxgb_makedev(p)) != 0) { 983 printf("makedev failed %d\n", err); 984 return (err); 985 } 986 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 987 cxgb_media_status); 988 989 if (!strcmp(p->phy.desc, "10GBASE-CX4")) { 990 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 991 } else if (!strcmp(p->phy.desc, "10GBASE-SR")) { 992 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 993 } else if (!strcmp(p->phy.desc, "10GBASE-XR")) { 994 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 995 } else if (!strcmp(p->phy.desc, "10/100/1000BASE-T")) { 996 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 997 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 998 0, NULL); 999 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 1000 0, NULL); 1001 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1002 0, NULL); 1003 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1004 0, NULL); 1005 media_flags = 0; 1006 } else { 1007 printf("unsupported media type %s\n", p->phy.desc); 1008 return (ENXIO); 1009 } 1010 if (media_flags) { 1011 ifmedia_add(&p->media, media_flags, 0, NULL); 1012 ifmedia_set(&p->media, media_flags); 1013 } else { 1014 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1015 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1016 } 1017 1018 1019 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id); 1020 #ifdef TASKQUEUE_CURRENT 1021 /* Create a port for handling TX without starvation */ 1022 p->tq = taskqueue_create(p->taskqbuf, M_NOWAIT, 1023 taskqueue_thread_enqueue, &p->tq); 1024 #else 1025 /* Create a port for handling TX without starvation */ 1026 p->tq = taskqueue_create_fast(p->taskqbuf, M_NOWAIT, 1027 taskqueue_thread_enqueue, &p->tq); 1028 #endif 1029 t3_sge_init_port(p); 1030 cxgb_link_start(p); 1031 t3_link_changed(sc, p->port_id); 1032 return (0); 1033 } 1034 1035 static int 1036 cxgb_port_detach(device_t dev) 1037 { 1038 struct port_info *p; 1039 1040 p = device_get_softc(dev); 1041 1042 PORT_LOCK(p); 1043 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1044 cxgb_stop_locked(p); 1045 PORT_UNLOCK(p); 1046 1047 if (p->tq != NULL) { 1048 taskqueue_drain(p->tq, &p->start_task); 1049 taskqueue_free(p->tq); 1050 p->tq = NULL; 1051 } 1052 1053 ether_ifdetach(p->ifp); 1054 printf("waiting for callout to stop ..."); 1055 DELAY(1000000); 1056 printf("done\n"); 1057 /* 1058 * the lock may be acquired in ifdetach 1059 */ 1060 PORT_LOCK_DEINIT(p); 1061 if_free(p->ifp); 1062 1063 if (p->port_cdev != NULL) 1064 destroy_dev(p->port_cdev); 1065 1066 return (0); 1067 } 1068 1069 void 1070 t3_fatal_err(struct adapter *sc) 1071 { 1072 u_int fw_status[4]; 1073 1074 if (sc->flags & FULL_INIT_DONE) { 1075 t3_sge_stop(sc); 1076 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1077 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1078 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1079 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1080 t3_intr_disable(sc); 1081 } 1082 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1083 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1084 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1085 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1086 } 1087 1088 int 1089 t3_os_find_pci_capability(adapter_t *sc, int cap) 1090 { 1091 device_t dev; 1092 struct pci_devinfo *dinfo; 1093 pcicfgregs *cfg; 1094 uint32_t status; 1095 uint8_t ptr; 1096 1097 dev = sc->dev; 1098 dinfo = device_get_ivars(dev); 1099 cfg = &dinfo->cfg; 1100 1101 status = pci_read_config(dev, PCIR_STATUS, 2); 1102 if (!(status & PCIM_STATUS_CAPPRESENT)) 1103 return (0); 1104 1105 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1106 case 0: 1107 case 1: 1108 ptr = PCIR_CAP_PTR; 1109 break; 1110 case 2: 1111 ptr = PCIR_CAP_PTR_2; 1112 break; 1113 default: 1114 return (0); 1115 break; 1116 } 1117 ptr = pci_read_config(dev, ptr, 1); 1118 1119 while (ptr != 0) { 1120 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1121 return (ptr); 1122 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1123 } 1124 1125 return (0); 1126 } 1127 1128 int 1129 t3_os_pci_save_state(struct adapter *sc) 1130 { 1131 device_t dev; 1132 struct pci_devinfo *dinfo; 1133 1134 dev = sc->dev; 1135 dinfo = device_get_ivars(dev); 1136 1137 pci_cfg_save(dev, dinfo, 0); 1138 return (0); 1139 } 1140 1141 int 1142 t3_os_pci_restore_state(struct adapter *sc) 1143 { 1144 device_t dev; 1145 struct pci_devinfo *dinfo; 1146 1147 dev = sc->dev; 1148 dinfo = device_get_ivars(dev); 1149 1150 pci_cfg_restore(dev, dinfo); 1151 return (0); 1152 } 1153 1154 /** 1155 * t3_os_link_changed - handle link status changes 1156 * @adapter: the adapter associated with the link change 1157 * @port_id: the port index whose limk status has changed 1158 * @link_stat: the new status of the link 1159 * @speed: the new speed setting 1160 * @duplex: the new duplex setting 1161 * @fc: the new flow-control setting 1162 * 1163 * This is the OS-dependent handler for link status changes. The OS 1164 * neutral handler takes care of most of the processing for these events, 1165 * then calls this handler for any OS-specific processing. 1166 */ 1167 void 1168 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1169 int duplex, int fc) 1170 { 1171 struct port_info *pi = &adapter->port[port_id]; 1172 struct cmac *mac = &adapter->port[port_id].mac; 1173 1174 if (link_status) { 1175 t3_mac_enable(mac, MAC_DIRECTION_RX); 1176 if_link_state_change(pi->ifp, LINK_STATE_UP); 1177 } else { 1178 pi->phy.ops->power_down(&pi->phy, 1); 1179 t3_mac_disable(mac, MAC_DIRECTION_RX); 1180 t3_link_start(&pi->phy, mac, &pi->link_config); 1181 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1182 } 1183 } 1184 1185 /* 1186 * Interrupt-context handler for external (PHY) interrupts. 1187 */ 1188 void 1189 t3_os_ext_intr_handler(adapter_t *sc) 1190 { 1191 if (cxgb_debug) 1192 printf("t3_os_ext_intr_handler\n"); 1193 /* 1194 * Schedule a task to handle external interrupts as they may be slow 1195 * and we use a mutex to protect MDIO registers. We disable PHY 1196 * interrupts in the meantime and let the task reenable them when 1197 * it's done. 1198 */ 1199 ADAPTER_LOCK(sc); 1200 if (sc->slow_intr_mask) { 1201 sc->slow_intr_mask &= ~F_T3DBG; 1202 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1203 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1204 } 1205 ADAPTER_UNLOCK(sc); 1206 } 1207 1208 void 1209 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1210 { 1211 1212 /* 1213 * The ifnet might not be allocated before this gets called, 1214 * as this is called early on in attach by t3_prep_adapter 1215 * save the address off in the port structure 1216 */ 1217 if (cxgb_debug) 1218 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1219 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1220 } 1221 1222 /** 1223 * link_start - enable a port 1224 * @p: the port to enable 1225 * 1226 * Performs the MAC and PHY actions needed to enable a port. 1227 */ 1228 static void 1229 cxgb_link_start(struct port_info *p) 1230 { 1231 struct ifnet *ifp; 1232 struct t3_rx_mode rm; 1233 struct cmac *mac = &p->mac; 1234 1235 ifp = p->ifp; 1236 1237 t3_init_rx_mode(&rm, p); 1238 if (!mac->multiport) 1239 t3_mac_reset(mac); 1240 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1241 t3_mac_set_address(mac, 0, p->hw_addr); 1242 t3_mac_set_rx_mode(mac, &rm); 1243 t3_link_start(&p->phy, mac, &p->link_config); 1244 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1245 } 1246 1247 1248 static int 1249 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1250 unsigned long n) 1251 { 1252 int attempts = 5; 1253 1254 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1255 if (!--attempts) 1256 return (ETIMEDOUT); 1257 t3_os_sleep(10); 1258 } 1259 return 0; 1260 } 1261 1262 static int 1263 init_tp_parity(struct adapter *adap) 1264 { 1265 int i; 1266 struct mbuf *m; 1267 struct cpl_set_tcb_field *greq; 1268 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1269 1270 t3_tp_set_offload_mode(adap, 1); 1271 1272 for (i = 0; i < 16; i++) { 1273 struct cpl_smt_write_req *req; 1274 1275 m = m_gethdr(M_WAITOK, MT_DATA); 1276 req = mtod(m, struct cpl_smt_write_req *); 1277 m->m_len = m->m_pkthdr.len = sizeof(*req); 1278 memset(req, 0, sizeof(*req)); 1279 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1280 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1281 req->iff = i; 1282 t3_mgmt_tx(adap, m); 1283 } 1284 1285 for (i = 0; i < 2048; i++) { 1286 struct cpl_l2t_write_req *req; 1287 1288 m = m_gethdr(M_WAITOK, MT_DATA); 1289 req = mtod(m, struct cpl_l2t_write_req *); 1290 m->m_len = m->m_pkthdr.len = sizeof(*req); 1291 memset(req, 0, sizeof(*req)); 1292 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1293 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1294 req->params = htonl(V_L2T_W_IDX(i)); 1295 t3_mgmt_tx(adap, m); 1296 } 1297 1298 for (i = 0; i < 2048; i++) { 1299 struct cpl_rte_write_req *req; 1300 1301 m = m_gethdr(M_WAITOK, MT_DATA); 1302 req = mtod(m, struct cpl_rte_write_req *); 1303 m->m_len = m->m_pkthdr.len = sizeof(*req); 1304 memset(req, 0, sizeof(*req)); 1305 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1306 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1307 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1308 t3_mgmt_tx(adap, m); 1309 } 1310 1311 m = m_gethdr(M_WAITOK, MT_DATA); 1312 greq = mtod(m, struct cpl_set_tcb_field *); 1313 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1314 memset(greq, 0, sizeof(*greq)); 1315 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1316 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1317 greq->mask = htobe64(1); 1318 t3_mgmt_tx(adap, m); 1319 1320 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1321 t3_tp_set_offload_mode(adap, 0); 1322 return (i); 1323 } 1324 1325 /** 1326 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1327 * @adap: the adapter 1328 * 1329 * Sets up RSS to distribute packets to multiple receive queues. We 1330 * configure the RSS CPU lookup table to distribute to the number of HW 1331 * receive queues, and the response queue lookup table to narrow that 1332 * down to the response queues actually configured for each port. 1333 * We always configure the RSS mapping for two ports since the mapping 1334 * table has plenty of entries. 1335 */ 1336 static void 1337 setup_rss(adapter_t *adap) 1338 { 1339 int i; 1340 u_int nq[2]; 1341 uint8_t cpus[SGE_QSETS + 1]; 1342 uint16_t rspq_map[RSS_TABLE_SIZE]; 1343 1344 for (i = 0; i < SGE_QSETS; ++i) 1345 cpus[i] = i; 1346 cpus[SGE_QSETS] = 0xff; 1347 1348 nq[0] = nq[1] = 0; 1349 for_each_port(adap, i) { 1350 const struct port_info *pi = adap2pinfo(adap, i); 1351 1352 nq[pi->tx_chan] += pi->nqsets; 1353 } 1354 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1355 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1356 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1357 } 1358 /* Calculate the reverse RSS map table */ 1359 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1360 if (adap->rrss_map[rspq_map[i]] == 0xff) 1361 adap->rrss_map[rspq_map[i]] = i; 1362 1363 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1364 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1365 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1366 cpus, rspq_map); 1367 1368 } 1369 1370 /* 1371 * Sends an mbuf to an offload queue driver 1372 * after dealing with any active network taps. 1373 */ 1374 static inline int 1375 offload_tx(struct t3cdev *tdev, struct mbuf *m) 1376 { 1377 int ret; 1378 1379 ret = t3_offload_tx(tdev, m); 1380 return (ret); 1381 } 1382 1383 static int 1384 write_smt_entry(struct adapter *adapter, int idx) 1385 { 1386 struct port_info *pi = &adapter->port[idx]; 1387 struct cpl_smt_write_req *req; 1388 struct mbuf *m; 1389 1390 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1391 return (ENOMEM); 1392 1393 req = mtod(m, struct cpl_smt_write_req *); 1394 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1395 1396 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1397 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1398 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1399 req->iff = idx; 1400 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1401 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1402 1403 m_set_priority(m, 1); 1404 1405 offload_tx(&adapter->tdev, m); 1406 1407 return (0); 1408 } 1409 1410 static int 1411 init_smt(struct adapter *adapter) 1412 { 1413 int i; 1414 1415 for_each_port(adapter, i) 1416 write_smt_entry(adapter, i); 1417 return 0; 1418 } 1419 1420 static void 1421 init_port_mtus(adapter_t *adapter) 1422 { 1423 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1424 1425 if (adapter->port[1].ifp) 1426 mtus |= adapter->port[1].ifp->if_mtu << 16; 1427 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1428 } 1429 1430 static void 1431 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1432 int hi, int port) 1433 { 1434 struct mbuf *m; 1435 struct mngt_pktsched_wr *req; 1436 1437 m = m_gethdr(M_DONTWAIT, MT_DATA); 1438 if (m) { 1439 req = mtod(m, struct mngt_pktsched_wr *); 1440 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1441 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1442 req->sched = sched; 1443 req->idx = qidx; 1444 req->min = lo; 1445 req->max = hi; 1446 req->binding = port; 1447 m->m_len = m->m_pkthdr.len = sizeof(*req); 1448 t3_mgmt_tx(adap, m); 1449 } 1450 } 1451 1452 static void 1453 bind_qsets(adapter_t *sc) 1454 { 1455 int i, j; 1456 1457 cxgb_pcpu_startup_threads(sc); 1458 for (i = 0; i < (sc)->params.nports; ++i) { 1459 const struct port_info *pi = adap2pinfo(sc, i); 1460 1461 for (j = 0; j < pi->nqsets; ++j) { 1462 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1463 -1, pi->tx_chan); 1464 1465 } 1466 } 1467 } 1468 1469 static void 1470 update_tpeeprom(struct adapter *adap) 1471 { 1472 #ifdef FIRMWARE_LATEST 1473 const struct firmware *tpeeprom; 1474 #else 1475 struct firmware *tpeeprom; 1476 #endif 1477 1478 uint32_t version; 1479 unsigned int major, minor; 1480 int ret, len; 1481 char rev; 1482 1483 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1484 1485 major = G_TP_VERSION_MAJOR(version); 1486 minor = G_TP_VERSION_MINOR(version); 1487 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1488 return; 1489 1490 rev = t3rev2char(adap); 1491 1492 tpeeprom = firmware_get(TPEEPROM_NAME); 1493 if (tpeeprom == NULL) { 1494 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1495 TPEEPROM_NAME); 1496 return; 1497 } 1498 1499 len = tpeeprom->datasize - 4; 1500 1501 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1502 if (ret) 1503 goto release_tpeeprom; 1504 1505 if (len != TP_SRAM_LEN) { 1506 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", TPEEPROM_NAME, len, TP_SRAM_LEN); 1507 return; 1508 } 1509 1510 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1511 TP_SRAM_OFFSET); 1512 1513 if (!ret) { 1514 device_printf(adap->dev, 1515 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1516 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1517 } else 1518 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1519 1520 release_tpeeprom: 1521 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1522 1523 return; 1524 } 1525 1526 static int 1527 update_tpsram(struct adapter *adap) 1528 { 1529 #ifdef FIRMWARE_LATEST 1530 const struct firmware *tpsram; 1531 #else 1532 struct firmware *tpsram; 1533 #endif 1534 int ret; 1535 char rev; 1536 1537 rev = t3rev2char(adap); 1538 if (!rev) 1539 return 0; 1540 1541 update_tpeeprom(adap); 1542 1543 tpsram = firmware_get(TPSRAM_NAME); 1544 if (tpsram == NULL){ 1545 device_printf(adap->dev, "could not load TP SRAM\n"); 1546 return (EINVAL); 1547 } else 1548 device_printf(adap->dev, "updating TP SRAM\n"); 1549 1550 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1551 if (ret) 1552 goto release_tpsram; 1553 1554 ret = t3_set_proto_sram(adap, tpsram->data); 1555 if (ret) 1556 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1557 1558 release_tpsram: 1559 firmware_put(tpsram, FIRMWARE_UNLOAD); 1560 1561 return ret; 1562 } 1563 1564 /** 1565 * cxgb_up - enable the adapter 1566 * @adap: adapter being enabled 1567 * 1568 * Called when the first port is enabled, this function performs the 1569 * actions necessary to make an adapter operational, such as completing 1570 * the initialization of HW modules, and enabling interrupts. 1571 * 1572 */ 1573 static int 1574 cxgb_up(struct adapter *sc) 1575 { 1576 int err = 0; 1577 1578 if ((sc->flags & FULL_INIT_DONE) == 0) { 1579 1580 if ((sc->flags & FW_UPTODATE) == 0) 1581 if ((err = upgrade_fw(sc))) 1582 goto out; 1583 if ((sc->flags & TPS_UPTODATE) == 0) 1584 if ((err = update_tpsram(sc))) 1585 goto out; 1586 err = t3_init_hw(sc, 0); 1587 if (err) 1588 goto out; 1589 1590 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1591 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1592 1593 err = setup_sge_qsets(sc); 1594 if (err) 1595 goto out; 1596 1597 setup_rss(sc); 1598 t3_add_configured_sysctls(sc); 1599 sc->flags |= FULL_INIT_DONE; 1600 } 1601 1602 t3_intr_clear(sc); 1603 1604 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1605 if ((sc->flags & USING_MSIX) == 0) { 1606 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1607 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1608 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", 1609 sc->irq_rid); 1610 err = EINVAL; 1611 goto out; 1612 } 1613 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1614 1615 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1616 #ifdef INTR_FILTERS 1617 NULL, 1618 #endif 1619 sc->cxgb_intr, sc, &sc->intr_tag)) { 1620 device_printf(sc->dev, "Cannot set up interrupt\n"); 1621 err = EINVAL; 1622 goto irq_err; 1623 } 1624 } else { 1625 cxgb_setup_msix(sc, sc->msi_count); 1626 } 1627 1628 t3_sge_start(sc); 1629 t3_intr_enable(sc); 1630 1631 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1632 is_offload(sc) && init_tp_parity(sc) == 0) 1633 sc->flags |= TP_PARITY_INIT; 1634 1635 if (sc->flags & TP_PARITY_INIT) { 1636 t3_write_reg(sc, A_TP_INT_CAUSE, 1637 F_CMCACHEPERR | F_ARPLUTPERR); 1638 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1639 } 1640 1641 1642 if (!(sc->flags & QUEUES_BOUND)) { 1643 bind_qsets(sc); 1644 sc->flags |= QUEUES_BOUND; 1645 } 1646 out: 1647 return (err); 1648 irq_err: 1649 CH_ERR(sc, "request_irq failed, err %d\n", err); 1650 goto out; 1651 } 1652 1653 1654 /* 1655 * Release resources when all the ports and offloading have been stopped. 1656 */ 1657 static void 1658 cxgb_down_locked(struct adapter *sc) 1659 { 1660 1661 t3_sge_stop(sc); 1662 t3_intr_disable(sc); 1663 1664 if (sc->intr_tag != NULL) { 1665 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1666 sc->intr_tag = NULL; 1667 } 1668 if (sc->irq_res != NULL) { 1669 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1670 sc->irq_rid, sc->irq_res); 1671 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1672 sc->irq_res); 1673 sc->irq_res = NULL; 1674 } 1675 1676 if (sc->flags & USING_MSIX) 1677 cxgb_teardown_msix(sc); 1678 1679 callout_stop(&sc->cxgb_tick_ch); 1680 callout_stop(&sc->sge_timer_ch); 1681 callout_drain(&sc->cxgb_tick_ch); 1682 callout_drain(&sc->sge_timer_ch); 1683 1684 if (sc->tq != NULL) { 1685 printf("draining slow intr\n"); 1686 1687 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1688 printf("draining ext intr\n"); 1689 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1690 printf("draining tick task\n"); 1691 taskqueue_drain(sc->tq, &sc->tick_task); 1692 } 1693 ADAPTER_UNLOCK(sc); 1694 } 1695 1696 static int 1697 offload_open(struct port_info *pi) 1698 { 1699 struct adapter *adapter = pi->adapter; 1700 struct t3cdev *tdev = &adapter->tdev; 1701 #ifdef notyet 1702 T3CDEV(pi->ifp); 1703 #endif 1704 int adap_up = adapter->open_device_map & PORT_MASK; 1705 int err = 0; 1706 1707 CTR1(KTR_CXGB, "device_map=0x%x", adapter->open_device_map); 1708 if (atomic_cmpset_int(&adapter->open_device_map, 1709 (adapter->open_device_map & ~(1<<OFFLOAD_DEVMAP_BIT)), 1710 (adapter->open_device_map | (1<<OFFLOAD_DEVMAP_BIT))) == 0) 1711 return (0); 1712 1713 1714 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1715 printf("offload_open: DEVMAP_BIT did not get set 0x%x\n", adapter->open_device_map); 1716 ADAPTER_LOCK(pi->adapter); 1717 if (!adap_up) 1718 err = cxgb_up(adapter); 1719 ADAPTER_UNLOCK(pi->adapter); 1720 if (err) 1721 return (err); 1722 1723 t3_tp_set_offload_mode(adapter, 1); 1724 tdev->lldev = pi->ifp; 1725 err = cxgb_offload_activate(adapter); 1726 if (err) 1727 goto out; 1728 1729 init_port_mtus(adapter); 1730 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1731 adapter->params.b_wnd, 1732 adapter->params.rev == 0 ? 1733 adapter->port[0].ifp->if_mtu : 0xffff); 1734 init_smt(adapter); 1735 1736 /* Call back all registered clients */ 1737 cxgb_add_clients(tdev); 1738 1739 out: 1740 /* restore them in case the offload module has changed them */ 1741 if (err) { 1742 t3_tp_set_offload_mode(adapter, 0); 1743 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1744 cxgb_set_dummy_ops(tdev); 1745 } 1746 return (err); 1747 } 1748 1749 static int 1750 offload_close(struct t3cdev *tdev) 1751 { 1752 struct adapter *adapter = tdev2adap(tdev); 1753 1754 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1755 return (0); 1756 1757 /* Call back all registered clients */ 1758 cxgb_remove_clients(tdev); 1759 tdev->lldev = NULL; 1760 cxgb_set_dummy_ops(tdev); 1761 t3_tp_set_offload_mode(adapter, 0); 1762 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1763 1764 ADAPTER_LOCK(adapter); 1765 if (!adapter->open_device_map) 1766 cxgb_down_locked(adapter); 1767 else 1768 ADAPTER_UNLOCK(adapter); 1769 return (0); 1770 } 1771 1772 1773 static void 1774 cxgb_init(void *arg) 1775 { 1776 struct port_info *p = arg; 1777 1778 PORT_LOCK(p); 1779 cxgb_init_locked(p); 1780 PORT_UNLOCK(p); 1781 } 1782 1783 static void 1784 cxgb_init_locked(struct port_info *p) 1785 { 1786 struct ifnet *ifp; 1787 adapter_t *sc = p->adapter; 1788 int err; 1789 1790 PORT_LOCK_ASSERT_OWNED(p); 1791 ifp = p->ifp; 1792 1793 ADAPTER_LOCK(p->adapter); 1794 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1795 ADAPTER_UNLOCK(p->adapter); 1796 cxgb_stop_locked(p); 1797 return; 1798 } 1799 if (p->adapter->open_device_map == 0) { 1800 t3_intr_clear(sc); 1801 } 1802 setbit(&p->adapter->open_device_map, p->port_id); 1803 ADAPTER_UNLOCK(p->adapter); 1804 1805 if (is_offload(sc) && !ofld_disable) { 1806 err = offload_open(p); 1807 if (err) 1808 log(LOG_WARNING, 1809 "Could not initialize offload capabilities\n"); 1810 } 1811 ifp->if_baudrate = p->link_config.speed * 1000000; 1812 1813 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1814 t3_port_intr_enable(sc, p->port_id); 1815 1816 t3_sge_reset_adapter(sc); 1817 1818 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1819 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1820 } 1821 1822 static void 1823 cxgb_set_rxmode(struct port_info *p) 1824 { 1825 struct t3_rx_mode rm; 1826 struct cmac *mac = &p->mac; 1827 1828 t3_init_rx_mode(&rm, p); 1829 mtx_lock(&p->adapter->mdio_lock); 1830 t3_mac_set_rx_mode(mac, &rm); 1831 mtx_unlock(&p->adapter->mdio_lock); 1832 } 1833 1834 static void 1835 cxgb_stop_locked(struct port_info *p) 1836 { 1837 struct ifnet *ifp; 1838 1839 PORT_LOCK_ASSERT_OWNED(p); 1840 ADAPTER_LOCK_ASSERT_NOTOWNED(p->adapter); 1841 1842 ifp = p->ifp; 1843 t3_port_intr_disable(p->adapter, p->port_id); 1844 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1845 p->phy.ops->power_down(&p->phy, 1); 1846 t3_mac_disable(&p->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1847 1848 ADAPTER_LOCK(p->adapter); 1849 clrbit(&p->adapter->open_device_map, p->port_id); 1850 1851 if (p->adapter->open_device_map == 0) { 1852 cxgb_down_locked(p->adapter); 1853 } else 1854 ADAPTER_UNLOCK(p->adapter); 1855 1856 } 1857 1858 static int 1859 cxgb_set_mtu(struct port_info *p, int mtu) 1860 { 1861 struct ifnet *ifp = p->ifp; 1862 int error = 0; 1863 1864 if ((mtu < ETHERMIN) || (mtu > ETHER_MAX_LEN_JUMBO)) 1865 error = EINVAL; 1866 else if (ifp->if_mtu != mtu) { 1867 PORT_LOCK(p); 1868 ifp->if_mtu = mtu; 1869 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1870 cxgb_stop_locked(p); 1871 cxgb_init_locked(p); 1872 } 1873 PORT_UNLOCK(p); 1874 } 1875 return (error); 1876 } 1877 1878 static int 1879 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1880 { 1881 struct port_info *p = ifp->if_softc; 1882 struct ifaddr *ifa = (struct ifaddr *)data; 1883 struct ifreq *ifr = (struct ifreq *)data; 1884 int flags, error = 0; 1885 uint32_t mask; 1886 1887 /* 1888 * XXX need to check that we aren't in the middle of an unload 1889 */ 1890 switch (command) { 1891 case SIOCSIFMTU: 1892 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1893 break; 1894 case SIOCSIFADDR: 1895 if (ifa->ifa_addr->sa_family == AF_INET) { 1896 ifp->if_flags |= IFF_UP; 1897 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1898 PORT_LOCK(p); 1899 cxgb_init_locked(p); 1900 PORT_UNLOCK(p); 1901 } 1902 arp_ifinit(ifp, ifa); 1903 } else 1904 error = ether_ioctl(ifp, command, data); 1905 break; 1906 case SIOCSIFFLAGS: 1907 PORT_LOCK(p); 1908 if (ifp->if_flags & IFF_UP) { 1909 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1910 flags = p->if_flags; 1911 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1912 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1913 cxgb_set_rxmode(p); 1914 } else 1915 cxgb_init_locked(p); 1916 p->if_flags = ifp->if_flags; 1917 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1918 cxgb_stop_locked(p); 1919 1920 PORT_UNLOCK(p); 1921 break; 1922 case SIOCADDMULTI: 1923 case SIOCDELMULTI: 1924 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1925 cxgb_set_rxmode(p); 1926 } 1927 break; 1928 case SIOCSIFMEDIA: 1929 case SIOCGIFMEDIA: 1930 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1931 break; 1932 case SIOCSIFCAP: 1933 PORT_LOCK(p); 1934 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1935 if (mask & IFCAP_TXCSUM) { 1936 if (IFCAP_TXCSUM & ifp->if_capenable) { 1937 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 1938 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 1939 | CSUM_TSO); 1940 } else { 1941 ifp->if_capenable |= IFCAP_TXCSUM; 1942 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1943 } 1944 } else if (mask & IFCAP_RXCSUM) { 1945 if (IFCAP_RXCSUM & ifp->if_capenable) { 1946 ifp->if_capenable &= ~IFCAP_RXCSUM; 1947 } else { 1948 ifp->if_capenable |= IFCAP_RXCSUM; 1949 } 1950 } 1951 if (mask & IFCAP_TSO4) { 1952 if (IFCAP_TSO4 & ifp->if_capenable) { 1953 ifp->if_capenable &= ~IFCAP_TSO4; 1954 ifp->if_hwassist &= ~CSUM_TSO; 1955 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 1956 ifp->if_capenable |= IFCAP_TSO4; 1957 ifp->if_hwassist |= CSUM_TSO; 1958 } else { 1959 if (cxgb_debug) 1960 printf("cxgb requires tx checksum offload" 1961 " be enabled to use TSO\n"); 1962 error = EINVAL; 1963 } 1964 } 1965 PORT_UNLOCK(p); 1966 break; 1967 default: 1968 error = ether_ioctl(ifp, command, data); 1969 break; 1970 } 1971 return (error); 1972 } 1973 1974 static int 1975 cxgb_media_change(struct ifnet *ifp) 1976 { 1977 if_printf(ifp, "media change not supported\n"); 1978 return (ENXIO); 1979 } 1980 1981 static void 1982 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1983 { 1984 struct port_info *p = ifp->if_softc; 1985 1986 ifmr->ifm_status = IFM_AVALID; 1987 ifmr->ifm_active = IFM_ETHER; 1988 1989 if (!p->link_config.link_ok) 1990 return; 1991 1992 ifmr->ifm_status |= IFM_ACTIVE; 1993 1994 switch (p->link_config.speed) { 1995 case 10: 1996 ifmr->ifm_active |= IFM_10_T; 1997 break; 1998 case 100: 1999 ifmr->ifm_active |= IFM_100_TX; 2000 break; 2001 case 1000: 2002 ifmr->ifm_active |= IFM_1000_T; 2003 break; 2004 } 2005 2006 if (p->link_config.duplex) 2007 ifmr->ifm_active |= IFM_FDX; 2008 else 2009 ifmr->ifm_active |= IFM_HDX; 2010 } 2011 2012 static void 2013 cxgb_async_intr(void *data) 2014 { 2015 adapter_t *sc = data; 2016 2017 if (cxgb_debug) 2018 device_printf(sc->dev, "cxgb_async_intr\n"); 2019 /* 2020 * May need to sleep - defer to taskqueue 2021 */ 2022 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2023 } 2024 2025 static void 2026 cxgb_ext_intr_handler(void *arg, int count) 2027 { 2028 adapter_t *sc = (adapter_t *)arg; 2029 2030 if (cxgb_debug) 2031 printf("cxgb_ext_intr_handler\n"); 2032 2033 t3_phy_intr_handler(sc); 2034 2035 /* Now reenable external interrupts */ 2036 ADAPTER_LOCK(sc); 2037 if (sc->slow_intr_mask) { 2038 sc->slow_intr_mask |= F_T3DBG; 2039 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2040 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2041 } 2042 ADAPTER_UNLOCK(sc); 2043 } 2044 2045 static void 2046 check_link_status(adapter_t *sc) 2047 { 2048 int i; 2049 2050 for (i = 0; i < (sc)->params.nports; ++i) { 2051 struct port_info *p = &sc->port[i]; 2052 2053 if (!(p->phy.caps & SUPPORTED_IRQ)) 2054 t3_link_changed(sc, i); 2055 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2056 } 2057 } 2058 2059 static void 2060 check_t3b2_mac(struct adapter *adapter) 2061 { 2062 int i; 2063 2064 if(adapter->flags & CXGB_SHUTDOWN) 2065 return; 2066 2067 for_each_port(adapter, i) { 2068 struct port_info *p = &adapter->port[i]; 2069 struct ifnet *ifp = p->ifp; 2070 int status; 2071 2072 if(adapter->flags & CXGB_SHUTDOWN) 2073 return; 2074 2075 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2076 continue; 2077 2078 status = 0; 2079 PORT_LOCK(p); 2080 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2081 status = t3b2_mac_watchdog_task(&p->mac); 2082 if (status == 1) 2083 p->mac.stats.num_toggled++; 2084 else if (status == 2) { 2085 struct cmac *mac = &p->mac; 2086 2087 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN 2088 + ETHER_VLAN_ENCAP_LEN); 2089 t3_mac_set_address(mac, 0, p->hw_addr); 2090 cxgb_set_rxmode(p); 2091 t3_link_start(&p->phy, mac, &p->link_config); 2092 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2093 t3_port_intr_enable(adapter, p->port_id); 2094 p->mac.stats.num_resets++; 2095 } 2096 PORT_UNLOCK(p); 2097 } 2098 } 2099 2100 static void 2101 cxgb_tick(void *arg) 2102 { 2103 adapter_t *sc = (adapter_t *)arg; 2104 2105 if(sc->flags & CXGB_SHUTDOWN) 2106 return; 2107 2108 taskqueue_enqueue(sc->tq, &sc->tick_task); 2109 callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); 2110 } 2111 2112 static void 2113 cxgb_tick_handler(void *arg, int count) 2114 { 2115 adapter_t *sc = (adapter_t *)arg; 2116 const struct adapter_params *p = &sc->params; 2117 2118 if(sc->flags & CXGB_SHUTDOWN) 2119 return; 2120 2121 ADAPTER_LOCK(sc); 2122 if (p->linkpoll_period) 2123 check_link_status(sc); 2124 2125 /* 2126 * adapter lock can currently only be acquired after the 2127 * port lock 2128 */ 2129 ADAPTER_UNLOCK(sc); 2130 2131 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2132 check_t3b2_mac(sc); 2133 } 2134 2135 static void 2136 touch_bars(device_t dev) 2137 { 2138 /* 2139 * Don't enable yet 2140 */ 2141 #if !defined(__LP64__) && 0 2142 u32 v; 2143 2144 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2145 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2146 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2147 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2148 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2149 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2150 #endif 2151 } 2152 2153 static int 2154 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2155 { 2156 uint8_t *buf; 2157 int err = 0; 2158 u32 aligned_offset, aligned_len, *p; 2159 struct adapter *adapter = pi->adapter; 2160 2161 2162 aligned_offset = offset & ~3; 2163 aligned_len = (len + (offset & 3) + 3) & ~3; 2164 2165 if (aligned_offset != offset || aligned_len != len) { 2166 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2167 if (!buf) 2168 return (ENOMEM); 2169 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2170 if (!err && aligned_len > 4) 2171 err = t3_seeprom_read(adapter, 2172 aligned_offset + aligned_len - 4, 2173 (u32 *)&buf[aligned_len - 4]); 2174 if (err) 2175 goto out; 2176 memcpy(buf + (offset & 3), data, len); 2177 } else 2178 buf = (uint8_t *)(uintptr_t)data; 2179 2180 err = t3_seeprom_wp(adapter, 0); 2181 if (err) 2182 goto out; 2183 2184 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2185 err = t3_seeprom_write(adapter, aligned_offset, *p); 2186 aligned_offset += 4; 2187 } 2188 2189 if (!err) 2190 err = t3_seeprom_wp(adapter, 1); 2191 out: 2192 if (buf != data) 2193 free(buf, M_DEVBUF); 2194 return err; 2195 } 2196 2197 2198 static int 2199 in_range(int val, int lo, int hi) 2200 { 2201 return val < 0 || (val <= hi && val >= lo); 2202 } 2203 2204 static int 2205 cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2206 { 2207 return (0); 2208 } 2209 2210 static int 2211 cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2212 { 2213 return (0); 2214 } 2215 2216 static int 2217 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2218 int fflag, struct thread *td) 2219 { 2220 int mmd, error = 0; 2221 struct port_info *pi = dev->si_drv1; 2222 adapter_t *sc = pi->adapter; 2223 2224 #ifdef PRIV_SUPPORTED 2225 if (priv_check(td, PRIV_DRIVER)) { 2226 if (cxgb_debug) 2227 printf("user does not have access to privileged ioctls\n"); 2228 return (EPERM); 2229 } 2230 #else 2231 if (suser(td)) { 2232 if (cxgb_debug) 2233 printf("user does not have access to privileged ioctls\n"); 2234 return (EPERM); 2235 } 2236 #endif 2237 2238 switch (cmd) { 2239 case SIOCGMIIREG: { 2240 uint32_t val; 2241 struct cphy *phy = &pi->phy; 2242 struct mii_data *mid = (struct mii_data *)data; 2243 2244 if (!phy->mdio_read) 2245 return (EOPNOTSUPP); 2246 if (is_10G(sc)) { 2247 mmd = mid->phy_id >> 8; 2248 if (!mmd) 2249 mmd = MDIO_DEV_PCS; 2250 else if (mmd > MDIO_DEV_XGXS) 2251 return (EINVAL); 2252 2253 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2254 mid->reg_num, &val); 2255 } else 2256 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2257 mid->reg_num & 0x1f, &val); 2258 if (error == 0) 2259 mid->val_out = val; 2260 break; 2261 } 2262 case SIOCSMIIREG: { 2263 struct cphy *phy = &pi->phy; 2264 struct mii_data *mid = (struct mii_data *)data; 2265 2266 if (!phy->mdio_write) 2267 return (EOPNOTSUPP); 2268 if (is_10G(sc)) { 2269 mmd = mid->phy_id >> 8; 2270 if (!mmd) 2271 mmd = MDIO_DEV_PCS; 2272 else if (mmd > MDIO_DEV_XGXS) 2273 return (EINVAL); 2274 2275 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2276 mmd, mid->reg_num, mid->val_in); 2277 } else 2278 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2279 mid->reg_num & 0x1f, 2280 mid->val_in); 2281 break; 2282 } 2283 case CHELSIO_SETREG: { 2284 struct ch_reg *edata = (struct ch_reg *)data; 2285 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2286 return (EFAULT); 2287 t3_write_reg(sc, edata->addr, edata->val); 2288 break; 2289 } 2290 case CHELSIO_GETREG: { 2291 struct ch_reg *edata = (struct ch_reg *)data; 2292 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2293 return (EFAULT); 2294 edata->val = t3_read_reg(sc, edata->addr); 2295 break; 2296 } 2297 case CHELSIO_GET_SGE_CONTEXT: { 2298 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2299 mtx_lock_spin(&sc->sge.reg_lock); 2300 switch (ecntxt->cntxt_type) { 2301 case CNTXT_TYPE_EGRESS: 2302 error = t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2303 ecntxt->data); 2304 break; 2305 case CNTXT_TYPE_FL: 2306 error = t3_sge_read_fl(sc, ecntxt->cntxt_id, 2307 ecntxt->data); 2308 break; 2309 case CNTXT_TYPE_RSP: 2310 error = t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2311 ecntxt->data); 2312 break; 2313 case CNTXT_TYPE_CQ: 2314 error = t3_sge_read_cq(sc, ecntxt->cntxt_id, 2315 ecntxt->data); 2316 break; 2317 default: 2318 error = EINVAL; 2319 break; 2320 } 2321 mtx_unlock_spin(&sc->sge.reg_lock); 2322 break; 2323 } 2324 case CHELSIO_GET_SGE_DESC: { 2325 struct ch_desc *edesc = (struct ch_desc *)data; 2326 int ret; 2327 if (edesc->queue_num >= SGE_QSETS * 6) 2328 return (EINVAL); 2329 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2330 edesc->queue_num % 6, edesc->idx, edesc->data); 2331 if (ret < 0) 2332 return (EINVAL); 2333 edesc->size = ret; 2334 break; 2335 } 2336 case CHELSIO_SET_QSET_PARAMS: { 2337 struct qset_params *q; 2338 struct ch_qset_params *t = (struct ch_qset_params *)data; 2339 int i; 2340 2341 if (t->qset_idx >= SGE_QSETS) 2342 return (EINVAL); 2343 if (!in_range(t->intr_lat, 0, M_NEWTIMER) || 2344 !in_range(t->cong_thres, 0, 255) || 2345 !in_range(t->txq_size[0], MIN_TXQ_ENTRIES, 2346 MAX_TXQ_ENTRIES) || 2347 !in_range(t->txq_size[1], MIN_TXQ_ENTRIES, 2348 MAX_TXQ_ENTRIES) || 2349 !in_range(t->txq_size[2], MIN_CTRL_TXQ_ENTRIES, 2350 MAX_CTRL_TXQ_ENTRIES) || 2351 !in_range(t->fl_size[0], MIN_FL_ENTRIES, MAX_RX_BUFFERS) || 2352 !in_range(t->fl_size[1], MIN_FL_ENTRIES, 2353 MAX_RX_JUMBO_BUFFERS) || 2354 !in_range(t->rspq_size, MIN_RSPQ_ENTRIES, MAX_RSPQ_ENTRIES)) 2355 return (EINVAL); 2356 2357 if ((sc->flags & FULL_INIT_DONE) && t->lro > 0) 2358 for_each_port(sc, i) { 2359 pi = adap2pinfo(sc, i); 2360 if (t->qset_idx >= pi->first_qset && 2361 t->qset_idx < pi->first_qset + pi->nqsets 2362 #if 0 2363 && !pi->rx_csum_offload 2364 #endif 2365 ) 2366 return -EINVAL; 2367 } 2368 if ((sc->flags & FULL_INIT_DONE) && 2369 (t->rspq_size >= 0 || t->fl_size[0] >= 0 || 2370 t->fl_size[1] >= 0 || t->txq_size[0] >= 0 || 2371 t->txq_size[1] >= 0 || t->txq_size[2] >= 0 || 2372 t->polling >= 0 || t->cong_thres >= 0)) 2373 return (EBUSY); 2374 2375 q = &sc->params.sge.qset[t->qset_idx]; 2376 2377 if (t->rspq_size >= 0) 2378 q->rspq_size = t->rspq_size; 2379 if (t->fl_size[0] >= 0) 2380 q->fl_size = t->fl_size[0]; 2381 if (t->fl_size[1] >= 0) 2382 q->jumbo_size = t->fl_size[1]; 2383 if (t->txq_size[0] >= 0) 2384 q->txq_size[0] = t->txq_size[0]; 2385 if (t->txq_size[1] >= 0) 2386 q->txq_size[1] = t->txq_size[1]; 2387 if (t->txq_size[2] >= 0) 2388 q->txq_size[2] = t->txq_size[2]; 2389 if (t->cong_thres >= 0) 2390 q->cong_thres = t->cong_thres; 2391 if (t->intr_lat >= 0) { 2392 struct sge_qset *qs = &sc->sge.qs[t->qset_idx]; 2393 2394 q->coalesce_nsecs = t->intr_lat*1000; 2395 t3_update_qset_coalesce(qs, q); 2396 } 2397 break; 2398 } 2399 case CHELSIO_GET_QSET_PARAMS: { 2400 struct qset_params *q; 2401 struct ch_qset_params *t = (struct ch_qset_params *)data; 2402 2403 if (t->qset_idx >= SGE_QSETS) 2404 return (EINVAL); 2405 2406 q = &(sc)->params.sge.qset[t->qset_idx]; 2407 t->rspq_size = q->rspq_size; 2408 t->txq_size[0] = q->txq_size[0]; 2409 t->txq_size[1] = q->txq_size[1]; 2410 t->txq_size[2] = q->txq_size[2]; 2411 t->fl_size[0] = q->fl_size; 2412 t->fl_size[1] = q->jumbo_size; 2413 t->polling = q->polling; 2414 t->intr_lat = q->coalesce_nsecs / 1000; 2415 t->cong_thres = q->cong_thres; 2416 break; 2417 } 2418 case CHELSIO_SET_QSET_NUM: { 2419 struct ch_reg *edata = (struct ch_reg *)data; 2420 unsigned int port_idx = pi->port_id; 2421 2422 if (sc->flags & FULL_INIT_DONE) 2423 return (EBUSY); 2424 if (edata->val < 1 || 2425 (edata->val > 1 && !(sc->flags & USING_MSIX))) 2426 return (EINVAL); 2427 if (edata->val + sc->port[!port_idx].nqsets > SGE_QSETS) 2428 return (EINVAL); 2429 sc->port[port_idx].nqsets = edata->val; 2430 sc->port[0].first_qset = 0; 2431 /* 2432 * XXX hardcode ourselves to 2 ports just like LEEENUX 2433 */ 2434 sc->port[1].first_qset = sc->port[0].nqsets; 2435 break; 2436 } 2437 case CHELSIO_GET_QSET_NUM: { 2438 struct ch_reg *edata = (struct ch_reg *)data; 2439 edata->val = pi->nqsets; 2440 break; 2441 } 2442 #ifdef notyet 2443 case CHELSIO_LOAD_FW: 2444 case CHELSIO_GET_PM: 2445 case CHELSIO_SET_PM: 2446 return (EOPNOTSUPP); 2447 break; 2448 #endif 2449 case CHELSIO_SETMTUTAB: { 2450 struct ch_mtus *m = (struct ch_mtus *)data; 2451 int i; 2452 2453 if (!is_offload(sc)) 2454 return (EOPNOTSUPP); 2455 if (offload_running(sc)) 2456 return (EBUSY); 2457 if (m->nmtus != NMTUS) 2458 return (EINVAL); 2459 if (m->mtus[0] < 81) /* accommodate SACK */ 2460 return (EINVAL); 2461 2462 /* 2463 * MTUs must be in ascending order 2464 */ 2465 for (i = 1; i < NMTUS; ++i) 2466 if (m->mtus[i] < m->mtus[i - 1]) 2467 return (EINVAL); 2468 2469 memcpy(sc->params.mtus, m->mtus, 2470 sizeof(sc->params.mtus)); 2471 break; 2472 } 2473 case CHELSIO_GETMTUTAB: { 2474 struct ch_mtus *m = (struct ch_mtus *)data; 2475 2476 if (!is_offload(sc)) 2477 return (EOPNOTSUPP); 2478 2479 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2480 m->nmtus = NMTUS; 2481 break; 2482 } 2483 case CHELSIO_DEVUP: 2484 if (!is_offload(sc)) 2485 return (EOPNOTSUPP); 2486 return offload_open(pi); 2487 break; 2488 case CHELSIO_GET_MEM: { 2489 struct ch_mem_range *t = (struct ch_mem_range *)data; 2490 struct mc7 *mem; 2491 uint8_t *useraddr; 2492 u64 buf[32]; 2493 2494 if (!is_offload(sc)) 2495 return (EOPNOTSUPP); 2496 if (!(sc->flags & FULL_INIT_DONE)) 2497 return (EIO); /* need the memory controllers */ 2498 if ((t->addr & 0x7) || (t->len & 0x7)) 2499 return (EINVAL); 2500 if (t->mem_id == MEM_CM) 2501 mem = &sc->cm; 2502 else if (t->mem_id == MEM_PMRX) 2503 mem = &sc->pmrx; 2504 else if (t->mem_id == MEM_PMTX) 2505 mem = &sc->pmtx; 2506 else 2507 return (EINVAL); 2508 2509 /* 2510 * Version scheme: 2511 * bits 0..9: chip version 2512 * bits 10..15: chip revision 2513 */ 2514 t->version = 3 | (sc->params.rev << 10); 2515 2516 /* 2517 * Read 256 bytes at a time as len can be large and we don't 2518 * want to use huge intermediate buffers. 2519 */ 2520 useraddr = (uint8_t *)t->buf; 2521 while (t->len) { 2522 unsigned int chunk = min(t->len, sizeof(buf)); 2523 2524 error = t3_mc7_bd_read(mem, t->addr / 8, chunk / 8, buf); 2525 if (error) 2526 return (-error); 2527 if (copyout(buf, useraddr, chunk)) 2528 return (EFAULT); 2529 useraddr += chunk; 2530 t->addr += chunk; 2531 t->len -= chunk; 2532 } 2533 break; 2534 } 2535 case CHELSIO_READ_TCAM_WORD: { 2536 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2537 2538 if (!is_offload(sc)) 2539 return (EOPNOTSUPP); 2540 if (!(sc->flags & FULL_INIT_DONE)) 2541 return (EIO); /* need MC5 */ 2542 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2543 break; 2544 } 2545 case CHELSIO_SET_TRACE_FILTER: { 2546 struct ch_trace *t = (struct ch_trace *)data; 2547 const struct trace_params *tp; 2548 2549 tp = (const struct trace_params *)&t->sip; 2550 if (t->config_tx) 2551 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2552 t->trace_tx); 2553 if (t->config_rx) 2554 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2555 t->trace_rx); 2556 break; 2557 } 2558 case CHELSIO_SET_PKTSCHED: { 2559 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2560 if (sc->open_device_map == 0) 2561 return (EAGAIN); 2562 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2563 p->binding); 2564 break; 2565 } 2566 case CHELSIO_IFCONF_GETREGS: { 2567 struct ifconf_regs *regs = (struct ifconf_regs *)data; 2568 int reglen = cxgb_get_regs_len(); 2569 uint8_t *buf = malloc(REGDUMP_SIZE, M_DEVBUF, M_NOWAIT); 2570 if (buf == NULL) { 2571 return (ENOMEM); 2572 } if (regs->len > reglen) 2573 regs->len = reglen; 2574 else if (regs->len < reglen) { 2575 error = E2BIG; 2576 goto done; 2577 } 2578 cxgb_get_regs(sc, regs, buf); 2579 error = copyout(buf, regs->data, reglen); 2580 2581 done: 2582 free(buf, M_DEVBUF); 2583 2584 break; 2585 } 2586 case CHELSIO_SET_HW_SCHED: { 2587 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2588 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2589 2590 if ((sc->flags & FULL_INIT_DONE) == 0) 2591 return (EAGAIN); /* need TP to be initialized */ 2592 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2593 !in_range(t->channel, 0, 1) || 2594 !in_range(t->kbps, 0, 10000000) || 2595 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2596 !in_range(t->flow_ipg, 0, 2597 dack_ticks_to_usec(sc, 0x7ff))) 2598 return (EINVAL); 2599 2600 if (t->kbps >= 0) { 2601 error = t3_config_sched(sc, t->kbps, t->sched); 2602 if (error < 0) 2603 return (-error); 2604 } 2605 if (t->class_ipg >= 0) 2606 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2607 if (t->flow_ipg >= 0) { 2608 t->flow_ipg *= 1000; /* us -> ns */ 2609 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2610 } 2611 if (t->mode >= 0) { 2612 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2613 2614 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2615 bit, t->mode ? bit : 0); 2616 } 2617 if (t->channel >= 0) 2618 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2619 1 << t->sched, t->channel << t->sched); 2620 break; 2621 } 2622 default: 2623 return (EOPNOTSUPP); 2624 break; 2625 } 2626 2627 return (error); 2628 } 2629 2630 static __inline void 2631 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2632 unsigned int end) 2633 { 2634 uint32_t *p = (uint32_t *)buf + start; 2635 2636 for ( ; start <= end; start += sizeof(uint32_t)) 2637 *p++ = t3_read_reg(ap, start); 2638 } 2639 2640 #define T3_REGMAP_SIZE (3 * 1024) 2641 static int 2642 cxgb_get_regs_len(void) 2643 { 2644 return T3_REGMAP_SIZE; 2645 } 2646 #undef T3_REGMAP_SIZE 2647 2648 static void 2649 cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf) 2650 { 2651 2652 /* 2653 * Version scheme: 2654 * bits 0..9: chip version 2655 * bits 10..15: chip revision 2656 * bit 31: set for PCIe cards 2657 */ 2658 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2659 2660 /* 2661 * We skip the MAC statistics registers because they are clear-on-read. 2662 * Also reading multi-register stats would need to synchronize with the 2663 * periodic mac stats accumulation. Hard to justify the complexity. 2664 */ 2665 memset(buf, 0, REGDUMP_SIZE); 2666 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2667 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2668 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2669 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2670 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2671 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2672 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2673 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2674 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2675 } 2676 2677 2678 MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 2679