1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/pciio.h> 39 #include <sys/conf.h> 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/bus_dma.h> 43 #include <sys/rman.h> 44 #include <sys/ioccom.h> 45 #include <sys/mbuf.h> 46 #include <sys/linker.h> 47 #include <sys/firmware.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/smp.h> 51 #include <sys/sysctl.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in_systm.h> 64 #include <netinet/in.h> 65 #include <netinet/if_ether.h> 66 #include <netinet/ip.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pci_private.h> 74 75 #ifdef CONFIG_DEFINED 76 #include <cxgb_include.h> 77 #else 78 #include <dev/cxgb/cxgb_include.h> 79 #endif 80 81 #ifdef PRIV_SUPPORTED 82 #include <sys/priv.h> 83 #endif 84 85 static int cxgb_setup_msix(adapter_t *, int); 86 static void cxgb_teardown_msix(adapter_t *); 87 static void cxgb_init(void *); 88 static void cxgb_init_locked(struct port_info *); 89 static void cxgb_stop_locked(struct port_info *); 90 static void cxgb_set_rxmode(struct port_info *); 91 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 92 static void cxgb_start(struct ifnet *); 93 static void cxgb_start_proc(void *, int ncount); 94 static int cxgb_media_change(struct ifnet *); 95 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 96 static int setup_sge_qsets(adapter_t *); 97 static void cxgb_async_intr(void *); 98 static void cxgb_ext_intr_handler(void *, int); 99 static void cxgb_tick_handler(void *, int); 100 static void cxgb_down_locked(struct adapter *sc); 101 static void cxgb_tick(void *); 102 static void setup_rss(adapter_t *sc); 103 104 /* Attachment glue for the PCI controller end of the device. Each port of 105 * the device is attached separately, as defined later. 106 */ 107 static int cxgb_controller_probe(device_t); 108 static int cxgb_controller_attach(device_t); 109 static int cxgb_controller_detach(device_t); 110 static void cxgb_free(struct adapter *); 111 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 112 unsigned int end); 113 static void cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf); 114 static int cxgb_get_regs_len(void); 115 static int offload_open(struct port_info *pi); 116 #ifdef notyet 117 static int offload_close(struct toedev *tdev); 118 #endif 119 120 121 static device_method_t cxgb_controller_methods[] = { 122 DEVMETHOD(device_probe, cxgb_controller_probe), 123 DEVMETHOD(device_attach, cxgb_controller_attach), 124 DEVMETHOD(device_detach, cxgb_controller_detach), 125 126 /* bus interface */ 127 DEVMETHOD(bus_print_child, bus_generic_print_child), 128 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 129 130 { 0, 0 } 131 }; 132 133 static driver_t cxgb_controller_driver = { 134 "cxgbc", 135 cxgb_controller_methods, 136 sizeof(struct adapter) 137 }; 138 139 static devclass_t cxgb_controller_devclass; 140 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 141 142 /* 143 * Attachment glue for the ports. Attachment is done directly to the 144 * controller device. 145 */ 146 static int cxgb_port_probe(device_t); 147 static int cxgb_port_attach(device_t); 148 static int cxgb_port_detach(device_t); 149 150 static device_method_t cxgb_port_methods[] = { 151 DEVMETHOD(device_probe, cxgb_port_probe), 152 DEVMETHOD(device_attach, cxgb_port_attach), 153 DEVMETHOD(device_detach, cxgb_port_detach), 154 { 0, 0 } 155 }; 156 157 static driver_t cxgb_port_driver = { 158 "cxgb", 159 cxgb_port_methods, 160 0 161 }; 162 163 static d_ioctl_t cxgb_extension_ioctl; 164 static d_open_t cxgb_extension_open; 165 static d_close_t cxgb_extension_close; 166 167 static struct cdevsw cxgb_cdevsw = { 168 .d_version = D_VERSION, 169 .d_flags = 0, 170 .d_open = cxgb_extension_open, 171 .d_close = cxgb_extension_close, 172 .d_ioctl = cxgb_extension_ioctl, 173 .d_name = "cxgb", 174 }; 175 176 static devclass_t cxgb_port_devclass; 177 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 178 179 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 180 181 extern int collapse_mbufs; 182 /* 183 * The driver uses the best interrupt scheme available on a platform in the 184 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 185 * of these schemes the driver may consider as follows: 186 * 187 * msi = 2: choose from among all three options 188 * msi = 1 : only consider MSI and pin interrupts 189 * msi = 0: force pin interrupts 190 */ 191 static int msi_allowed = 2; 192 193 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 194 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 195 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 196 "MSI-X, MSI, INTx selector"); 197 198 /* 199 * The driver enables offload as a default. 200 * To disable it, use ofld_disable = 1. 201 */ 202 static int ofld_disable = 0; 203 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 204 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 205 "disable ULP offload"); 206 207 /* 208 * The driver uses an auto-queue algorithm by default. 209 * To disable it and force a single queue-set per port, use singleq = 1. 210 */ 211 static int singleq = 1; 212 TUNABLE_INT("hw.cxgb.singleq", &singleq); 213 SYSCTL_UINT(_hw_cxgb, OID_AUTO, singleq, CTLFLAG_RDTUN, &singleq, 0, 214 "use a single queue-set per port"); 215 216 enum { 217 MAX_TXQ_ENTRIES = 16384, 218 MAX_CTRL_TXQ_ENTRIES = 1024, 219 MAX_RSPQ_ENTRIES = 16384, 220 MAX_RX_BUFFERS = 16384, 221 MAX_RX_JUMBO_BUFFERS = 16384, 222 MIN_TXQ_ENTRIES = 4, 223 MIN_CTRL_TXQ_ENTRIES = 4, 224 MIN_RSPQ_ENTRIES = 32, 225 MIN_FL_ENTRIES = 32 226 }; 227 228 struct filter_info { 229 u32 sip; 230 u32 sip_mask; 231 u32 dip; 232 u16 sport; 233 u16 dport; 234 u32 vlan:12; 235 u32 vlan_prio:3; 236 u32 mac_hit:1; 237 u32 mac_idx:4; 238 u32 mac_vld:1; 239 u32 pkt_type:2; 240 u32 report_filter_id:1; 241 u32 pass:1; 242 u32 rss:1; 243 u32 qset:3; 244 u32 locked:1; 245 u32 valid:1; 246 }; 247 248 enum { FILTER_NO_VLAN_PRI = 7 }; 249 250 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 251 252 /* Table for probing the cards. The desc field isn't actually used */ 253 struct cxgb_ident { 254 uint16_t vendor; 255 uint16_t device; 256 int index; 257 char *desc; 258 } cxgb_identifiers[] = { 259 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 260 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 261 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 262 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 263 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 264 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 265 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 266 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 267 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 268 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 269 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 270 {0, 0, 0, NULL} 271 }; 272 273 274 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 275 276 static inline char 277 t3rev2char(struct adapter *adapter) 278 { 279 char rev = 'z'; 280 281 switch(adapter->params.rev) { 282 case T3_REV_A: 283 rev = 'a'; 284 break; 285 case T3_REV_B: 286 case T3_REV_B2: 287 rev = 'b'; 288 break; 289 case T3_REV_C: 290 rev = 'c'; 291 break; 292 } 293 return rev; 294 } 295 296 static struct cxgb_ident * 297 cxgb_get_ident(device_t dev) 298 { 299 struct cxgb_ident *id; 300 301 for (id = cxgb_identifiers; id->desc != NULL; id++) { 302 if ((id->vendor == pci_get_vendor(dev)) && 303 (id->device == pci_get_device(dev))) { 304 return (id); 305 } 306 } 307 return (NULL); 308 } 309 310 static const struct adapter_info * 311 cxgb_get_adapter_info(device_t dev) 312 { 313 struct cxgb_ident *id; 314 const struct adapter_info *ai; 315 316 id = cxgb_get_ident(dev); 317 if (id == NULL) 318 return (NULL); 319 320 ai = t3_get_adapter_info(id->index); 321 322 return (ai); 323 } 324 325 static int 326 cxgb_controller_probe(device_t dev) 327 { 328 const struct adapter_info *ai; 329 char *ports, buf[80]; 330 int nports; 331 332 ai = cxgb_get_adapter_info(dev); 333 if (ai == NULL) 334 return (ENXIO); 335 336 nports = ai->nports0 + ai->nports1; 337 if (nports == 1) 338 ports = "port"; 339 else 340 ports = "ports"; 341 342 snprintf(buf, sizeof(buf), "%s RNIC, %d %s", ai->desc, nports, ports); 343 device_set_desc_copy(dev, buf); 344 return (BUS_PROBE_DEFAULT); 345 } 346 347 #define FW_FNAME "t3fw%d%d%d" 348 #define TPEEPROM_NAME "t3%ctpe%d%d%d" 349 #define TPSRAM_NAME "t3%cps%d%d%d" 350 351 static int 352 upgrade_fw(adapter_t *sc) 353 { 354 char buf[32]; 355 #ifdef FIRMWARE_LATEST 356 const struct firmware *fw; 357 #else 358 struct firmware *fw; 359 #endif 360 int status; 361 362 snprintf(&buf[0], sizeof(buf), FW_FNAME, FW_VERSION_MAJOR, 363 FW_VERSION_MINOR, FW_VERSION_MICRO); 364 365 fw = firmware_get(buf); 366 367 if (fw == NULL) { 368 device_printf(sc->dev, "Could not find firmware image %s\n", buf); 369 return (ENOENT); 370 } else 371 device_printf(sc->dev, "updating firmware on card with %s\n", buf); 372 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 373 374 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 375 376 firmware_put(fw, FIRMWARE_UNLOAD); 377 378 return (status); 379 } 380 381 static int 382 cxgb_controller_attach(device_t dev) 383 { 384 device_t child; 385 const struct adapter_info *ai; 386 struct adapter *sc; 387 int i, reg, msi_needed, error = 0; 388 uint32_t vers; 389 int port_qsets = 1; 390 391 sc = device_get_softc(dev); 392 sc->dev = dev; 393 sc->msi_count = 0; 394 395 /* find the PCIe link width and set max read request to 4KB*/ 396 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 397 uint16_t lnk, pectl; 398 lnk = pci_read_config(dev, reg + 0x12, 2); 399 sc->link_width = (lnk >> 4) & 0x3f; 400 401 pectl = pci_read_config(dev, reg + 0x8, 2); 402 pectl = (pectl & ~0x7000) | (5 << 12); 403 pci_write_config(dev, reg + 0x8, pectl, 2); 404 } 405 406 ai = cxgb_get_adapter_info(dev); 407 if (sc->link_width != 0 && sc->link_width <= 4 && 408 (ai->nports0 + ai->nports1) <= 2) { 409 device_printf(sc->dev, 410 "PCIe x%d Link, expect reduced performance\n", 411 sc->link_width); 412 } 413 414 pci_enable_busmaster(dev); 415 /* 416 * Allocate the registers and make them available to the driver. 417 * The registers that we care about for NIC mode are in BAR 0 418 */ 419 sc->regs_rid = PCIR_BAR(0); 420 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 421 &sc->regs_rid, RF_ACTIVE)) == NULL) { 422 device_printf(dev, "Cannot allocate BAR\n"); 423 return (ENXIO); 424 } 425 426 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 427 device_get_unit(dev)); 428 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 429 430 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 431 device_get_unit(dev)); 432 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 433 device_get_unit(dev)); 434 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 435 device_get_unit(dev)); 436 437 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_DEF); 438 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 439 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 440 441 sc->bt = rman_get_bustag(sc->regs_res); 442 sc->bh = rman_get_bushandle(sc->regs_res); 443 sc->mmio_len = rman_get_size(sc->regs_res); 444 445 if (t3_prep_adapter(sc, ai, 1) < 0) { 446 printf("prep adapter failed\n"); 447 error = ENODEV; 448 goto out; 449 } 450 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 451 * enough messages for the queue sets. If that fails, try falling 452 * back to MSI. If that fails, then try falling back to the legacy 453 * interrupt pin model. 454 */ 455 #ifdef MSI_SUPPORTED 456 457 sc->msix_regs_rid = 0x20; 458 if ((msi_allowed >= 2) && 459 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 460 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 461 462 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 463 464 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 465 (sc->msi_count != msi_needed)) { 466 device_printf(dev, "msix allocation failed - msi_count = %d" 467 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 468 msi_needed, error); 469 sc->msi_count = 0; 470 pci_release_msi(dev); 471 bus_release_resource(dev, SYS_RES_MEMORY, 472 sc->msix_regs_rid, sc->msix_regs_res); 473 sc->msix_regs_res = NULL; 474 } else { 475 sc->flags |= USING_MSIX; 476 sc->cxgb_intr = t3_intr_msix; 477 } 478 } 479 480 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 481 sc->msi_count = 1; 482 if (pci_alloc_msi(dev, &sc->msi_count)) { 483 device_printf(dev, "alloc msi failed - will try INTx\n"); 484 sc->msi_count = 0; 485 pci_release_msi(dev); 486 } else { 487 sc->flags |= USING_MSI; 488 sc->irq_rid = 1; 489 sc->cxgb_intr = t3_intr_msi; 490 } 491 } 492 #endif 493 if (sc->msi_count == 0) { 494 device_printf(dev, "using line interrupts\n"); 495 sc->irq_rid = 0; 496 sc->cxgb_intr = t3b_intr; 497 } 498 499 500 /* Create a private taskqueue thread for handling driver events */ 501 #ifdef TASKQUEUE_CURRENT 502 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 503 taskqueue_thread_enqueue, &sc->tq); 504 #else 505 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 506 taskqueue_thread_enqueue, &sc->tq); 507 #endif 508 if (sc->tq == NULL) { 509 device_printf(dev, "failed to allocate controller task queue\n"); 510 goto out; 511 } 512 513 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 514 device_get_nameunit(dev)); 515 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 516 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 517 518 519 /* Create a periodic callout for checking adapter status */ 520 callout_init(&sc->cxgb_tick_ch, TRUE); 521 522 if (t3_check_fw_version(sc) != 0) { 523 /* 524 * Warn user that a firmware update will be attempted in init. 525 */ 526 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 527 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 528 sc->flags &= ~FW_UPTODATE; 529 } else { 530 sc->flags |= FW_UPTODATE; 531 } 532 533 if (t3_check_tpsram_version(sc) != 0) { 534 /* 535 * Warn user that a firmware update will be attempted in init. 536 */ 537 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 538 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 539 sc->flags &= ~TPS_UPTODATE; 540 } else { 541 sc->flags |= TPS_UPTODATE; 542 } 543 544 if ((sc->flags & USING_MSIX) && !singleq) 545 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 546 547 /* 548 * Create a child device for each MAC. The ethernet attachment 549 * will be done in these children. 550 */ 551 for (i = 0; i < (sc)->params.nports; i++) { 552 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 553 device_printf(dev, "failed to add child port\n"); 554 error = EINVAL; 555 goto out; 556 } 557 sc->port[i].adapter = sc; 558 sc->port[i].nqsets = port_qsets; 559 sc->port[i].first_qset = i*port_qsets; 560 sc->port[i].port = i; 561 sc->portdev[i] = child; 562 device_set_softc(child, &sc->port[i]); 563 } 564 if ((error = bus_generic_attach(dev)) != 0) 565 goto out; 566 567 /* 568 * XXX need to poll for link status 569 */ 570 sc->params.stats_update_period = 1; 571 572 /* initialize sge private state */ 573 t3_sge_init_adapter(sc); 574 575 t3_led_ready(sc); 576 577 cxgb_offload_init(); 578 if (is_offload(sc)) { 579 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 580 cxgb_adapter_ofld(sc); 581 } 582 error = t3_get_fw_version(sc, &vers); 583 if (error) 584 goto out; 585 586 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 587 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 588 G_FW_VERSION_MICRO(vers)); 589 590 t3_add_sysctls(sc); 591 out: 592 if (error) 593 cxgb_free(sc); 594 595 return (error); 596 } 597 598 static int 599 cxgb_controller_detach(device_t dev) 600 { 601 struct adapter *sc; 602 603 sc = device_get_softc(dev); 604 605 cxgb_free(sc); 606 607 return (0); 608 } 609 610 static void 611 cxgb_free(struct adapter *sc) 612 { 613 int i; 614 615 ADAPTER_LOCK(sc); 616 /* 617 * drops the lock 618 */ 619 cxgb_down_locked(sc); 620 621 #ifdef MSI_SUPPORTED 622 if (sc->flags & (USING_MSI | USING_MSIX)) { 623 device_printf(sc->dev, "releasing msi message(s)\n"); 624 pci_release_msi(sc->dev); 625 } else { 626 device_printf(sc->dev, "no msi message to release\n"); 627 } 628 #endif 629 if (sc->msix_regs_res != NULL) { 630 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 631 sc->msix_regs_res); 632 } 633 634 t3_sge_deinit_sw(sc); 635 636 if (sc->tq != NULL) { 637 taskqueue_drain(sc->tq, &sc->ext_intr_task); 638 taskqueue_drain(sc->tq, &sc->tick_task); 639 taskqueue_free(sc->tq); 640 } 641 642 tsleep(&sc, 0, "cxgb unload", hz); 643 644 for (i = 0; i < (sc)->params.nports; ++i) { 645 if (sc->portdev[i] != NULL) 646 device_delete_child(sc->dev, sc->portdev[i]); 647 } 648 649 bus_generic_detach(sc->dev); 650 #ifdef notyet 651 if (is_offload(sc)) { 652 cxgb_adapter_unofld(sc); 653 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 654 offload_close(&sc->tdev); 655 } 656 #endif 657 t3_free_sge_resources(sc); 658 free(sc->filters, M_DEVBUF); 659 t3_sge_free(sc); 660 661 cxgb_offload_exit(); 662 663 if (sc->regs_res != NULL) 664 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 665 sc->regs_res); 666 667 MTX_DESTROY(&sc->mdio_lock); 668 MTX_DESTROY(&sc->sge.reg_lock); 669 MTX_DESTROY(&sc->elmer_lock); 670 ADAPTER_LOCK_DEINIT(sc); 671 672 return; 673 } 674 675 676 677 static int 678 alloc_filters(struct adapter *adap) 679 { 680 struct filter_info *p; 681 int nfilters; 682 683 if ((nfilters = adap->params.mc5.nfilters) == 0) 684 return (0); 685 686 adap->filters = malloc(nfilters*sizeof(struct filter_info), 687 M_DEVBUF, M_ZERO|M_WAITOK); 688 689 if (adap->filters == NULL) 690 return (ENOMEM); 691 692 /* Set the default filters, only need to set non-0 fields here. */ 693 p = &adap->filters[nfilters - 1]; 694 p->vlan = 0xfff; 695 p->vlan_prio = FILTER_NO_VLAN_PRI; 696 p->pass = p->rss = p->valid = p->locked = 1; 697 698 return (0); 699 } 700 701 static inline void 702 set_tcb_field_ulp(struct cpl_set_tcb_field *req, 703 unsigned int tid, unsigned int word, 704 uint64_t mask, uint64_t val) 705 { 706 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req; 707 708 txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT)); 709 txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*req) / 8)); 710 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid)); 711 req->reply = V_NO_REPLY(1); 712 req->cpu_idx = 0; 713 req->word = htons(word); 714 req->mask = htobe64(mask); 715 req->val = htobe64(val); 716 } 717 718 static int 719 set_filter(struct adapter *adap, int id, const struct filter_info *f) 720 { 721 int len; 722 struct mbuf *m; 723 struct ulp_txpkt *txpkt; 724 struct work_request_hdr *wr; 725 struct cpl_pass_open_req *oreq; 726 struct cpl_set_tcb_field *sreq; 727 728 len = sizeof(*wr) + sizeof(*oreq) + 2 * sizeof(*sreq); 729 id += t3_mc5_size(&adap->mc5) - adap->params.mc5.nroutes - 730 adap->params.mc5.nfilters; 731 732 m = m_gethdr(M_TRYWAIT, MT_DATA); 733 wr = mtod(m, struct work_request_hdr *); 734 wr->wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS) | F_WR_ATOMIC); 735 m->m_len = m->m_pkthdr.len = len; 736 737 oreq = (struct cpl_pass_open_req *)(wr + 1); 738 txpkt = (struct ulp_txpkt *)oreq; 739 txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT)); 740 txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*oreq) / 8)); 741 OPCODE_TID(oreq) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, id)); 742 oreq->local_port = htons(f->dport); 743 oreq->peer_port = htons(f->sport); 744 oreq->local_ip = htonl(f->dip); 745 oreq->peer_ip = htonl(f->sip); 746 oreq->peer_netmask = htonl(f->sip_mask); 747 oreq->opt0h = 0; 748 oreq->opt0l = htonl(F_NO_OFFLOAD); 749 oreq->opt1 = htonl(V_MAC_MATCH_VALID(f->mac_vld) | 750 V_CONN_POLICY(CPL_CONN_POLICY_FILTER) | 751 V_VLAN_PRI(f->vlan_prio >> 1) | 752 V_VLAN_PRI_VALID(f->vlan_prio != FILTER_NO_VLAN_PRI) | 753 V_PKT_TYPE(f->pkt_type) | V_OPT1_VLAN(f->vlan) | 754 V_MAC_MATCH(f->mac_idx | (f->mac_hit << 4))); 755 756 sreq = (struct cpl_set_tcb_field *)(oreq + 1); 757 set_tcb_field_ulp(sreq, id, 1, 0x1800808000ULL, 758 (f->report_filter_id << 15) | (1 << 23) | 759 ((u64)f->pass << 35) | ((u64)!f->rss << 36)); 760 set_tcb_field_ulp(sreq + 1, id, 25, 0x3f80000, 761 (u64)adap->rrss_map[f->qset] << 19); 762 t3_mgmt_tx(adap, m); 763 return 0; 764 } 765 766 static int 767 setup_hw_filters(struct adapter *adap) 768 { 769 int i, err; 770 771 if (adap->filters == NULL) 772 return 0; 773 774 t3_enable_filters(adap); 775 776 for (i = err = 0; i < adap->params.mc5.nfilters && !err; i++) 777 if (adap->filters[i].locked) 778 err = set_filter(adap, i, &adap->filters[i]); 779 return err; 780 } 781 782 /** 783 * setup_sge_qsets - configure SGE Tx/Rx/response queues 784 * @sc: the controller softc 785 * 786 * Determines how many sets of SGE queues to use and initializes them. 787 * We support multiple queue sets per port if we have MSI-X, otherwise 788 * just one queue set per port. 789 */ 790 static int 791 setup_sge_qsets(adapter_t *sc) 792 { 793 int i, j, err, irq_idx, qset_idx; 794 u_int ntxq = SGE_TXQ_PER_SET; 795 796 if ((err = t3_sge_alloc(sc)) != 0) { 797 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 798 return (err); 799 } 800 801 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 802 irq_idx = -1; 803 else 804 irq_idx = 0; 805 806 for (qset_idx = 0, i = 0; i < (sc)->params.nports; ++i) { 807 struct port_info *pi = &sc->port[i]; 808 809 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) { 810 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 811 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 812 &sc->params.sge.qset[qset_idx], ntxq, pi); 813 if (err) { 814 t3_free_sge_resources(sc); 815 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", err); 816 return (err); 817 } 818 } 819 } 820 821 return (0); 822 } 823 824 static void 825 cxgb_teardown_msix(adapter_t *sc) 826 { 827 int i, nqsets; 828 829 for (nqsets = i = 0; i < (sc)->params.nports; i++) 830 nqsets += sc->port[i].nqsets; 831 832 for (i = 0; i < nqsets; i++) { 833 if (sc->msix_intr_tag[i] != NULL) { 834 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 835 sc->msix_intr_tag[i]); 836 sc->msix_intr_tag[i] = NULL; 837 } 838 if (sc->msix_irq_res[i] != NULL) { 839 bus_release_resource(sc->dev, SYS_RES_IRQ, 840 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 841 sc->msix_irq_res[i] = NULL; 842 } 843 } 844 } 845 846 static int 847 cxgb_setup_msix(adapter_t *sc, int msix_count) 848 { 849 int i, j, k, nqsets, rid; 850 851 /* The first message indicates link changes and error conditions */ 852 sc->irq_rid = 1; 853 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 854 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 855 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 856 return (EINVAL); 857 } 858 859 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 860 #ifdef INTR_FILTERS 861 NULL, 862 #endif 863 cxgb_async_intr, sc, &sc->intr_tag)) { 864 device_printf(sc->dev, "Cannot set up interrupt\n"); 865 return (EINVAL); 866 } 867 for (i = k = 0; i < (sc)->params.nports; i++) { 868 nqsets = sc->port[i].nqsets; 869 for (j = 0; j < nqsets; j++, k++) { 870 struct sge_qset *qs = &sc->sge.qs[k]; 871 872 rid = k + 2; 873 if (cxgb_debug) 874 printf("rid=%d ", rid); 875 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 876 sc->dev, SYS_RES_IRQ, &rid, 877 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 878 device_printf(sc->dev, "Cannot allocate " 879 "interrupt for message %d\n", rid); 880 return (EINVAL); 881 } 882 sc->msix_irq_rid[k] = rid; 883 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 884 INTR_MPSAFE|INTR_TYPE_NET, 885 #ifdef INTR_FILTERS 886 NULL, 887 #endif 888 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 889 device_printf(sc->dev, "Cannot set up " 890 "interrupt for message %d\n", rid); 891 return (EINVAL); 892 } 893 } 894 } 895 896 897 return (0); 898 } 899 900 static int 901 cxgb_port_probe(device_t dev) 902 { 903 struct port_info *p; 904 char buf[80]; 905 906 p = device_get_softc(dev); 907 908 snprintf(buf, sizeof(buf), "Port %d %s", p->port, p->port_type->desc); 909 device_set_desc_copy(dev, buf); 910 return (0); 911 } 912 913 914 static int 915 cxgb_makedev(struct port_info *pi) 916 { 917 918 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 919 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 920 921 if (pi->port_cdev == NULL) 922 return (ENOMEM); 923 924 pi->port_cdev->si_drv1 = (void *)pi; 925 926 return (0); 927 } 928 929 930 #ifdef TSO_SUPPORTED 931 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU) 932 /* Don't enable TSO6 yet */ 933 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU) 934 #else 935 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 936 /* Don't enable TSO6 yet */ 937 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 938 #define IFCAP_TSO4 0x0 939 #define CSUM_TSO 0x0 940 #endif 941 942 943 static int 944 cxgb_port_attach(device_t dev) 945 { 946 struct port_info *p; 947 struct ifnet *ifp; 948 int err, media_flags; 949 950 p = device_get_softc(dev); 951 952 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 953 device_get_unit(device_get_parent(dev)), p->port); 954 PORT_LOCK_INIT(p, p->lockbuf); 955 956 /* Allocate an ifnet object and set it up */ 957 ifp = p->ifp = if_alloc(IFT_ETHER); 958 if (ifp == NULL) { 959 device_printf(dev, "Cannot allocate ifnet\n"); 960 return (ENOMEM); 961 } 962 963 /* 964 * Note that there is currently no watchdog timer. 965 */ 966 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 967 ifp->if_init = cxgb_init; 968 ifp->if_softc = p; 969 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 970 ifp->if_ioctl = cxgb_ioctl; 971 ifp->if_start = cxgb_start; 972 ifp->if_timer = 0; /* Disable ifnet watchdog */ 973 ifp->if_watchdog = NULL; 974 975 ifp->if_snd.ifq_drv_maxlen = TX_ETH_Q_SIZE; 976 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 977 IFQ_SET_READY(&ifp->if_snd); 978 979 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 980 ifp->if_capabilities |= CXGB_CAP; 981 ifp->if_capenable |= CXGB_CAP_ENABLE; 982 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 983 /* 984 * disable TSO on 4-port - it isn't supported by the firmware yet 985 */ 986 if (p->adapter->params.nports > 2) { 987 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 988 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 989 ifp->if_hwassist &= ~CSUM_TSO; 990 } 991 992 ether_ifattach(ifp, p->hw_addr); 993 /* 994 * Only default to jumbo frames on 10GigE 995 */ 996 if (p->adapter->params.nports <= 2) 997 ifp->if_mtu = 9000; 998 if ((err = cxgb_makedev(p)) != 0) { 999 printf("makedev failed %d\n", err); 1000 return (err); 1001 } 1002 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 1003 cxgb_media_status); 1004 1005 if (!strcmp(p->port_type->desc, "10GBASE-CX4")) { 1006 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 1007 } else if (!strcmp(p->port_type->desc, "10GBASE-SR")) { 1008 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 1009 } else if (!strcmp(p->port_type->desc, "10GBASE-XR")) { 1010 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 1011 } else if (!strcmp(p->port_type->desc, "10/100/1000BASE-T")) { 1012 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 1013 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1014 0, NULL); 1015 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 1016 0, NULL); 1017 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1018 0, NULL); 1019 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1020 0, NULL); 1021 media_flags = 0; 1022 } else { 1023 printf("unsupported media type %s\n", p->port_type->desc); 1024 return (ENXIO); 1025 } 1026 if (media_flags) { 1027 ifmedia_add(&p->media, media_flags, 0, NULL); 1028 ifmedia_set(&p->media, media_flags); 1029 } else { 1030 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1031 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1032 } 1033 1034 1035 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port); 1036 #ifdef TASKQUEUE_CURRENT 1037 /* Create a port for handling TX without starvation */ 1038 p->tq = taskqueue_create(p->taskqbuf, M_NOWAIT, 1039 taskqueue_thread_enqueue, &p->tq); 1040 #else 1041 /* Create a port for handling TX without starvation */ 1042 p->tq = taskqueue_create_fast(buf, M_NOWAIT, 1043 taskqueue_thread_enqueue, &p->tq); 1044 #endif 1045 1046 if (p->tq == NULL) { 1047 device_printf(dev, "failed to allocate port task queue\n"); 1048 return (ENOMEM); 1049 } 1050 taskqueue_start_threads(&p->tq, 1, PI_NET, "%s taskq", 1051 device_get_nameunit(dev)); 1052 TASK_INIT(&p->start_task, 0, cxgb_start_proc, ifp); 1053 1054 t3_sge_init_port(p); 1055 1056 return (0); 1057 } 1058 1059 static int 1060 cxgb_port_detach(device_t dev) 1061 { 1062 struct port_info *p; 1063 1064 p = device_get_softc(dev); 1065 1066 PORT_LOCK(p); 1067 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1068 cxgb_stop_locked(p); 1069 PORT_UNLOCK(p); 1070 1071 if (p->tq != NULL) { 1072 taskqueue_drain(p->tq, &p->start_task); 1073 taskqueue_free(p->tq); 1074 p->tq = NULL; 1075 } 1076 1077 PORT_LOCK_DEINIT(p); 1078 ether_ifdetach(p->ifp); 1079 if_free(p->ifp); 1080 1081 if (p->port_cdev != NULL) 1082 destroy_dev(p->port_cdev); 1083 1084 return (0); 1085 } 1086 1087 void 1088 t3_fatal_err(struct adapter *sc) 1089 { 1090 u_int fw_status[4]; 1091 1092 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1093 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1094 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1095 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1096 } 1097 1098 int 1099 t3_os_find_pci_capability(adapter_t *sc, int cap) 1100 { 1101 device_t dev; 1102 struct pci_devinfo *dinfo; 1103 pcicfgregs *cfg; 1104 uint32_t status; 1105 uint8_t ptr; 1106 1107 dev = sc->dev; 1108 dinfo = device_get_ivars(dev); 1109 cfg = &dinfo->cfg; 1110 1111 status = pci_read_config(dev, PCIR_STATUS, 2); 1112 if (!(status & PCIM_STATUS_CAPPRESENT)) 1113 return (0); 1114 1115 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1116 case 0: 1117 case 1: 1118 ptr = PCIR_CAP_PTR; 1119 break; 1120 case 2: 1121 ptr = PCIR_CAP_PTR_2; 1122 break; 1123 default: 1124 return (0); 1125 break; 1126 } 1127 ptr = pci_read_config(dev, ptr, 1); 1128 1129 while (ptr != 0) { 1130 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1131 return (ptr); 1132 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1133 } 1134 1135 return (0); 1136 } 1137 1138 int 1139 t3_os_pci_save_state(struct adapter *sc) 1140 { 1141 device_t dev; 1142 struct pci_devinfo *dinfo; 1143 1144 dev = sc->dev; 1145 dinfo = device_get_ivars(dev); 1146 1147 pci_cfg_save(dev, dinfo, 0); 1148 return (0); 1149 } 1150 1151 int 1152 t3_os_pci_restore_state(struct adapter *sc) 1153 { 1154 device_t dev; 1155 struct pci_devinfo *dinfo; 1156 1157 dev = sc->dev; 1158 dinfo = device_get_ivars(dev); 1159 1160 pci_cfg_restore(dev, dinfo); 1161 return (0); 1162 } 1163 1164 /** 1165 * t3_os_link_changed - handle link status changes 1166 * @adapter: the adapter associated with the link change 1167 * @port_id: the port index whose limk status has changed 1168 * @link_stat: the new status of the link 1169 * @speed: the new speed setting 1170 * @duplex: the new duplex setting 1171 * @fc: the new flow-control setting 1172 * 1173 * This is the OS-dependent handler for link status changes. The OS 1174 * neutral handler takes care of most of the processing for these events, 1175 * then calls this handler for any OS-specific processing. 1176 */ 1177 void 1178 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1179 int duplex, int fc) 1180 { 1181 struct port_info *pi = &adapter->port[port_id]; 1182 struct cmac *mac = &adapter->port[port_id].mac; 1183 1184 if ((pi->ifp->if_flags & IFF_UP) == 0) 1185 return; 1186 1187 if (link_status) { 1188 t3_mac_enable(mac, MAC_DIRECTION_RX); 1189 if_link_state_change(pi->ifp, LINK_STATE_UP); 1190 } else { 1191 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1192 pi->phy.ops->power_down(&pi->phy, 1); 1193 t3_mac_disable(mac, MAC_DIRECTION_RX); 1194 t3_link_start(&pi->phy, mac, &pi->link_config); 1195 } 1196 } 1197 1198 1199 /* 1200 * Interrupt-context handler for external (PHY) interrupts. 1201 */ 1202 void 1203 t3_os_ext_intr_handler(adapter_t *sc) 1204 { 1205 if (cxgb_debug) 1206 printf("t3_os_ext_intr_handler\n"); 1207 /* 1208 * Schedule a task to handle external interrupts as they may be slow 1209 * and we use a mutex to protect MDIO registers. We disable PHY 1210 * interrupts in the meantime and let the task reenable them when 1211 * it's done. 1212 */ 1213 ADAPTER_LOCK(sc); 1214 if (sc->slow_intr_mask) { 1215 sc->slow_intr_mask &= ~F_T3DBG; 1216 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1217 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1218 } 1219 ADAPTER_UNLOCK(sc); 1220 } 1221 1222 void 1223 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1224 { 1225 1226 /* 1227 * The ifnet might not be allocated before this gets called, 1228 * as this is called early on in attach by t3_prep_adapter 1229 * save the address off in the port structure 1230 */ 1231 if (cxgb_debug) 1232 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1233 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1234 } 1235 1236 /** 1237 * link_start - enable a port 1238 * @p: the port to enable 1239 * 1240 * Performs the MAC and PHY actions needed to enable a port. 1241 */ 1242 static void 1243 cxgb_link_start(struct port_info *p) 1244 { 1245 struct ifnet *ifp; 1246 struct t3_rx_mode rm; 1247 struct cmac *mac = &p->mac; 1248 1249 ifp = p->ifp; 1250 1251 t3_init_rx_mode(&rm, p); 1252 t3_mac_reset(mac); 1253 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1254 t3_mac_set_address(mac, 0, p->hw_addr); 1255 t3_mac_set_rx_mode(mac, &rm); 1256 t3_link_start(&p->phy, mac, &p->link_config); 1257 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1258 } 1259 1260 /** 1261 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1262 * @adap: the adapter 1263 * 1264 * Sets up RSS to distribute packets to multiple receive queues. We 1265 * configure the RSS CPU lookup table to distribute to the number of HW 1266 * receive queues, and the response queue lookup table to narrow that 1267 * down to the response queues actually configured for each port. 1268 * We always configure the RSS mapping for two ports since the mapping 1269 * table has plenty of entries. 1270 */ 1271 static void 1272 setup_rss(adapter_t *adap) 1273 { 1274 int i; 1275 u_int nq[2]; 1276 uint8_t cpus[SGE_QSETS + 1]; 1277 uint16_t rspq_map[RSS_TABLE_SIZE]; 1278 1279 nq[0] = adap->port[0].nqsets; 1280 nq[1] = max((u_int)adap->port[1].nqsets, 1U); 1281 1282 for (i = 0; i < SGE_QSETS; ++i) 1283 cpus[i] = i; 1284 cpus[SGE_QSETS] = 0xff; 1285 1286 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1287 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1288 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1289 } 1290 /* Calculate the reverse RSS map table */ 1291 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1292 if (adap->rrss_map[rspq_map[i]] == 0xff) 1293 adap->rrss_map[rspq_map[i]] = i; 1294 1295 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1296 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1297 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6), cpus, rspq_map); 1298 1299 } 1300 1301 /* 1302 * Sends an mbuf to an offload queue driver 1303 * after dealing with any active network taps. 1304 */ 1305 static inline int 1306 offload_tx(struct toedev *tdev, struct mbuf *m) 1307 { 1308 int ret; 1309 1310 critical_enter(); 1311 ret = t3_offload_tx(tdev, m); 1312 critical_exit(); 1313 return (ret); 1314 } 1315 1316 static int 1317 write_smt_entry(struct adapter *adapter, int idx) 1318 { 1319 struct port_info *pi = &adapter->port[idx]; 1320 struct cpl_smt_write_req *req; 1321 struct mbuf *m; 1322 1323 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1324 return (ENOMEM); 1325 1326 req = mtod(m, struct cpl_smt_write_req *); 1327 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1328 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1329 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1330 req->iff = idx; 1331 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1332 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1333 1334 m_set_priority(m, 1); 1335 1336 offload_tx(&adapter->tdev, m); 1337 1338 return (0); 1339 } 1340 1341 static int 1342 init_smt(struct adapter *adapter) 1343 { 1344 int i; 1345 1346 for_each_port(adapter, i) 1347 write_smt_entry(adapter, i); 1348 return 0; 1349 } 1350 1351 static void 1352 init_port_mtus(adapter_t *adapter) 1353 { 1354 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1355 1356 if (adapter->port[1].ifp) 1357 mtus |= adapter->port[1].ifp->if_mtu << 16; 1358 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1359 } 1360 1361 static void 1362 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1363 int hi, int port) 1364 { 1365 struct mbuf *m; 1366 struct mngt_pktsched_wr *req; 1367 1368 m = m_gethdr(M_DONTWAIT, MT_DATA); 1369 if (m) { 1370 req = mtod(m, struct mngt_pktsched_wr *); 1371 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1372 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1373 req->sched = sched; 1374 req->idx = qidx; 1375 req->min = lo; 1376 req->max = hi; 1377 req->binding = port; 1378 m->m_len = m->m_pkthdr.len = sizeof(*req); 1379 t3_mgmt_tx(adap, m); 1380 } 1381 } 1382 1383 static void 1384 bind_qsets(adapter_t *sc) 1385 { 1386 int i, j; 1387 1388 for (i = 0; i < (sc)->params.nports; ++i) { 1389 const struct port_info *pi = adap2pinfo(sc, i); 1390 1391 for (j = 0; j < pi->nqsets; ++j) 1392 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1393 -1, i); 1394 } 1395 } 1396 1397 static void 1398 update_tpeeprom(struct adapter *adap) 1399 { 1400 const struct firmware *tpeeprom; 1401 char buf[64]; 1402 uint32_t version; 1403 unsigned int major, minor; 1404 int ret, len; 1405 char rev; 1406 1407 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1408 1409 major = G_TP_VERSION_MAJOR(version); 1410 minor = G_TP_VERSION_MINOR(version); 1411 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1412 return; 1413 1414 rev = t3rev2char(adap); 1415 1416 snprintf(buf, sizeof(buf), TPEEPROM_NAME, rev, 1417 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1418 1419 tpeeprom = firmware_get(buf); 1420 if (tpeeprom == NULL) { 1421 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1422 buf); 1423 return; 1424 } 1425 1426 len = tpeeprom->datasize - 4; 1427 1428 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1429 if (ret) 1430 goto release_tpeeprom; 1431 1432 if (len != TP_SRAM_LEN) { 1433 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", buf, len, TP_SRAM_LEN); 1434 return; 1435 } 1436 1437 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1438 TP_SRAM_OFFSET); 1439 1440 if (!ret) { 1441 device_printf(adap->dev, 1442 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1443 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1444 } else 1445 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1446 1447 release_tpeeprom: 1448 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1449 1450 return; 1451 } 1452 1453 static int 1454 update_tpsram(struct adapter *adap) 1455 { 1456 const struct firmware *tpsram; 1457 char buf[64]; 1458 int ret; 1459 char rev; 1460 1461 rev = t3rev2char(adap); 1462 if (!rev) 1463 return 0; 1464 1465 update_tpeeprom(adap); 1466 1467 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev, 1468 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1469 1470 tpsram = firmware_get(buf); 1471 if (tpsram == NULL){ 1472 device_printf(adap->dev, "could not load TP SRAM: unable to load %s\n", 1473 buf); 1474 return (EINVAL); 1475 } else 1476 device_printf(adap->dev, "updating TP SRAM with %s\n", buf); 1477 1478 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1479 if (ret) 1480 goto release_tpsram; 1481 1482 ret = t3_set_proto_sram(adap, tpsram->data); 1483 if (ret) 1484 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1485 1486 release_tpsram: 1487 firmware_put(tpsram, FIRMWARE_UNLOAD); 1488 1489 return ret; 1490 } 1491 1492 /** 1493 * cxgb_up - enable the adapter 1494 * @adap: adapter being enabled 1495 * 1496 * Called when the first port is enabled, this function performs the 1497 * actions necessary to make an adapter operational, such as completing 1498 * the initialization of HW modules, and enabling interrupts. 1499 * 1500 */ 1501 static int 1502 cxgb_up(struct adapter *sc) 1503 { 1504 int err = 0; 1505 1506 if ((sc->flags & FULL_INIT_DONE) == 0) { 1507 1508 if ((sc->flags & FW_UPTODATE) == 0) 1509 if ((err = upgrade_fw(sc))) 1510 goto out; 1511 if ((sc->flags & TPS_UPTODATE) == 0) 1512 if ((err = update_tpsram(sc))) 1513 goto out; 1514 err = t3_init_hw(sc, 0); 1515 if (err) 1516 goto out; 1517 1518 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1519 1520 err = setup_sge_qsets(sc); 1521 if (err) 1522 goto out; 1523 1524 alloc_filters(sc); 1525 setup_rss(sc); 1526 sc->flags |= FULL_INIT_DONE; 1527 } 1528 1529 t3_intr_clear(sc); 1530 1531 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1532 if ((sc->flags & USING_MSIX) == 0) { 1533 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1534 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1535 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", sc->irq_rid); 1536 err = EINVAL; 1537 goto out; 1538 } 1539 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1540 1541 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1542 #ifdef INTR_FILTERS 1543 NULL, 1544 #endif 1545 sc->cxgb_intr, sc, &sc->intr_tag)) { 1546 device_printf(sc->dev, "Cannot set up interrupt\n"); 1547 err = EINVAL; 1548 goto irq_err; 1549 } 1550 } else { 1551 cxgb_setup_msix(sc, sc->msi_count); 1552 } 1553 1554 t3_sge_start(sc); 1555 t3_intr_enable(sc); 1556 1557 if ((sc->flags & (USING_MSIX | QUEUES_BOUND)) == USING_MSIX) { 1558 bind_qsets(sc); 1559 setup_hw_filters(sc); 1560 sc->flags |= QUEUES_BOUND; 1561 } 1562 out: 1563 return (err); 1564 irq_err: 1565 CH_ERR(sc, "request_irq failed, err %d\n", err); 1566 goto out; 1567 } 1568 1569 1570 /* 1571 * Release resources when all the ports and offloading have been stopped. 1572 */ 1573 static void 1574 cxgb_down_locked(struct adapter *sc) 1575 { 1576 int i; 1577 1578 t3_sge_stop(sc); 1579 t3_intr_disable(sc); 1580 1581 if (sc->intr_tag != NULL) { 1582 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1583 sc->intr_tag = NULL; 1584 } 1585 if (sc->irq_res != NULL) { 1586 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1587 sc->irq_rid, sc->irq_res); 1588 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1589 sc->irq_res); 1590 sc->irq_res = NULL; 1591 } 1592 1593 if (sc->flags & USING_MSIX) 1594 cxgb_teardown_msix(sc); 1595 ADAPTER_UNLOCK(sc); 1596 1597 callout_drain(&sc->cxgb_tick_ch); 1598 callout_drain(&sc->sge_timer_ch); 1599 1600 if (sc->tq != NULL) 1601 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1602 for (i = 0; i < sc->params.nports; i++) 1603 if (sc->port[i].tq != NULL) 1604 taskqueue_drain(sc->port[i].tq, &sc->port[i].timer_reclaim_task); 1605 1606 } 1607 1608 static int 1609 offload_open(struct port_info *pi) 1610 { 1611 struct adapter *adapter = pi->adapter; 1612 struct toedev *tdev = TOEDEV(pi->ifp); 1613 int adap_up = adapter->open_device_map & PORT_MASK; 1614 int err = 0; 1615 1616 if (atomic_cmpset_int(&adapter->open_device_map, 1617 (adapter->open_device_map & ~OFFLOAD_DEVMAP_BIT), 1618 (adapter->open_device_map | OFFLOAD_DEVMAP_BIT)) == 0) 1619 return (0); 1620 1621 ADAPTER_LOCK(pi->adapter); 1622 if (!adap_up) 1623 err = cxgb_up(adapter); 1624 ADAPTER_UNLOCK(pi->adapter); 1625 if (err) 1626 return (err); 1627 1628 t3_tp_set_offload_mode(adapter, 1); 1629 tdev->lldev = adapter->port[0].ifp; 1630 err = cxgb_offload_activate(adapter); 1631 if (err) 1632 goto out; 1633 1634 init_port_mtus(adapter); 1635 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1636 adapter->params.b_wnd, 1637 adapter->params.rev == 0 ? 1638 adapter->port[0].ifp->if_mtu : 0xffff); 1639 init_smt(adapter); 1640 1641 /* Call back all registered clients */ 1642 cxgb_add_clients(tdev); 1643 1644 out: 1645 /* restore them in case the offload module has changed them */ 1646 if (err) { 1647 t3_tp_set_offload_mode(adapter, 0); 1648 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1649 cxgb_set_dummy_ops(tdev); 1650 } 1651 return (err); 1652 } 1653 #ifdef notyet 1654 static int 1655 offload_close(struct toedev *tdev) 1656 { 1657 struct adapter *adapter = tdev2adap(tdev); 1658 1659 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1660 return (0); 1661 1662 /* Call back all registered clients */ 1663 cxgb_remove_clients(tdev); 1664 tdev->lldev = NULL; 1665 cxgb_set_dummy_ops(tdev); 1666 t3_tp_set_offload_mode(adapter, 0); 1667 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1668 1669 if (!adapter->open_device_map) 1670 cxgb_down(adapter); 1671 1672 cxgb_offload_deactivate(adapter); 1673 return (0); 1674 } 1675 #endif 1676 1677 static void 1678 cxgb_init(void *arg) 1679 { 1680 struct port_info *p = arg; 1681 1682 PORT_LOCK(p); 1683 cxgb_init_locked(p); 1684 PORT_UNLOCK(p); 1685 } 1686 1687 static void 1688 cxgb_init_locked(struct port_info *p) 1689 { 1690 struct ifnet *ifp; 1691 adapter_t *sc = p->adapter; 1692 int err; 1693 1694 PORT_LOCK_ASSERT_OWNED(p); 1695 ifp = p->ifp; 1696 1697 ADAPTER_LOCK(p->adapter); 1698 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1699 ADAPTER_UNLOCK(p->adapter); 1700 cxgb_stop_locked(p); 1701 return; 1702 } 1703 if (p->adapter->open_device_map == 0) { 1704 t3_intr_clear(sc); 1705 t3_sge_init_adapter(sc); 1706 } 1707 setbit(&p->adapter->open_device_map, p->port); 1708 ADAPTER_UNLOCK(p->adapter); 1709 1710 if (is_offload(sc) && !ofld_disable) { 1711 err = offload_open(p); 1712 if (err) 1713 log(LOG_WARNING, 1714 "Could not initialize offload capabilities\n"); 1715 } 1716 cxgb_link_start(p); 1717 t3_link_changed(sc, p->port); 1718 ifp->if_baudrate = p->link_config.speed * 1000000; 1719 1720 t3_port_intr_enable(sc, p->port); 1721 1722 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz, 1723 cxgb_tick, sc); 1724 1725 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1726 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1727 } 1728 1729 static void 1730 cxgb_set_rxmode(struct port_info *p) 1731 { 1732 struct t3_rx_mode rm; 1733 struct cmac *mac = &p->mac; 1734 1735 PORT_LOCK_ASSERT_OWNED(p); 1736 1737 t3_init_rx_mode(&rm, p); 1738 t3_mac_set_rx_mode(mac, &rm); 1739 } 1740 1741 static void 1742 cxgb_stop_locked(struct port_info *p) 1743 { 1744 struct ifnet *ifp; 1745 1746 PORT_LOCK_ASSERT_OWNED(p); 1747 ADAPTER_LOCK_ASSERT_NOTOWNED(p->adapter); 1748 1749 ifp = p->ifp; 1750 1751 t3_port_intr_disable(p->adapter, p->port); 1752 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1753 p->phy.ops->power_down(&p->phy, 1); 1754 t3_mac_disable(&p->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1755 1756 ADAPTER_LOCK(p->adapter); 1757 clrbit(&p->adapter->open_device_map, p->port); 1758 1759 1760 if (p->adapter->open_device_map == 0) { 1761 cxgb_down_locked(p->adapter); 1762 } else 1763 ADAPTER_UNLOCK(p->adapter); 1764 1765 } 1766 1767 static int 1768 cxgb_set_mtu(struct port_info *p, int mtu) 1769 { 1770 struct ifnet *ifp = p->ifp; 1771 int error = 0; 1772 1773 if ((mtu < ETHERMIN) || (mtu > ETHER_MAX_LEN_JUMBO)) 1774 error = EINVAL; 1775 else if (ifp->if_mtu != mtu) { 1776 PORT_LOCK(p); 1777 ifp->if_mtu = mtu; 1778 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1779 callout_stop(&p->adapter->cxgb_tick_ch); 1780 cxgb_stop_locked(p); 1781 cxgb_init_locked(p); 1782 } 1783 PORT_UNLOCK(p); 1784 } 1785 return (error); 1786 } 1787 1788 static int 1789 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1790 { 1791 struct port_info *p = ifp->if_softc; 1792 struct ifaddr *ifa = (struct ifaddr *)data; 1793 struct ifreq *ifr = (struct ifreq *)data; 1794 int flags, error = 0; 1795 uint32_t mask; 1796 1797 /* 1798 * XXX need to check that we aren't in the middle of an unload 1799 */ 1800 switch (command) { 1801 case SIOCSIFMTU: 1802 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1803 break; 1804 case SIOCSIFADDR: 1805 case SIOCGIFADDR: 1806 PORT_LOCK(p); 1807 if (ifa->ifa_addr->sa_family == AF_INET) { 1808 ifp->if_flags |= IFF_UP; 1809 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1810 cxgb_init_locked(p); 1811 arp_ifinit(ifp, ifa); 1812 } else 1813 error = ether_ioctl(ifp, command, data); 1814 PORT_UNLOCK(p); 1815 break; 1816 case SIOCSIFFLAGS: 1817 callout_drain(&p->adapter->cxgb_tick_ch); 1818 PORT_LOCK(p); 1819 if (ifp->if_flags & IFF_UP) { 1820 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1821 flags = p->if_flags; 1822 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1823 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1824 cxgb_set_rxmode(p); 1825 } else 1826 cxgb_init_locked(p); 1827 p->if_flags = ifp->if_flags; 1828 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1829 cxgb_stop_locked(p); 1830 1831 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1832 adapter_t *sc = p->adapter; 1833 callout_reset(&sc->cxgb_tick_ch, 1834 sc->params.stats_update_period * hz, 1835 cxgb_tick, sc); 1836 } 1837 PORT_UNLOCK(p); 1838 break; 1839 case SIOCSIFMEDIA: 1840 case SIOCGIFMEDIA: 1841 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1842 break; 1843 case SIOCSIFCAP: 1844 PORT_LOCK(p); 1845 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1846 if (mask & IFCAP_TXCSUM) { 1847 if (IFCAP_TXCSUM & ifp->if_capenable) { 1848 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 1849 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 1850 | CSUM_TSO); 1851 } else { 1852 ifp->if_capenable |= IFCAP_TXCSUM; 1853 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1854 } 1855 } else if (mask & IFCAP_RXCSUM) { 1856 if (IFCAP_RXCSUM & ifp->if_capenable) { 1857 ifp->if_capenable &= ~IFCAP_RXCSUM; 1858 } else { 1859 ifp->if_capenable |= IFCAP_RXCSUM; 1860 } 1861 } 1862 if (mask & IFCAP_TSO4) { 1863 if (IFCAP_TSO4 & ifp->if_capenable) { 1864 ifp->if_capenable &= ~IFCAP_TSO4; 1865 ifp->if_hwassist &= ~CSUM_TSO; 1866 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 1867 ifp->if_capenable |= IFCAP_TSO4; 1868 ifp->if_hwassist |= CSUM_TSO; 1869 } else { 1870 if (cxgb_debug) 1871 printf("cxgb requires tx checksum offload" 1872 " be enabled to use TSO\n"); 1873 error = EINVAL; 1874 } 1875 } 1876 PORT_UNLOCK(p); 1877 break; 1878 default: 1879 error = ether_ioctl(ifp, command, data); 1880 break; 1881 } 1882 return (error); 1883 } 1884 1885 static int 1886 cxgb_start_tx(struct ifnet *ifp, uint32_t txmax) 1887 { 1888 struct sge_qset *qs; 1889 struct sge_txq *txq; 1890 struct port_info *p = ifp->if_softc; 1891 struct mbuf *m0, *m = NULL; 1892 int err, in_use_init; 1893 1894 if (!p->link_config.link_ok) 1895 return (ENXIO); 1896 1897 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1898 return (ENOBUFS); 1899 1900 qs = &p->adapter->sge.qs[p->first_qset]; 1901 txq = &qs->txq[TXQ_ETH]; 1902 err = 0; 1903 1904 if (txq->flags & TXQ_TRANSMITTING) 1905 return (EINPROGRESS); 1906 1907 mtx_lock(&txq->lock); 1908 txq->flags |= TXQ_TRANSMITTING; 1909 in_use_init = txq->in_use; 1910 while ((txq->in_use - in_use_init < txmax) && 1911 (txq->size > txq->in_use + TX_MAX_DESC)) { 1912 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1913 if (m == NULL) 1914 break; 1915 /* 1916 * Convert chain to M_IOVEC 1917 */ 1918 KASSERT((m->m_flags & M_IOVEC) == 0, ("IOVEC set too early")); 1919 m0 = m; 1920 #ifdef INVARIANTS 1921 /* 1922 * Clean up after net stack sloppiness 1923 * before calling m_sanity 1924 */ 1925 m0 = m->m_next; 1926 while (m0) { 1927 m0->m_flags &= ~M_PKTHDR; 1928 m0 = m0->m_next; 1929 } 1930 m_sanity(m0, 0); 1931 m0 = m; 1932 #endif 1933 if (collapse_mbufs && m->m_pkthdr.len > MCLBYTES && 1934 m_collapse(m, TX_MAX_SEGS, &m0) == EFBIG) { 1935 if ((m0 = m_defrag(m, M_NOWAIT)) != NULL) { 1936 m = m0; 1937 m_collapse(m, TX_MAX_SEGS, &m0); 1938 } else 1939 break; 1940 } 1941 m = m0; 1942 if ((err = t3_encap(p, &m)) != 0) 1943 break; 1944 BPF_MTAP(ifp, m); 1945 } 1946 txq->flags &= ~TXQ_TRANSMITTING; 1947 mtx_unlock(&txq->lock); 1948 1949 if (__predict_false(err)) { 1950 if (err == ENOMEM) { 1951 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1952 IFQ_LOCK(&ifp->if_snd); 1953 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1954 IFQ_UNLOCK(&ifp->if_snd); 1955 } 1956 } 1957 if (err == 0 && m == NULL) 1958 err = ENOBUFS; 1959 else if ((err == 0) && (txq->size <= txq->in_use + TX_MAX_DESC) && 1960 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1961 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1962 err = ENOSPC; 1963 } 1964 return (err); 1965 } 1966 1967 static void 1968 cxgb_start_proc(void *arg, int ncount) 1969 { 1970 struct ifnet *ifp = arg; 1971 struct port_info *pi = ifp->if_softc; 1972 struct sge_qset *qs; 1973 struct sge_txq *txq; 1974 int error; 1975 1976 qs = &pi->adapter->sge.qs[pi->first_qset]; 1977 txq = &qs->txq[TXQ_ETH]; 1978 1979 do { 1980 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2) 1981 taskqueue_enqueue(pi->tq, &txq->qreclaim_task); 1982 1983 error = cxgb_start_tx(ifp, TX_START_MAX_DESC); 1984 } while (error == 0); 1985 } 1986 1987 static void 1988 cxgb_start(struct ifnet *ifp) 1989 { 1990 struct port_info *pi = ifp->if_softc; 1991 struct sge_qset *qs; 1992 struct sge_txq *txq; 1993 int err; 1994 1995 qs = &pi->adapter->sge.qs[pi->first_qset]; 1996 txq = &qs->txq[TXQ_ETH]; 1997 1998 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2) 1999 taskqueue_enqueue(pi->tq, 2000 &txq->qreclaim_task); 2001 2002 err = cxgb_start_tx(ifp, TX_START_MAX_DESC); 2003 2004 if (err == 0) 2005 taskqueue_enqueue(pi->tq, &pi->start_task); 2006 } 2007 2008 2009 static int 2010 cxgb_media_change(struct ifnet *ifp) 2011 { 2012 if_printf(ifp, "media change not supported\n"); 2013 return (ENXIO); 2014 } 2015 2016 static void 2017 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2018 { 2019 struct port_info *p = ifp->if_softc; 2020 2021 ifmr->ifm_status = IFM_AVALID; 2022 ifmr->ifm_active = IFM_ETHER; 2023 2024 if (!p->link_config.link_ok) 2025 return; 2026 2027 ifmr->ifm_status |= IFM_ACTIVE; 2028 2029 switch (p->link_config.speed) { 2030 case 10: 2031 ifmr->ifm_active |= IFM_10_T; 2032 break; 2033 case 100: 2034 ifmr->ifm_active |= IFM_100_TX; 2035 break; 2036 case 1000: 2037 ifmr->ifm_active |= IFM_1000_T; 2038 break; 2039 } 2040 2041 if (p->link_config.duplex) 2042 ifmr->ifm_active |= IFM_FDX; 2043 else 2044 ifmr->ifm_active |= IFM_HDX; 2045 } 2046 2047 static void 2048 cxgb_async_intr(void *data) 2049 { 2050 adapter_t *sc = data; 2051 2052 if (cxgb_debug) 2053 device_printf(sc->dev, "cxgb_async_intr\n"); 2054 /* 2055 * May need to sleep - defer to taskqueue 2056 */ 2057 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2058 } 2059 2060 static void 2061 cxgb_ext_intr_handler(void *arg, int count) 2062 { 2063 adapter_t *sc = (adapter_t *)arg; 2064 2065 if (cxgb_debug) 2066 printf("cxgb_ext_intr_handler\n"); 2067 2068 t3_phy_intr_handler(sc); 2069 2070 /* Now reenable external interrupts */ 2071 ADAPTER_LOCK(sc); 2072 if (sc->slow_intr_mask) { 2073 sc->slow_intr_mask |= F_T3DBG; 2074 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2075 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2076 } 2077 ADAPTER_UNLOCK(sc); 2078 } 2079 2080 static void 2081 check_link_status(adapter_t *sc) 2082 { 2083 int i; 2084 2085 for (i = 0; i < (sc)->params.nports; ++i) { 2086 struct port_info *p = &sc->port[i]; 2087 2088 if (!(p->port_type->caps & SUPPORTED_IRQ)) 2089 t3_link_changed(sc, i); 2090 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2091 } 2092 } 2093 2094 static void 2095 check_t3b2_mac(struct adapter *adapter) 2096 { 2097 int i; 2098 2099 for_each_port(adapter, i) { 2100 struct port_info *p = &adapter->port[i]; 2101 struct ifnet *ifp = p->ifp; 2102 int status; 2103 2104 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2105 continue; 2106 2107 status = 0; 2108 PORT_LOCK(p); 2109 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2110 status = t3b2_mac_watchdog_task(&p->mac); 2111 if (status == 1) 2112 p->mac.stats.num_toggled++; 2113 else if (status == 2) { 2114 struct cmac *mac = &p->mac; 2115 2116 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN 2117 + ETHER_VLAN_ENCAP_LEN); 2118 t3_mac_set_address(mac, 0, p->hw_addr); 2119 cxgb_set_rxmode(p); 2120 t3_link_start(&p->phy, mac, &p->link_config); 2121 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2122 t3_port_intr_enable(adapter, p->port); 2123 p->mac.stats.num_resets++; 2124 } 2125 PORT_UNLOCK(p); 2126 } 2127 } 2128 2129 static void 2130 cxgb_tick(void *arg) 2131 { 2132 adapter_t *sc = (adapter_t *)arg; 2133 2134 taskqueue_enqueue(sc->tq, &sc->tick_task); 2135 2136 if (sc->open_device_map != 0) 2137 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz, 2138 cxgb_tick, sc); 2139 } 2140 2141 static void 2142 cxgb_tick_handler(void *arg, int count) 2143 { 2144 adapter_t *sc = (adapter_t *)arg; 2145 const struct adapter_params *p = &sc->params; 2146 2147 ADAPTER_LOCK(sc); 2148 if (p->linkpoll_period) 2149 check_link_status(sc); 2150 2151 /* 2152 * adapter lock can currently only be acquire after the 2153 * port lock 2154 */ 2155 ADAPTER_UNLOCK(sc); 2156 2157 if (p->rev == T3_REV_B2 && p->nports < 4) 2158 check_t3b2_mac(sc); 2159 } 2160 2161 #if 0 2162 static void * 2163 filter_get_idx(struct seq_file *seq, loff_t pos) 2164 { 2165 int i; 2166 struct adapter *adap = seq->private; 2167 struct filter_info *p = adap->filters; 2168 2169 if (!p) 2170 return NULL; 2171 2172 for (i = 0; i < adap->params.mc5.nfilters; i++, p++) 2173 if (p->valid) { 2174 if (!pos) 2175 return p; 2176 pos--; 2177 } 2178 return NULL; 2179 } 2180 2181 static void *filter_get_nxt_idx(struct seq_file *seq, struct filter_info *p) 2182 { 2183 struct adapter *adap = seq->private; 2184 struct filter_info *end = &adap->filters[adap->params.mc5.nfilters]; 2185 2186 while (++p < end && !p->valid) 2187 ; 2188 return p < end ? p : NULL; 2189 } 2190 2191 static void *filter_seq_start(struct seq_file *seq, loff_t *pos) 2192 { 2193 return *pos ? filter_get_idx(seq, *pos - 1) : SEQ_START_TOKEN; 2194 } 2195 2196 static void *filter_seq_next(struct seq_file *seq, void *v, loff_t *pos) 2197 { 2198 v = *pos ? filter_get_nxt_idx(seq, v) : filter_get_idx(seq, 0); 2199 if (v) 2200 ++*pos; 2201 return v; 2202 } 2203 2204 static void filter_seq_stop(struct seq_file *seq, void *v) 2205 { 2206 } 2207 2208 static int filter_seq_show(struct seq_file *seq, void *v) 2209 { 2210 static const char *pkt_type[] = { "any", "tcp", "udp", "frag" }; 2211 2212 if (v == SEQ_START_TOKEN) 2213 seq_puts(seq, "index SIP DIP sport " 2214 "dport VLAN PRI MAC type Q\n"); 2215 else { 2216 char sip[20], dip[20]; 2217 struct filter_info *f = v; 2218 struct adapter *adap = seq->private; 2219 2220 sprintf(sip, NIPQUAD_FMT "/%-2u", HIPQUAD(f->sip), 2221 f->sip_mask ? 33 - ffs(f->sip_mask) : 0); 2222 sprintf(dip, NIPQUAD_FMT, HIPQUAD(f->dip)); 2223 seq_printf(seq, "%5zu %18s %15s ", f - adap->filters, sip, dip); 2224 seq_printf(seq, f->sport ? "%5u " : " * ", f->sport); 2225 seq_printf(seq, f->dport ? "%5u " : " * ", f->dport); 2226 seq_printf(seq, f->vlan != 0xfff ? "%4u " : " * ", f->vlan); 2227 seq_printf(seq, f->vlan_prio == FILTER_NO_VLAN_PRI ? 2228 " * " : "%1u/%1u ", f->vlan_prio, f->vlan_prio | 1); 2229 if (!f->mac_vld) 2230 seq_printf(seq, " * "); 2231 else if (f->mac_hit) 2232 seq_printf(seq, "%3u ", f->mac_idx); 2233 else 2234 seq_printf(seq, " -1 "); 2235 seq_printf(seq, "%4s ", pkt_type[f->pkt_type]); 2236 if (!f->pass) 2237 seq_printf(seq, "-\n"); 2238 else if (f->rss) 2239 seq_printf(seq, "*\n"); 2240 else 2241 seq_printf(seq, "%1u\n", f->qset); 2242 } 2243 return 0; 2244 } 2245 2246 static struct seq_operations filter_seq_ops = { 2247 .start = filter_seq_start, 2248 .next = filter_seq_next, 2249 .stop = filter_seq_stop, 2250 .show = filter_seq_show 2251 }; 2252 2253 static int filter_seq_open(struct inode *inode, struct file *file) 2254 { 2255 int rc = seq_open(file, &filter_seq_ops); 2256 2257 if (!rc) { 2258 struct proc_dir_entry *dp = PDE(inode); 2259 struct seq_file *seq = file->private_data; 2260 2261 seq->private = dp->data; 2262 } 2263 return rc; 2264 } 2265 2266 static struct file_operations filter_seq_fops = { 2267 .owner = THIS_MODULE, 2268 .open = filter_seq_open, 2269 .read = seq_read, 2270 .llseek = seq_lseek, 2271 .release = seq_release 2272 }; 2273 2274 #endif 2275 2276 static int 2277 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2278 { 2279 uint8_t *buf; 2280 int err = 0; 2281 u32 aligned_offset, aligned_len, *p; 2282 struct adapter *adapter = pi->adapter; 2283 2284 2285 aligned_offset = offset & ~3; 2286 aligned_len = (len + (offset & 3) + 3) & ~3; 2287 2288 if (aligned_offset != offset || aligned_len != len) { 2289 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2290 if (!buf) 2291 return (ENOMEM); 2292 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2293 if (!err && aligned_len > 4) 2294 err = t3_seeprom_read(adapter, 2295 aligned_offset + aligned_len - 4, 2296 (u32 *)&buf[aligned_len - 4]); 2297 if (err) 2298 goto out; 2299 memcpy(buf + (offset & 3), data, len); 2300 } else 2301 buf = (uint8_t *)(uintptr_t)data; 2302 2303 err = t3_seeprom_wp(adapter, 0); 2304 if (err) 2305 goto out; 2306 2307 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2308 err = t3_seeprom_write(adapter, aligned_offset, *p); 2309 aligned_offset += 4; 2310 } 2311 2312 if (!err) 2313 err = t3_seeprom_wp(adapter, 1); 2314 out: 2315 if (buf != data) 2316 free(buf, M_DEVBUF); 2317 return err; 2318 } 2319 2320 2321 static int 2322 in_range(int val, int lo, int hi) 2323 { 2324 return val < 0 || (val <= hi && val >= lo); 2325 } 2326 2327 static int 2328 cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2329 { 2330 return (0); 2331 } 2332 2333 static int 2334 cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2335 { 2336 return (0); 2337 } 2338 2339 static int 2340 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2341 int fflag, struct thread *td) 2342 { 2343 int mmd, error = 0; 2344 struct port_info *pi = dev->si_drv1; 2345 adapter_t *sc = pi->adapter; 2346 2347 #ifdef PRIV_SUPPORTED 2348 if (priv_check(td, PRIV_DRIVER)) { 2349 if (cxgb_debug) 2350 printf("user does not have access to privileged ioctls\n"); 2351 return (EPERM); 2352 } 2353 #else 2354 if (suser(td)) { 2355 if (cxgb_debug) 2356 printf("user does not have access to privileged ioctls\n"); 2357 return (EPERM); 2358 } 2359 #endif 2360 2361 switch (cmd) { 2362 case SIOCGMIIREG: { 2363 uint32_t val; 2364 struct cphy *phy = &pi->phy; 2365 struct mii_data *mid = (struct mii_data *)data; 2366 2367 if (!phy->mdio_read) 2368 return (EOPNOTSUPP); 2369 if (is_10G(sc)) { 2370 mmd = mid->phy_id >> 8; 2371 if (!mmd) 2372 mmd = MDIO_DEV_PCS; 2373 else if (mmd > MDIO_DEV_XGXS) 2374 return (EINVAL); 2375 2376 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2377 mid->reg_num, &val); 2378 } else 2379 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2380 mid->reg_num & 0x1f, &val); 2381 if (error == 0) 2382 mid->val_out = val; 2383 break; 2384 } 2385 case SIOCSMIIREG: { 2386 struct cphy *phy = &pi->phy; 2387 struct mii_data *mid = (struct mii_data *)data; 2388 2389 if (!phy->mdio_write) 2390 return (EOPNOTSUPP); 2391 if (is_10G(sc)) { 2392 mmd = mid->phy_id >> 8; 2393 if (!mmd) 2394 mmd = MDIO_DEV_PCS; 2395 else if (mmd > MDIO_DEV_XGXS) 2396 return (EINVAL); 2397 2398 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2399 mmd, mid->reg_num, mid->val_in); 2400 } else 2401 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2402 mid->reg_num & 0x1f, 2403 mid->val_in); 2404 break; 2405 } 2406 case CHELSIO_SETREG: { 2407 struct ch_reg *edata = (struct ch_reg *)data; 2408 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2409 return (EFAULT); 2410 t3_write_reg(sc, edata->addr, edata->val); 2411 break; 2412 } 2413 case CHELSIO_GETREG: { 2414 struct ch_reg *edata = (struct ch_reg *)data; 2415 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2416 return (EFAULT); 2417 edata->val = t3_read_reg(sc, edata->addr); 2418 break; 2419 } 2420 case CHELSIO_GET_SGE_CONTEXT: { 2421 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2422 mtx_lock(&sc->sge.reg_lock); 2423 switch (ecntxt->cntxt_type) { 2424 case CNTXT_TYPE_EGRESS: 2425 error = t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2426 ecntxt->data); 2427 break; 2428 case CNTXT_TYPE_FL: 2429 error = t3_sge_read_fl(sc, ecntxt->cntxt_id, 2430 ecntxt->data); 2431 break; 2432 case CNTXT_TYPE_RSP: 2433 error = t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2434 ecntxt->data); 2435 break; 2436 case CNTXT_TYPE_CQ: 2437 error = t3_sge_read_cq(sc, ecntxt->cntxt_id, 2438 ecntxt->data); 2439 break; 2440 default: 2441 error = EINVAL; 2442 break; 2443 } 2444 mtx_unlock(&sc->sge.reg_lock); 2445 break; 2446 } 2447 case CHELSIO_GET_SGE_DESC: { 2448 struct ch_desc *edesc = (struct ch_desc *)data; 2449 int ret; 2450 if (edesc->queue_num >= SGE_QSETS * 6) 2451 return (EINVAL); 2452 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2453 edesc->queue_num % 6, edesc->idx, edesc->data); 2454 if (ret < 0) 2455 return (EINVAL); 2456 edesc->size = ret; 2457 break; 2458 } 2459 case CHELSIO_SET_QSET_PARAMS: { 2460 struct qset_params *q; 2461 struct ch_qset_params *t = (struct ch_qset_params *)data; 2462 2463 if (t->qset_idx >= SGE_QSETS) 2464 return (EINVAL); 2465 if (!in_range(t->intr_lat, 0, M_NEWTIMER) || 2466 !in_range(t->cong_thres, 0, 255) || 2467 !in_range(t->txq_size[0], MIN_TXQ_ENTRIES, 2468 MAX_TXQ_ENTRIES) || 2469 !in_range(t->txq_size[1], MIN_TXQ_ENTRIES, 2470 MAX_TXQ_ENTRIES) || 2471 !in_range(t->txq_size[2], MIN_CTRL_TXQ_ENTRIES, 2472 MAX_CTRL_TXQ_ENTRIES) || 2473 !in_range(t->fl_size[0], MIN_FL_ENTRIES, MAX_RX_BUFFERS) || 2474 !in_range(t->fl_size[1], MIN_FL_ENTRIES, 2475 MAX_RX_JUMBO_BUFFERS) || 2476 !in_range(t->rspq_size, MIN_RSPQ_ENTRIES, MAX_RSPQ_ENTRIES)) 2477 return (EINVAL); 2478 if ((sc->flags & FULL_INIT_DONE) && 2479 (t->rspq_size >= 0 || t->fl_size[0] >= 0 || 2480 t->fl_size[1] >= 0 || t->txq_size[0] >= 0 || 2481 t->txq_size[1] >= 0 || t->txq_size[2] >= 0 || 2482 t->polling >= 0 || t->cong_thres >= 0)) 2483 return (EBUSY); 2484 2485 q = &sc->params.sge.qset[t->qset_idx]; 2486 2487 if (t->rspq_size >= 0) 2488 q->rspq_size = t->rspq_size; 2489 if (t->fl_size[0] >= 0) 2490 q->fl_size = t->fl_size[0]; 2491 if (t->fl_size[1] >= 0) 2492 q->jumbo_size = t->fl_size[1]; 2493 if (t->txq_size[0] >= 0) 2494 q->txq_size[0] = t->txq_size[0]; 2495 if (t->txq_size[1] >= 0) 2496 q->txq_size[1] = t->txq_size[1]; 2497 if (t->txq_size[2] >= 0) 2498 q->txq_size[2] = t->txq_size[2]; 2499 if (t->cong_thres >= 0) 2500 q->cong_thres = t->cong_thres; 2501 if (t->intr_lat >= 0) { 2502 struct sge_qset *qs = &sc->sge.qs[t->qset_idx]; 2503 2504 q->coalesce_nsecs = t->intr_lat*1000; 2505 t3_update_qset_coalesce(qs, q); 2506 } 2507 break; 2508 } 2509 case CHELSIO_GET_QSET_PARAMS: { 2510 struct qset_params *q; 2511 struct ch_qset_params *t = (struct ch_qset_params *)data; 2512 2513 if (t->qset_idx >= SGE_QSETS) 2514 return (EINVAL); 2515 2516 q = &(sc)->params.sge.qset[t->qset_idx]; 2517 t->rspq_size = q->rspq_size; 2518 t->txq_size[0] = q->txq_size[0]; 2519 t->txq_size[1] = q->txq_size[1]; 2520 t->txq_size[2] = q->txq_size[2]; 2521 t->fl_size[0] = q->fl_size; 2522 t->fl_size[1] = q->jumbo_size; 2523 t->polling = q->polling; 2524 t->intr_lat = q->coalesce_nsecs / 1000; 2525 t->cong_thres = q->cong_thres; 2526 break; 2527 } 2528 case CHELSIO_SET_QSET_NUM: { 2529 struct ch_reg *edata = (struct ch_reg *)data; 2530 unsigned int port_idx = pi->port; 2531 2532 if (sc->flags & FULL_INIT_DONE) 2533 return (EBUSY); 2534 if (edata->val < 1 || 2535 (edata->val > 1 && !(sc->flags & USING_MSIX))) 2536 return (EINVAL); 2537 if (edata->val + sc->port[!port_idx].nqsets > SGE_QSETS) 2538 return (EINVAL); 2539 sc->port[port_idx].nqsets = edata->val; 2540 sc->port[0].first_qset = 0; 2541 /* 2542 * XXX hardcode ourselves to 2 ports just like LEEENUX 2543 */ 2544 sc->port[1].first_qset = sc->port[0].nqsets; 2545 break; 2546 } 2547 case CHELSIO_GET_QSET_NUM: { 2548 struct ch_reg *edata = (struct ch_reg *)data; 2549 edata->val = pi->nqsets; 2550 break; 2551 } 2552 #ifdef notyet 2553 case CHELSIO_LOAD_FW: 2554 case CHELSIO_GET_PM: 2555 case CHELSIO_SET_PM: 2556 return (EOPNOTSUPP); 2557 break; 2558 #endif 2559 case CHELSIO_SETMTUTAB: { 2560 struct ch_mtus *m = (struct ch_mtus *)data; 2561 int i; 2562 2563 if (!is_offload(sc)) 2564 return (EOPNOTSUPP); 2565 if (offload_running(sc)) 2566 return (EBUSY); 2567 if (m->nmtus != NMTUS) 2568 return (EINVAL); 2569 if (m->mtus[0] < 81) /* accommodate SACK */ 2570 return (EINVAL); 2571 2572 /* 2573 * MTUs must be in ascending order 2574 */ 2575 for (i = 1; i < NMTUS; ++i) 2576 if (m->mtus[i] < m->mtus[i - 1]) 2577 return (EINVAL); 2578 2579 memcpy(sc->params.mtus, m->mtus, 2580 sizeof(sc->params.mtus)); 2581 break; 2582 } 2583 case CHELSIO_GETMTUTAB: { 2584 struct ch_mtus *m = (struct ch_mtus *)data; 2585 2586 if (!is_offload(sc)) 2587 return (EOPNOTSUPP); 2588 2589 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2590 m->nmtus = NMTUS; 2591 break; 2592 } 2593 case CHELSIO_SET_FILTER: { 2594 struct ch_filter *f = (struct ch_filter *)data; 2595 struct filter_info *p; 2596 int ret; 2597 2598 if (sc->params.mc5.nfilters == 0) 2599 return (EOPNOTSUPP); 2600 if (!(sc->flags & FULL_INIT_DONE)) 2601 return (EAGAIN); /* can still change nfilters */ 2602 if (sc->filters == NULL) 2603 return (ENOMEM); 2604 2605 if (f->filter_id >= sc->params.mc5.nfilters || 2606 (f->val.dip && f->mask.dip != 0xffffffff) || 2607 (f->val.sport && f->mask.sport != 0xffff) || 2608 (f->val.dport && f->mask.dport != 0xffff) || 2609 (f->mask.vlan && f->mask.vlan != 0xfff) || 2610 (f->mask.vlan_prio && f->mask.vlan_prio != 7) || 2611 (f->mac_addr_idx != 0xffff && f->mac_addr_idx > 15) || 2612 f->qset >= SGE_QSETS || 2613 sc->rrss_map[f->qset] >= RSS_TABLE_SIZE) 2614 return (EINVAL); 2615 2616 p = &sc->filters[f->filter_id]; 2617 if (p->locked) 2618 return (EPERM); 2619 2620 p->sip = f->val.sip; 2621 p->sip_mask = f->mask.sip; 2622 p->dip = f->val.dip; 2623 p->sport = f->val.sport; 2624 p->dport = f->val.dport; 2625 p->vlan = f->mask.vlan ? f->val.vlan : 0xfff; 2626 p->vlan_prio = f->mask.vlan_prio ? (f->val.vlan_prio & 6) : 2627 FILTER_NO_VLAN_PRI; 2628 p->mac_hit = f->mac_hit; 2629 p->mac_vld = f->mac_addr_idx != 0xffff; 2630 p->mac_idx = f->mac_addr_idx; 2631 p->pkt_type = f->proto; 2632 p->report_filter_id = f->want_filter_id; 2633 p->pass = f->pass; 2634 p->rss = f->rss; 2635 p->qset = f->qset; 2636 2637 ret = set_filter(sc, f->filter_id, p); 2638 if (ret) 2639 return ret; 2640 p->valid = 1; 2641 break; 2642 } 2643 case CHELSIO_DEL_FILTER: { 2644 struct ch_filter *f = (struct ch_filter *)data; 2645 struct filter_info *p; 2646 2647 if (sc->params.mc5.nfilters == 0) 2648 return (EOPNOTSUPP); 2649 if (!(sc->flags & FULL_INIT_DONE)) 2650 return (EAGAIN); /* can still change nfilters */ 2651 if (sc->filters == NULL) 2652 return (ENOMEM); 2653 if (f->filter_id >= sc->params.mc5.nfilters) 2654 return (EINVAL); 2655 2656 p = &sc->filters[f->filter_id]; 2657 if (p->locked) 2658 return (EPERM); 2659 memset(p, 0, sizeof(*p)); 2660 p->sip_mask = 0xffffffff; 2661 p->vlan = 0xfff; 2662 p->vlan_prio = FILTER_NO_VLAN_PRI; 2663 p->pkt_type = 1; 2664 return set_filter(sc, f->filter_id, p); 2665 } 2666 case CHELSIO_DEVUP: 2667 if (!is_offload(sc)) 2668 return (EOPNOTSUPP); 2669 return offload_open(pi); 2670 break; 2671 case CHELSIO_GET_MEM: { 2672 struct ch_mem_range *t = (struct ch_mem_range *)data; 2673 struct mc7 *mem; 2674 uint8_t *useraddr; 2675 u64 buf[32]; 2676 2677 if (!is_offload(sc)) 2678 return (EOPNOTSUPP); 2679 if (!(sc->flags & FULL_INIT_DONE)) 2680 return (EIO); /* need the memory controllers */ 2681 if ((t->addr & 0x7) || (t->len & 0x7)) 2682 return (EINVAL); 2683 if (t->mem_id == MEM_CM) 2684 mem = &sc->cm; 2685 else if (t->mem_id == MEM_PMRX) 2686 mem = &sc->pmrx; 2687 else if (t->mem_id == MEM_PMTX) 2688 mem = &sc->pmtx; 2689 else 2690 return (EINVAL); 2691 2692 /* 2693 * Version scheme: 2694 * bits 0..9: chip version 2695 * bits 10..15: chip revision 2696 */ 2697 t->version = 3 | (sc->params.rev << 10); 2698 2699 /* 2700 * Read 256 bytes at a time as len can be large and we don't 2701 * want to use huge intermediate buffers. 2702 */ 2703 useraddr = (uint8_t *)(t + 1); /* advance to start of buffer */ 2704 while (t->len) { 2705 unsigned int chunk = min(t->len, sizeof(buf)); 2706 2707 error = t3_mc7_bd_read(mem, t->addr / 8, chunk / 8, buf); 2708 if (error) 2709 return (-error); 2710 if (copyout(buf, useraddr, chunk)) 2711 return (EFAULT); 2712 useraddr += chunk; 2713 t->addr += chunk; 2714 t->len -= chunk; 2715 } 2716 break; 2717 } 2718 case CHELSIO_READ_TCAM_WORD: { 2719 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2720 2721 if (!is_offload(sc)) 2722 return (EOPNOTSUPP); 2723 if (!(sc->flags & FULL_INIT_DONE)) 2724 return (EIO); /* need MC5 */ 2725 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2726 break; 2727 } 2728 case CHELSIO_SET_TRACE_FILTER: { 2729 struct ch_trace *t = (struct ch_trace *)data; 2730 const struct trace_params *tp; 2731 2732 tp = (const struct trace_params *)&t->sip; 2733 if (t->config_tx) 2734 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2735 t->trace_tx); 2736 if (t->config_rx) 2737 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2738 t->trace_rx); 2739 break; 2740 } 2741 case CHELSIO_SET_PKTSCHED: { 2742 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2743 if (sc->open_device_map == 0) 2744 return (EAGAIN); 2745 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2746 p->binding); 2747 break; 2748 } 2749 case CHELSIO_IFCONF_GETREGS: { 2750 struct ifconf_regs *regs = (struct ifconf_regs *)data; 2751 int reglen = cxgb_get_regs_len(); 2752 uint8_t *buf = malloc(REGDUMP_SIZE, M_DEVBUF, M_NOWAIT); 2753 if (buf == NULL) { 2754 return (ENOMEM); 2755 } if (regs->len > reglen) 2756 regs->len = reglen; 2757 else if (regs->len < reglen) { 2758 error = E2BIG; 2759 goto done; 2760 } 2761 cxgb_get_regs(sc, regs, buf); 2762 error = copyout(buf, regs->data, reglen); 2763 2764 done: 2765 free(buf, M_DEVBUF); 2766 2767 break; 2768 } 2769 case CHELSIO_SET_HW_SCHED: { 2770 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2771 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2772 2773 if ((sc->flags & FULL_INIT_DONE) == 0) 2774 return (EAGAIN); /* need TP to be initialized */ 2775 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2776 !in_range(t->channel, 0, 1) || 2777 !in_range(t->kbps, 0, 10000000) || 2778 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2779 !in_range(t->flow_ipg, 0, 2780 dack_ticks_to_usec(sc, 0x7ff))) 2781 return (EINVAL); 2782 2783 if (t->kbps >= 0) { 2784 error = t3_config_sched(sc, t->kbps, t->sched); 2785 if (error < 0) 2786 return (-error); 2787 } 2788 if (t->class_ipg >= 0) 2789 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2790 if (t->flow_ipg >= 0) { 2791 t->flow_ipg *= 1000; /* us -> ns */ 2792 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2793 } 2794 if (t->mode >= 0) { 2795 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2796 2797 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2798 bit, t->mode ? bit : 0); 2799 } 2800 if (t->channel >= 0) 2801 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2802 1 << t->sched, t->channel << t->sched); 2803 break; 2804 } 2805 default: 2806 return (EOPNOTSUPP); 2807 break; 2808 } 2809 2810 return (error); 2811 } 2812 2813 static __inline void 2814 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2815 unsigned int end) 2816 { 2817 uint32_t *p = (uint32_t *)buf + start; 2818 2819 for ( ; start <= end; start += sizeof(uint32_t)) 2820 *p++ = t3_read_reg(ap, start); 2821 } 2822 2823 #define T3_REGMAP_SIZE (3 * 1024) 2824 static int 2825 cxgb_get_regs_len(void) 2826 { 2827 return T3_REGMAP_SIZE; 2828 } 2829 #undef T3_REGMAP_SIZE 2830 2831 static void 2832 cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf) 2833 { 2834 2835 /* 2836 * Version scheme: 2837 * bits 0..9: chip version 2838 * bits 10..15: chip revision 2839 * bit 31: set for PCIe cards 2840 */ 2841 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2842 2843 /* 2844 * We skip the MAC statistics registers because they are clear-on-read. 2845 * Also reading multi-register stats would need to synchronize with the 2846 * periodic mac stats accumulation. Hard to justify the complexity. 2847 */ 2848 memset(buf, 0, REGDUMP_SIZE); 2849 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2850 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2851 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2852 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2853 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2854 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2855 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2856 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2857 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2858 } 2859