1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/pciio.h> 39 #include <sys/conf.h> 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/bus_dma.h> 43 #include <sys/ktr.h> 44 #include <sys/rman.h> 45 #include <sys/ioccom.h> 46 #include <sys/mbuf.h> 47 #include <sys/linker.h> 48 #include <sys/firmware.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/smp.h> 52 #include <sys/sysctl.h> 53 #include <sys/syslog.h> 54 #include <sys/queue.h> 55 #include <sys/taskqueue.h> 56 #include <sys/proc.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 66 #include <netinet/in_systm.h> 67 #include <netinet/in.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pci_private.h> 77 78 #ifdef CONFIG_DEFINED 79 #include <cxgb_include.h> 80 #else 81 #include <dev/cxgb/cxgb_include.h> 82 #endif 83 84 #ifdef PRIV_SUPPORTED 85 #include <sys/priv.h> 86 #endif 87 88 #ifdef IFNET_MULTIQUEUE 89 #include <machine/intr_machdep.h> 90 #endif 91 92 static int cxgb_setup_msix(adapter_t *, int); 93 static void cxgb_teardown_msix(adapter_t *); 94 static void cxgb_init(void *); 95 static void cxgb_init_locked(struct port_info *); 96 static void cxgb_stop_locked(struct port_info *); 97 static void cxgb_set_rxmode(struct port_info *); 98 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 99 static int cxgb_media_change(struct ifnet *); 100 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 101 static int setup_sge_qsets(adapter_t *); 102 static void cxgb_async_intr(void *); 103 static void cxgb_ext_intr_handler(void *, int); 104 static void cxgb_tick_handler(void *, int); 105 static void cxgb_down_locked(struct adapter *sc); 106 static void cxgb_tick(void *); 107 static void setup_rss(adapter_t *sc); 108 109 /* Attachment glue for the PCI controller end of the device. Each port of 110 * the device is attached separately, as defined later. 111 */ 112 static int cxgb_controller_probe(device_t); 113 static int cxgb_controller_attach(device_t); 114 static int cxgb_controller_detach(device_t); 115 static void cxgb_free(struct adapter *); 116 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 117 unsigned int end); 118 static void cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf); 119 static int cxgb_get_regs_len(void); 120 static int offload_open(struct port_info *pi); 121 static void touch_bars(device_t dev); 122 static int offload_close(struct t3cdev *tdev); 123 static void cxgb_link_start(struct port_info *p); 124 125 static device_method_t cxgb_controller_methods[] = { 126 DEVMETHOD(device_probe, cxgb_controller_probe), 127 DEVMETHOD(device_attach, cxgb_controller_attach), 128 DEVMETHOD(device_detach, cxgb_controller_detach), 129 130 /* bus interface */ 131 DEVMETHOD(bus_print_child, bus_generic_print_child), 132 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 133 134 { 0, 0 } 135 }; 136 137 static driver_t cxgb_controller_driver = { 138 "cxgbc", 139 cxgb_controller_methods, 140 sizeof(struct adapter) 141 }; 142 143 static devclass_t cxgb_controller_devclass; 144 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 145 146 /* 147 * Attachment glue for the ports. Attachment is done directly to the 148 * controller device. 149 */ 150 static int cxgb_port_probe(device_t); 151 static int cxgb_port_attach(device_t); 152 static int cxgb_port_detach(device_t); 153 154 static device_method_t cxgb_port_methods[] = { 155 DEVMETHOD(device_probe, cxgb_port_probe), 156 DEVMETHOD(device_attach, cxgb_port_attach), 157 DEVMETHOD(device_detach, cxgb_port_detach), 158 { 0, 0 } 159 }; 160 161 static driver_t cxgb_port_driver = { 162 "cxgb", 163 cxgb_port_methods, 164 0 165 }; 166 167 static d_ioctl_t cxgb_extension_ioctl; 168 static d_open_t cxgb_extension_open; 169 static d_close_t cxgb_extension_close; 170 171 static struct cdevsw cxgb_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = cxgb_extension_open, 175 .d_close = cxgb_extension_close, 176 .d_ioctl = cxgb_extension_ioctl, 177 .d_name = "cxgb", 178 }; 179 180 static devclass_t cxgb_port_devclass; 181 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 182 183 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 184 185 /* 186 * The driver uses the best interrupt scheme available on a platform in the 187 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 188 * of these schemes the driver may consider as follows: 189 * 190 * msi = 2: choose from among all three options 191 * msi = 1 : only consider MSI and pin interrupts 192 * msi = 0: force pin interrupts 193 */ 194 static int msi_allowed = 2; 195 196 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 197 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 198 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 199 "MSI-X, MSI, INTx selector"); 200 201 /* 202 * The driver enables offload as a default. 203 * To disable it, use ofld_disable = 1. 204 */ 205 static int ofld_disable = 0; 206 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 207 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 208 "disable ULP offload"); 209 210 /* 211 * The driver uses an auto-queue algorithm by default. 212 * To disable it and force a single queue-set per port, use singleq = 1. 213 */ 214 static int singleq = 0; 215 TUNABLE_INT("hw.cxgb.singleq", &singleq); 216 SYSCTL_UINT(_hw_cxgb, OID_AUTO, singleq, CTLFLAG_RDTUN, &singleq, 0, 217 "use a single queue-set per port"); 218 219 220 /* 221 * The driver uses an auto-queue algorithm by default. 222 * To disable it and force a single queue-set per port, use singleq = 1. 223 */ 224 static int force_fw_update = 0; 225 TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 226 SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 227 "update firmware even if up to date"); 228 229 int cxgb_use_16k_clusters = 0; 230 TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 231 SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 232 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 233 234 enum { 235 MAX_TXQ_ENTRIES = 16384, 236 MAX_CTRL_TXQ_ENTRIES = 1024, 237 MAX_RSPQ_ENTRIES = 16384, 238 MAX_RX_BUFFERS = 16384, 239 MAX_RX_JUMBO_BUFFERS = 16384, 240 MIN_TXQ_ENTRIES = 4, 241 MIN_CTRL_TXQ_ENTRIES = 4, 242 MIN_RSPQ_ENTRIES = 32, 243 MIN_FL_ENTRIES = 32, 244 MIN_FL_JUMBO_ENTRIES = 32 245 }; 246 247 struct filter_info { 248 u32 sip; 249 u32 sip_mask; 250 u32 dip; 251 u16 sport; 252 u16 dport; 253 u32 vlan:12; 254 u32 vlan_prio:3; 255 u32 mac_hit:1; 256 u32 mac_idx:4; 257 u32 mac_vld:1; 258 u32 pkt_type:2; 259 u32 report_filter_id:1; 260 u32 pass:1; 261 u32 rss:1; 262 u32 qset:3; 263 u32 locked:1; 264 u32 valid:1; 265 }; 266 267 enum { FILTER_NO_VLAN_PRI = 7 }; 268 269 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 270 271 /* Table for probing the cards. The desc field isn't actually used */ 272 struct cxgb_ident { 273 uint16_t vendor; 274 uint16_t device; 275 int index; 276 char *desc; 277 } cxgb_identifiers[] = { 278 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 279 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 280 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 281 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 285 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 286 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 287 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 288 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 289 {0, 0, 0, NULL} 290 }; 291 292 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 293 294 295 void 296 cxgb_log_tcb(struct adapter *sc, unsigned int tid) 297 { 298 char buf[TCB_SIZE]; 299 uint64_t *tcb = (uint64_t *)buf; 300 int i, error; 301 struct mc7 *mem = &sc->cm; 302 303 error = t3_mc7_bd_read(mem, tid*TCB_SIZE/8, TCB_SIZE/8, tcb); 304 if (error) 305 printf("cxgb_tcb_log failed\n"); 306 307 CTR1(KTR_CXGB, "TCB tid=%u", tid); 308 for (i = 0; i < TCB_SIZE / 32; i++) { 309 CTR5(KTR_CXGB, "%1d: %08x %08x %08x %08x", 310 i, (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 311 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 312 tcb += 2; 313 CTR4(KTR_CXGB, " %08x %08x %08x %08x", 314 (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 315 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 316 tcb += 2; 317 } 318 } 319 320 static __inline char 321 t3rev2char(struct adapter *adapter) 322 { 323 char rev = 'z'; 324 325 switch(adapter->params.rev) { 326 case T3_REV_A: 327 rev = 'a'; 328 break; 329 case T3_REV_B: 330 case T3_REV_B2: 331 rev = 'b'; 332 break; 333 case T3_REV_C: 334 rev = 'c'; 335 break; 336 } 337 return rev; 338 } 339 340 static struct cxgb_ident * 341 cxgb_get_ident(device_t dev) 342 { 343 struct cxgb_ident *id; 344 345 for (id = cxgb_identifiers; id->desc != NULL; id++) { 346 if ((id->vendor == pci_get_vendor(dev)) && 347 (id->device == pci_get_device(dev))) { 348 return (id); 349 } 350 } 351 return (NULL); 352 } 353 354 static const struct adapter_info * 355 cxgb_get_adapter_info(device_t dev) 356 { 357 struct cxgb_ident *id; 358 const struct adapter_info *ai; 359 360 id = cxgb_get_ident(dev); 361 if (id == NULL) 362 return (NULL); 363 364 ai = t3_get_adapter_info(id->index); 365 366 return (ai); 367 } 368 369 static int 370 cxgb_controller_probe(device_t dev) 371 { 372 const struct adapter_info *ai; 373 char *ports, buf[80]; 374 int nports; 375 376 ai = cxgb_get_adapter_info(dev); 377 if (ai == NULL) 378 return (ENXIO); 379 380 nports = ai->nports0 + ai->nports1; 381 if (nports == 1) 382 ports = "port"; 383 else 384 ports = "ports"; 385 386 snprintf(buf, sizeof(buf), "%s RNIC, %d %s", ai->desc, nports, ports); 387 device_set_desc_copy(dev, buf); 388 return (BUS_PROBE_DEFAULT); 389 } 390 391 #define FW_FNAME "cxgb_t3fw" 392 #define TPEEPROM_NAME "t3b_tp_eeprom" 393 #define TPSRAM_NAME "t3b_protocol_sram" 394 395 static int 396 upgrade_fw(adapter_t *sc) 397 { 398 #ifdef FIRMWARE_LATEST 399 const struct firmware *fw; 400 #else 401 struct firmware *fw; 402 #endif 403 int status; 404 405 if ((fw = firmware_get(FW_FNAME)) == NULL) { 406 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 407 return (ENOENT); 408 } else 409 device_printf(sc->dev, "updating firmware on card\n"); 410 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 411 412 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 413 414 firmware_put(fw, FIRMWARE_UNLOAD); 415 416 return (status); 417 } 418 419 static int 420 cxgb_controller_attach(device_t dev) 421 { 422 device_t child; 423 const struct adapter_info *ai; 424 struct adapter *sc; 425 int i, error = 0; 426 uint32_t vers; 427 int port_qsets = 1; 428 #ifdef MSI_SUPPORTED 429 int msi_needed, reg; 430 #endif 431 int must_load = 0; 432 sc = device_get_softc(dev); 433 sc->dev = dev; 434 sc->msi_count = 0; 435 ai = cxgb_get_adapter_info(dev); 436 437 /* 438 * XXX not really related but a recent addition 439 */ 440 #ifdef MSI_SUPPORTED 441 /* find the PCIe link width and set max read request to 4KB*/ 442 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 443 uint16_t lnk, pectl; 444 lnk = pci_read_config(dev, reg + 0x12, 2); 445 sc->link_width = (lnk >> 4) & 0x3f; 446 447 pectl = pci_read_config(dev, reg + 0x8, 2); 448 pectl = (pectl & ~0x7000) | (5 << 12); 449 pci_write_config(dev, reg + 0x8, pectl, 2); 450 } 451 452 if (sc->link_width != 0 && sc->link_width <= 4 && 453 (ai->nports0 + ai->nports1) <= 2) { 454 device_printf(sc->dev, 455 "PCIe x%d Link, expect reduced performance\n", 456 sc->link_width); 457 } 458 #endif 459 touch_bars(dev); 460 pci_enable_busmaster(dev); 461 /* 462 * Allocate the registers and make them available to the driver. 463 * The registers that we care about for NIC mode are in BAR 0 464 */ 465 sc->regs_rid = PCIR_BAR(0); 466 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 467 &sc->regs_rid, RF_ACTIVE)) == NULL) { 468 device_printf(dev, "Cannot allocate BAR region 0\n"); 469 return (ENXIO); 470 } 471 sc->udbs_rid = PCIR_BAR(2); 472 if ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 473 &sc->udbs_rid, RF_ACTIVE)) == NULL) { 474 device_printf(dev, "Cannot allocate BAR region 1\n"); 475 error = ENXIO; 476 goto out; 477 } 478 479 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 480 device_get_unit(dev)); 481 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 482 483 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 484 device_get_unit(dev)); 485 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 486 device_get_unit(dev)); 487 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 488 device_get_unit(dev)); 489 490 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 491 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 492 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 493 494 sc->bt = rman_get_bustag(sc->regs_res); 495 sc->bh = rman_get_bushandle(sc->regs_res); 496 sc->mmio_len = rman_get_size(sc->regs_res); 497 498 if (t3_prep_adapter(sc, ai, 1) < 0) { 499 printf("prep adapter failed\n"); 500 error = ENODEV; 501 goto out; 502 } 503 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 504 * enough messages for the queue sets. If that fails, try falling 505 * back to MSI. If that fails, then try falling back to the legacy 506 * interrupt pin model. 507 */ 508 #ifdef MSI_SUPPORTED 509 510 sc->msix_regs_rid = 0x20; 511 if ((msi_allowed >= 2) && 512 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 513 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 514 515 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 516 517 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 518 (sc->msi_count != msi_needed)) { 519 device_printf(dev, "msix allocation failed - msi_count = %d" 520 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 521 msi_needed, error); 522 sc->msi_count = 0; 523 pci_release_msi(dev); 524 bus_release_resource(dev, SYS_RES_MEMORY, 525 sc->msix_regs_rid, sc->msix_regs_res); 526 sc->msix_regs_res = NULL; 527 } else { 528 sc->flags |= USING_MSIX; 529 sc->cxgb_intr = t3_intr_msix; 530 } 531 } 532 533 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 534 sc->msi_count = 1; 535 if (pci_alloc_msi(dev, &sc->msi_count)) { 536 device_printf(dev, "alloc msi failed - will try INTx\n"); 537 sc->msi_count = 0; 538 pci_release_msi(dev); 539 } else { 540 sc->flags |= USING_MSI; 541 sc->irq_rid = 1; 542 sc->cxgb_intr = t3_intr_msi; 543 } 544 } 545 #endif 546 if (sc->msi_count == 0) { 547 device_printf(dev, "using line interrupts\n"); 548 sc->irq_rid = 0; 549 sc->cxgb_intr = t3b_intr; 550 } 551 552 if ((sc->flags & USING_MSIX) && !singleq) 553 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 554 555 /* Create a private taskqueue thread for handling driver events */ 556 #ifdef TASKQUEUE_CURRENT 557 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 558 taskqueue_thread_enqueue, &sc->tq); 559 #else 560 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 561 taskqueue_thread_enqueue, &sc->tq); 562 #endif 563 if (sc->tq == NULL) { 564 device_printf(dev, "failed to allocate controller task queue\n"); 565 goto out; 566 } 567 568 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 569 device_get_nameunit(dev)); 570 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 571 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 572 573 574 /* Create a periodic callout for checking adapter status */ 575 callout_init(&sc->cxgb_tick_ch, TRUE); 576 577 if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) { 578 /* 579 * Warn user that a firmware update will be attempted in init. 580 */ 581 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 582 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 583 sc->flags &= ~FW_UPTODATE; 584 } else { 585 sc->flags |= FW_UPTODATE; 586 } 587 588 if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) { 589 /* 590 * Warn user that a firmware update will be attempted in init. 591 */ 592 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 593 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 594 sc->flags &= ~TPS_UPTODATE; 595 } else { 596 sc->flags |= TPS_UPTODATE; 597 } 598 599 /* 600 * Create a child device for each MAC. The ethernet attachment 601 * will be done in these children. 602 */ 603 for (i = 0; i < (sc)->params.nports; i++) { 604 struct port_info *pi; 605 606 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 607 device_printf(dev, "failed to add child port\n"); 608 error = EINVAL; 609 goto out; 610 } 611 pi = &sc->port[i]; 612 pi->adapter = sc; 613 pi->nqsets = port_qsets; 614 pi->first_qset = i*port_qsets; 615 pi->port_id = i; 616 pi->tx_chan = i >= ai->nports0; 617 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 618 sc->rxpkt_map[pi->txpkt_intf] = i; 619 sc->port[i].tx_chan = i >= ai->nports0; 620 sc->portdev[i] = child; 621 device_set_softc(child, pi); 622 } 623 if ((error = bus_generic_attach(dev)) != 0) 624 goto out; 625 626 /* 627 * XXX need to poll for link status 628 */ 629 sc->params.stats_update_period = 1; 630 631 /* initialize sge private state */ 632 t3_sge_init_adapter(sc); 633 634 t3_led_ready(sc); 635 636 cxgb_offload_init(); 637 if (is_offload(sc)) { 638 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 639 cxgb_adapter_ofld(sc); 640 } 641 error = t3_get_fw_version(sc, &vers); 642 if (error) 643 goto out; 644 645 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 646 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 647 G_FW_VERSION_MICRO(vers)); 648 649 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 650 callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); 651 t3_add_attach_sysctls(sc); 652 out: 653 if (error) 654 cxgb_free(sc); 655 656 return (error); 657 } 658 659 static int 660 cxgb_controller_detach(device_t dev) 661 { 662 struct adapter *sc; 663 664 sc = device_get_softc(dev); 665 666 cxgb_free(sc); 667 668 return (0); 669 } 670 671 static void 672 cxgb_free(struct adapter *sc) 673 { 674 int i; 675 676 ADAPTER_LOCK(sc); 677 sc->flags |= CXGB_SHUTDOWN; 678 ADAPTER_UNLOCK(sc); 679 cxgb_pcpu_shutdown_threads(sc); 680 ADAPTER_LOCK(sc); 681 682 /* 683 * drops the lock 684 */ 685 cxgb_down_locked(sc); 686 687 #ifdef MSI_SUPPORTED 688 if (sc->flags & (USING_MSI | USING_MSIX)) { 689 device_printf(sc->dev, "releasing msi message(s)\n"); 690 pci_release_msi(sc->dev); 691 } else { 692 device_printf(sc->dev, "no msi message to release\n"); 693 } 694 #endif 695 if (sc->msix_regs_res != NULL) { 696 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 697 sc->msix_regs_res); 698 } 699 700 t3_sge_deinit_sw(sc); 701 /* 702 * Wait for last callout 703 */ 704 705 DELAY(hz*100); 706 707 for (i = 0; i < (sc)->params.nports; ++i) { 708 if (sc->portdev[i] != NULL) 709 device_delete_child(sc->dev, sc->portdev[i]); 710 } 711 712 bus_generic_detach(sc->dev); 713 if (sc->tq != NULL) { 714 taskqueue_free(sc->tq); 715 sc->tq = NULL; 716 } 717 718 if (is_offload(sc)) { 719 cxgb_adapter_unofld(sc); 720 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 721 offload_close(&sc->tdev); 722 else 723 printf("cxgb_free: DEVMAP_BIT not set\n"); 724 } else 725 printf("not offloading set\n"); 726 727 if (sc->flags & CXGB_OFLD_INIT) 728 cxgb_offload_deactivate(sc); 729 free(sc->filters, M_DEVBUF); 730 t3_sge_free(sc); 731 732 cxgb_offload_exit(); 733 734 if (sc->udbs_res != NULL) 735 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 736 sc->udbs_res); 737 738 if (sc->regs_res != NULL) 739 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 740 sc->regs_res); 741 742 MTX_DESTROY(&sc->mdio_lock); 743 MTX_DESTROY(&sc->sge.reg_lock); 744 MTX_DESTROY(&sc->elmer_lock); 745 ADAPTER_LOCK_DEINIT(sc); 746 } 747 748 /** 749 * setup_sge_qsets - configure SGE Tx/Rx/response queues 750 * @sc: the controller softc 751 * 752 * Determines how many sets of SGE queues to use and initializes them. 753 * We support multiple queue sets per port if we have MSI-X, otherwise 754 * just one queue set per port. 755 */ 756 static int 757 setup_sge_qsets(adapter_t *sc) 758 { 759 int i, j, err, irq_idx = 0, qset_idx = 0; 760 u_int ntxq = SGE_TXQ_PER_SET; 761 762 if ((err = t3_sge_alloc(sc)) != 0) { 763 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 764 return (err); 765 } 766 767 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 768 irq_idx = -1; 769 770 for (i = 0; i < (sc)->params.nports; i++) { 771 struct port_info *pi = &sc->port[i]; 772 773 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 774 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 775 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 776 &sc->params.sge.qset[qset_idx], ntxq, pi); 777 if (err) { 778 t3_free_sge_resources(sc); 779 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 780 err); 781 return (err); 782 } 783 } 784 } 785 786 return (0); 787 } 788 789 static void 790 cxgb_teardown_msix(adapter_t *sc) 791 { 792 int i, nqsets; 793 794 for (nqsets = i = 0; i < (sc)->params.nports; i++) 795 nqsets += sc->port[i].nqsets; 796 797 for (i = 0; i < nqsets; i++) { 798 if (sc->msix_intr_tag[i] != NULL) { 799 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 800 sc->msix_intr_tag[i]); 801 sc->msix_intr_tag[i] = NULL; 802 } 803 if (sc->msix_irq_res[i] != NULL) { 804 bus_release_resource(sc->dev, SYS_RES_IRQ, 805 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 806 sc->msix_irq_res[i] = NULL; 807 } 808 } 809 } 810 811 static int 812 cxgb_setup_msix(adapter_t *sc, int msix_count) 813 { 814 int i, j, k, nqsets, rid; 815 816 /* The first message indicates link changes and error conditions */ 817 sc->irq_rid = 1; 818 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 819 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 820 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 821 return (EINVAL); 822 } 823 824 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 825 #ifdef INTR_FILTERS 826 NULL, 827 #endif 828 cxgb_async_intr, sc, &sc->intr_tag)) { 829 device_printf(sc->dev, "Cannot set up interrupt\n"); 830 return (EINVAL); 831 } 832 for (i = k = 0; i < (sc)->params.nports; i++) { 833 nqsets = sc->port[i].nqsets; 834 for (j = 0; j < nqsets; j++, k++) { 835 struct sge_qset *qs = &sc->sge.qs[k]; 836 837 rid = k + 2; 838 if (cxgb_debug) 839 printf("rid=%d ", rid); 840 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 841 sc->dev, SYS_RES_IRQ, &rid, 842 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 843 device_printf(sc->dev, "Cannot allocate " 844 "interrupt for message %d\n", rid); 845 return (EINVAL); 846 } 847 sc->msix_irq_rid[k] = rid; 848 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 849 INTR_MPSAFE|INTR_TYPE_NET, 850 #ifdef INTR_FILTERS 851 NULL, 852 #endif 853 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 854 device_printf(sc->dev, "Cannot set up " 855 "interrupt for message %d\n", rid); 856 return (EINVAL); 857 } 858 #ifdef IFNET_MULTIQUEUE 859 if (singleq == 0) { 860 int vector = rman_get_start(sc->msix_irq_res[k]); 861 if (bootverbose) 862 device_printf(sc->dev, "binding vector=%d to cpu=%d\n", vector, k % mp_ncpus); 863 intr_bind(vector, k % mp_ncpus); 864 } 865 #endif 866 } 867 } 868 869 return (0); 870 } 871 872 static int 873 cxgb_port_probe(device_t dev) 874 { 875 struct port_info *p; 876 char buf[80]; 877 const char *desc; 878 879 p = device_get_softc(dev); 880 desc = p->phy.desc; 881 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 882 device_set_desc_copy(dev, buf); 883 return (0); 884 } 885 886 887 static int 888 cxgb_makedev(struct port_info *pi) 889 { 890 891 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 892 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 893 894 if (pi->port_cdev == NULL) 895 return (ENOMEM); 896 897 pi->port_cdev->si_drv1 = (void *)pi; 898 899 return (0); 900 } 901 902 903 #ifdef TSO_SUPPORTED 904 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU) 905 /* Don't enable TSO6 yet */ 906 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU) 907 #else 908 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 909 /* Don't enable TSO6 yet */ 910 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 911 #define IFCAP_TSO4 0x0 912 #define IFCAP_TSO6 0x0 913 #define CSUM_TSO 0x0 914 #endif 915 916 917 static int 918 cxgb_port_attach(device_t dev) 919 { 920 struct port_info *p; 921 struct ifnet *ifp; 922 int err, media_flags; 923 struct adapter *sc; 924 925 926 p = device_get_softc(dev); 927 sc = p->adapter; 928 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 929 device_get_unit(device_get_parent(dev)), p->port_id); 930 PORT_LOCK_INIT(p, p->lockbuf); 931 932 /* Allocate an ifnet object and set it up */ 933 ifp = p->ifp = if_alloc(IFT_ETHER); 934 if (ifp == NULL) { 935 device_printf(dev, "Cannot allocate ifnet\n"); 936 return (ENOMEM); 937 } 938 939 /* 940 * Note that there is currently no watchdog timer. 941 */ 942 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 943 ifp->if_init = cxgb_init; 944 ifp->if_softc = p; 945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 946 ifp->if_ioctl = cxgb_ioctl; 947 ifp->if_start = cxgb_start; 948 949 #if 0 950 #ifdef IFNET_MULTIQUEUE 951 ifp->if_flags |= IFF_MULTIQ; 952 ifp->if_mq_start = cxgb_pcpu_start; 953 #endif 954 #endif 955 ifp->if_timer = 0; /* Disable ifnet watchdog */ 956 ifp->if_watchdog = NULL; 957 958 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 959 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 960 IFQ_SET_READY(&ifp->if_snd); 961 962 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 963 ifp->if_capabilities |= CXGB_CAP; 964 ifp->if_capenable |= CXGB_CAP_ENABLE; 965 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 966 /* 967 * disable TSO on 4-port - it isn't supported by the firmware yet 968 */ 969 if (p->adapter->params.nports > 2) { 970 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 971 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 972 ifp->if_hwassist &= ~CSUM_TSO; 973 } 974 975 ether_ifattach(ifp, p->hw_addr); 976 /* 977 * Only default to jumbo frames on 10GigE 978 */ 979 if (p->adapter->params.nports <= 2) 980 ifp->if_mtu = 9000; 981 if ((err = cxgb_makedev(p)) != 0) { 982 printf("makedev failed %d\n", err); 983 return (err); 984 } 985 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 986 cxgb_media_status); 987 988 if (!strcmp(p->phy.desc, "10GBASE-CX4")) { 989 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 990 } else if (!strcmp(p->phy.desc, "10GBASE-SR")) { 991 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 992 } else if (!strcmp(p->phy.desc, "10GBASE-R")) { 993 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 994 } else if (!strcmp(p->phy.desc, "10/100/1000BASE-T")) { 995 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 996 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 997 0, NULL); 998 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 999 0, NULL); 1000 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1001 0, NULL); 1002 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1003 0, NULL); 1004 media_flags = 0; 1005 } else { 1006 printf("unsupported media type %s\n", p->phy.desc); 1007 return (ENXIO); 1008 } 1009 if (media_flags) { 1010 ifmedia_add(&p->media, media_flags, 0, NULL); 1011 ifmedia_set(&p->media, media_flags); 1012 } else { 1013 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1014 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1015 } 1016 1017 1018 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id); 1019 #ifdef TASKQUEUE_CURRENT 1020 /* Create a port for handling TX without starvation */ 1021 p->tq = taskqueue_create(p->taskqbuf, M_NOWAIT, 1022 taskqueue_thread_enqueue, &p->tq); 1023 #else 1024 /* Create a port for handling TX without starvation */ 1025 p->tq = taskqueue_create_fast(p->taskqbuf, M_NOWAIT, 1026 taskqueue_thread_enqueue, &p->tq); 1027 #endif 1028 /* Get the latest mac address, User can use a LAA */ 1029 bcopy(IF_LLADDR(p->ifp), p->hw_addr, ETHER_ADDR_LEN); 1030 t3_sge_init_port(p); 1031 #if defined(LINK_ATTACH) 1032 cxgb_link_start(p); 1033 t3_link_changed(sc, p->port_id); 1034 #endif 1035 return (0); 1036 } 1037 1038 static int 1039 cxgb_port_detach(device_t dev) 1040 { 1041 struct port_info *p; 1042 1043 p = device_get_softc(dev); 1044 1045 PORT_LOCK(p); 1046 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1047 cxgb_stop_locked(p); 1048 PORT_UNLOCK(p); 1049 1050 if (p->tq != NULL) { 1051 taskqueue_drain(p->tq, &p->start_task); 1052 taskqueue_free(p->tq); 1053 p->tq = NULL; 1054 } 1055 1056 ether_ifdetach(p->ifp); 1057 printf("waiting for callout to stop ..."); 1058 DELAY(1000000); 1059 printf("done\n"); 1060 /* 1061 * the lock may be acquired in ifdetach 1062 */ 1063 PORT_LOCK_DEINIT(p); 1064 if_free(p->ifp); 1065 1066 if (p->port_cdev != NULL) 1067 destroy_dev(p->port_cdev); 1068 1069 return (0); 1070 } 1071 1072 void 1073 t3_fatal_err(struct adapter *sc) 1074 { 1075 u_int fw_status[4]; 1076 1077 if (sc->flags & FULL_INIT_DONE) { 1078 t3_sge_stop(sc); 1079 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1080 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1081 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1082 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1083 t3_intr_disable(sc); 1084 } 1085 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1086 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1087 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1088 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1089 } 1090 1091 int 1092 t3_os_find_pci_capability(adapter_t *sc, int cap) 1093 { 1094 device_t dev; 1095 struct pci_devinfo *dinfo; 1096 pcicfgregs *cfg; 1097 uint32_t status; 1098 uint8_t ptr; 1099 1100 dev = sc->dev; 1101 dinfo = device_get_ivars(dev); 1102 cfg = &dinfo->cfg; 1103 1104 status = pci_read_config(dev, PCIR_STATUS, 2); 1105 if (!(status & PCIM_STATUS_CAPPRESENT)) 1106 return (0); 1107 1108 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1109 case 0: 1110 case 1: 1111 ptr = PCIR_CAP_PTR; 1112 break; 1113 case 2: 1114 ptr = PCIR_CAP_PTR_2; 1115 break; 1116 default: 1117 return (0); 1118 break; 1119 } 1120 ptr = pci_read_config(dev, ptr, 1); 1121 1122 while (ptr != 0) { 1123 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1124 return (ptr); 1125 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1126 } 1127 1128 return (0); 1129 } 1130 1131 int 1132 t3_os_pci_save_state(struct adapter *sc) 1133 { 1134 device_t dev; 1135 struct pci_devinfo *dinfo; 1136 1137 dev = sc->dev; 1138 dinfo = device_get_ivars(dev); 1139 1140 pci_cfg_save(dev, dinfo, 0); 1141 return (0); 1142 } 1143 1144 int 1145 t3_os_pci_restore_state(struct adapter *sc) 1146 { 1147 device_t dev; 1148 struct pci_devinfo *dinfo; 1149 1150 dev = sc->dev; 1151 dinfo = device_get_ivars(dev); 1152 1153 pci_cfg_restore(dev, dinfo); 1154 return (0); 1155 } 1156 1157 /** 1158 * t3_os_link_changed - handle link status changes 1159 * @adapter: the adapter associated with the link change 1160 * @port_id: the port index whose limk status has changed 1161 * @link_status: the new status of the link 1162 * @speed: the new speed setting 1163 * @duplex: the new duplex setting 1164 * @fc: the new flow-control setting 1165 * 1166 * This is the OS-dependent handler for link status changes. The OS 1167 * neutral handler takes care of most of the processing for these events, 1168 * then calls this handler for any OS-specific processing. 1169 */ 1170 void 1171 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1172 int duplex, int fc) 1173 { 1174 struct port_info *pi = &adapter->port[port_id]; 1175 struct cmac *mac = &adapter->port[port_id].mac; 1176 1177 if (link_status) { 1178 DELAY(10); 1179 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1180 /* Clear errors created by MAC enable */ 1181 t3_set_reg_field(adapter, 1182 A_XGM_STAT_CTRL + pi->mac.offset, 1183 F_CLRSTATS, 1); 1184 if_link_state_change(pi->ifp, LINK_STATE_UP); 1185 1186 } else { 1187 pi->phy.ops->power_down(&pi->phy, 1); 1188 t3_mac_disable(mac, MAC_DIRECTION_RX); 1189 t3_link_start(&pi->phy, mac, &pi->link_config); 1190 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1191 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1192 } 1193 } 1194 1195 /* 1196 * Interrupt-context handler for external (PHY) interrupts. 1197 */ 1198 void 1199 t3_os_ext_intr_handler(adapter_t *sc) 1200 { 1201 if (cxgb_debug) 1202 printf("t3_os_ext_intr_handler\n"); 1203 /* 1204 * Schedule a task to handle external interrupts as they may be slow 1205 * and we use a mutex to protect MDIO registers. We disable PHY 1206 * interrupts in the meantime and let the task reenable them when 1207 * it's done. 1208 */ 1209 ADAPTER_LOCK(sc); 1210 if (sc->slow_intr_mask) { 1211 sc->slow_intr_mask &= ~F_T3DBG; 1212 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1213 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1214 } 1215 ADAPTER_UNLOCK(sc); 1216 } 1217 1218 void 1219 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1220 { 1221 1222 /* 1223 * The ifnet might not be allocated before this gets called, 1224 * as this is called early on in attach by t3_prep_adapter 1225 * save the address off in the port structure 1226 */ 1227 if (cxgb_debug) 1228 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1229 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1230 } 1231 1232 /** 1233 * link_start - enable a port 1234 * @p: the port to enable 1235 * 1236 * Performs the MAC and PHY actions needed to enable a port. 1237 */ 1238 static void 1239 cxgb_link_start(struct port_info *p) 1240 { 1241 struct ifnet *ifp; 1242 struct t3_rx_mode rm; 1243 struct cmac *mac = &p->mac; 1244 1245 ifp = p->ifp; 1246 1247 t3_init_rx_mode(&rm, p); 1248 if (!mac->multiport) 1249 t3_mac_reset(mac); 1250 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1251 t3_mac_set_address(mac, 0, p->hw_addr); 1252 t3_mac_set_rx_mode(mac, &rm); 1253 t3_link_start(&p->phy, mac, &p->link_config); 1254 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1255 } 1256 1257 1258 static int 1259 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1260 unsigned long n) 1261 { 1262 int attempts = 5; 1263 1264 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1265 if (!--attempts) 1266 return (ETIMEDOUT); 1267 t3_os_sleep(10); 1268 } 1269 return 0; 1270 } 1271 1272 static int 1273 init_tp_parity(struct adapter *adap) 1274 { 1275 int i; 1276 struct mbuf *m; 1277 struct cpl_set_tcb_field *greq; 1278 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1279 1280 t3_tp_set_offload_mode(adap, 1); 1281 1282 for (i = 0; i < 16; i++) { 1283 struct cpl_smt_write_req *req; 1284 1285 m = m_gethdr(M_WAITOK, MT_DATA); 1286 req = mtod(m, struct cpl_smt_write_req *); 1287 m->m_len = m->m_pkthdr.len = sizeof(*req); 1288 memset(req, 0, sizeof(*req)); 1289 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1290 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1291 req->iff = i; 1292 t3_mgmt_tx(adap, m); 1293 } 1294 1295 for (i = 0; i < 2048; i++) { 1296 struct cpl_l2t_write_req *req; 1297 1298 m = m_gethdr(M_WAITOK, MT_DATA); 1299 req = mtod(m, struct cpl_l2t_write_req *); 1300 m->m_len = m->m_pkthdr.len = sizeof(*req); 1301 memset(req, 0, sizeof(*req)); 1302 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1303 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1304 req->params = htonl(V_L2T_W_IDX(i)); 1305 t3_mgmt_tx(adap, m); 1306 } 1307 1308 for (i = 0; i < 2048; i++) { 1309 struct cpl_rte_write_req *req; 1310 1311 m = m_gethdr(M_WAITOK, MT_DATA); 1312 req = mtod(m, struct cpl_rte_write_req *); 1313 m->m_len = m->m_pkthdr.len = sizeof(*req); 1314 memset(req, 0, sizeof(*req)); 1315 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1316 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1317 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1318 t3_mgmt_tx(adap, m); 1319 } 1320 1321 m = m_gethdr(M_WAITOK, MT_DATA); 1322 greq = mtod(m, struct cpl_set_tcb_field *); 1323 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1324 memset(greq, 0, sizeof(*greq)); 1325 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1326 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1327 greq->mask = htobe64(1); 1328 t3_mgmt_tx(adap, m); 1329 1330 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1331 t3_tp_set_offload_mode(adap, 0); 1332 return (i); 1333 } 1334 1335 /** 1336 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1337 * @adap: the adapter 1338 * 1339 * Sets up RSS to distribute packets to multiple receive queues. We 1340 * configure the RSS CPU lookup table to distribute to the number of HW 1341 * receive queues, and the response queue lookup table to narrow that 1342 * down to the response queues actually configured for each port. 1343 * We always configure the RSS mapping for two ports since the mapping 1344 * table has plenty of entries. 1345 */ 1346 static void 1347 setup_rss(adapter_t *adap) 1348 { 1349 int i; 1350 u_int nq[2]; 1351 uint8_t cpus[SGE_QSETS + 1]; 1352 uint16_t rspq_map[RSS_TABLE_SIZE]; 1353 1354 for (i = 0; i < SGE_QSETS; ++i) 1355 cpus[i] = i; 1356 cpus[SGE_QSETS] = 0xff; 1357 1358 nq[0] = nq[1] = 0; 1359 for_each_port(adap, i) { 1360 const struct port_info *pi = adap2pinfo(adap, i); 1361 1362 nq[pi->tx_chan] += pi->nqsets; 1363 } 1364 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1365 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1366 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1367 } 1368 /* Calculate the reverse RSS map table */ 1369 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1370 if (adap->rrss_map[rspq_map[i]] == 0xff) 1371 adap->rrss_map[rspq_map[i]] = i; 1372 1373 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1374 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1375 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1376 cpus, rspq_map); 1377 1378 } 1379 1380 /* 1381 * Sends an mbuf to an offload queue driver 1382 * after dealing with any active network taps. 1383 */ 1384 static inline int 1385 offload_tx(struct t3cdev *tdev, struct mbuf *m) 1386 { 1387 int ret; 1388 1389 ret = t3_offload_tx(tdev, m); 1390 return (ret); 1391 } 1392 1393 static int 1394 write_smt_entry(struct adapter *adapter, int idx) 1395 { 1396 struct port_info *pi = &adapter->port[idx]; 1397 struct cpl_smt_write_req *req; 1398 struct mbuf *m; 1399 1400 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1401 return (ENOMEM); 1402 1403 req = mtod(m, struct cpl_smt_write_req *); 1404 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1405 1406 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1407 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1408 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1409 req->iff = idx; 1410 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1411 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1412 1413 m_set_priority(m, 1); 1414 1415 offload_tx(&adapter->tdev, m); 1416 1417 return (0); 1418 } 1419 1420 static int 1421 init_smt(struct adapter *adapter) 1422 { 1423 int i; 1424 1425 for_each_port(adapter, i) 1426 write_smt_entry(adapter, i); 1427 return 0; 1428 } 1429 1430 static void 1431 init_port_mtus(adapter_t *adapter) 1432 { 1433 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1434 1435 if (adapter->port[1].ifp) 1436 mtus |= adapter->port[1].ifp->if_mtu << 16; 1437 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1438 } 1439 1440 static void 1441 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1442 int hi, int port) 1443 { 1444 struct mbuf *m; 1445 struct mngt_pktsched_wr *req; 1446 1447 m = m_gethdr(M_DONTWAIT, MT_DATA); 1448 if (m) { 1449 req = mtod(m, struct mngt_pktsched_wr *); 1450 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1451 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1452 req->sched = sched; 1453 req->idx = qidx; 1454 req->min = lo; 1455 req->max = hi; 1456 req->binding = port; 1457 m->m_len = m->m_pkthdr.len = sizeof(*req); 1458 t3_mgmt_tx(adap, m); 1459 } 1460 } 1461 1462 static void 1463 bind_qsets(adapter_t *sc) 1464 { 1465 int i, j; 1466 1467 cxgb_pcpu_startup_threads(sc); 1468 for (i = 0; i < (sc)->params.nports; ++i) { 1469 const struct port_info *pi = adap2pinfo(sc, i); 1470 1471 for (j = 0; j < pi->nqsets; ++j) { 1472 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1473 -1, pi->tx_chan); 1474 1475 } 1476 } 1477 } 1478 1479 static void 1480 update_tpeeprom(struct adapter *adap) 1481 { 1482 #ifdef FIRMWARE_LATEST 1483 const struct firmware *tpeeprom; 1484 #else 1485 struct firmware *tpeeprom; 1486 #endif 1487 1488 uint32_t version; 1489 unsigned int major, minor; 1490 int ret, len; 1491 char rev; 1492 1493 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1494 1495 major = G_TP_VERSION_MAJOR(version); 1496 minor = G_TP_VERSION_MINOR(version); 1497 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1498 return; 1499 1500 rev = t3rev2char(adap); 1501 1502 tpeeprom = firmware_get(TPEEPROM_NAME); 1503 if (tpeeprom == NULL) { 1504 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1505 TPEEPROM_NAME); 1506 return; 1507 } 1508 1509 len = tpeeprom->datasize - 4; 1510 1511 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1512 if (ret) 1513 goto release_tpeeprom; 1514 1515 if (len != TP_SRAM_LEN) { 1516 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", TPEEPROM_NAME, len, TP_SRAM_LEN); 1517 return; 1518 } 1519 1520 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1521 TP_SRAM_OFFSET); 1522 1523 if (!ret) { 1524 device_printf(adap->dev, 1525 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1526 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1527 } else 1528 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1529 1530 release_tpeeprom: 1531 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1532 1533 return; 1534 } 1535 1536 static int 1537 update_tpsram(struct adapter *adap) 1538 { 1539 #ifdef FIRMWARE_LATEST 1540 const struct firmware *tpsram; 1541 #else 1542 struct firmware *tpsram; 1543 #endif 1544 int ret; 1545 char rev; 1546 1547 rev = t3rev2char(adap); 1548 if (!rev) 1549 return 0; 1550 1551 update_tpeeprom(adap); 1552 1553 tpsram = firmware_get(TPSRAM_NAME); 1554 if (tpsram == NULL){ 1555 device_printf(adap->dev, "could not load TP SRAM\n"); 1556 return (EINVAL); 1557 } else 1558 device_printf(adap->dev, "updating TP SRAM\n"); 1559 1560 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1561 if (ret) 1562 goto release_tpsram; 1563 1564 ret = t3_set_proto_sram(adap, tpsram->data); 1565 if (ret) 1566 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1567 1568 release_tpsram: 1569 firmware_put(tpsram, FIRMWARE_UNLOAD); 1570 1571 return ret; 1572 } 1573 1574 /** 1575 * cxgb_up - enable the adapter 1576 * @adap: adapter being enabled 1577 * 1578 * Called when the first port is enabled, this function performs the 1579 * actions necessary to make an adapter operational, such as completing 1580 * the initialization of HW modules, and enabling interrupts. 1581 * 1582 */ 1583 static int 1584 cxgb_up(struct adapter *sc) 1585 { 1586 int err = 0; 1587 1588 if ((sc->flags & FULL_INIT_DONE) == 0) { 1589 1590 if ((sc->flags & FW_UPTODATE) == 0) 1591 if ((err = upgrade_fw(sc))) 1592 goto out; 1593 if ((sc->flags & TPS_UPTODATE) == 0) 1594 if ((err = update_tpsram(sc))) 1595 goto out; 1596 err = t3_init_hw(sc, 0); 1597 if (err) 1598 goto out; 1599 1600 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1601 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1602 1603 err = setup_sge_qsets(sc); 1604 if (err) 1605 goto out; 1606 1607 setup_rss(sc); 1608 t3_add_configured_sysctls(sc); 1609 sc->flags |= FULL_INIT_DONE; 1610 } 1611 1612 t3_intr_clear(sc); 1613 1614 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1615 if ((sc->flags & USING_MSIX) == 0) { 1616 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1617 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1618 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", 1619 sc->irq_rid); 1620 err = EINVAL; 1621 goto out; 1622 } 1623 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1624 1625 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1626 #ifdef INTR_FILTERS 1627 NULL, 1628 #endif 1629 sc->cxgb_intr, sc, &sc->intr_tag)) { 1630 device_printf(sc->dev, "Cannot set up interrupt\n"); 1631 err = EINVAL; 1632 goto irq_err; 1633 } 1634 } else { 1635 cxgb_setup_msix(sc, sc->msi_count); 1636 } 1637 1638 t3_sge_start(sc); 1639 t3_intr_enable(sc); 1640 1641 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1642 is_offload(sc) && init_tp_parity(sc) == 0) 1643 sc->flags |= TP_PARITY_INIT; 1644 1645 if (sc->flags & TP_PARITY_INIT) { 1646 t3_write_reg(sc, A_TP_INT_CAUSE, 1647 F_CMCACHEPERR | F_ARPLUTPERR); 1648 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1649 } 1650 1651 1652 if (!(sc->flags & QUEUES_BOUND)) { 1653 bind_qsets(sc); 1654 sc->flags |= QUEUES_BOUND; 1655 } 1656 out: 1657 return (err); 1658 irq_err: 1659 CH_ERR(sc, "request_irq failed, err %d\n", err); 1660 goto out; 1661 } 1662 1663 1664 /* 1665 * Release resources when all the ports and offloading have been stopped. 1666 */ 1667 static void 1668 cxgb_down_locked(struct adapter *sc) 1669 { 1670 1671 t3_sge_stop(sc); 1672 t3_intr_disable(sc); 1673 1674 if (sc->intr_tag != NULL) { 1675 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1676 sc->intr_tag = NULL; 1677 } 1678 if (sc->irq_res != NULL) { 1679 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1680 sc->irq_rid, sc->irq_res); 1681 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1682 sc->irq_res); 1683 sc->irq_res = NULL; 1684 } 1685 1686 if (sc->flags & USING_MSIX) 1687 cxgb_teardown_msix(sc); 1688 1689 callout_stop(&sc->cxgb_tick_ch); 1690 callout_stop(&sc->sge_timer_ch); 1691 callout_drain(&sc->cxgb_tick_ch); 1692 callout_drain(&sc->sge_timer_ch); 1693 1694 if (sc->tq != NULL) { 1695 printf("draining slow intr\n"); 1696 1697 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1698 printf("draining ext intr\n"); 1699 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1700 printf("draining tick task\n"); 1701 taskqueue_drain(sc->tq, &sc->tick_task); 1702 } 1703 ADAPTER_UNLOCK(sc); 1704 } 1705 1706 static int 1707 offload_open(struct port_info *pi) 1708 { 1709 struct adapter *adapter = pi->adapter; 1710 struct t3cdev *tdev = &adapter->tdev; 1711 #ifdef notyet 1712 T3CDEV(pi->ifp); 1713 #endif 1714 int adap_up = adapter->open_device_map & PORT_MASK; 1715 int err = 0; 1716 1717 CTR1(KTR_CXGB, "device_map=0x%x", adapter->open_device_map); 1718 if (atomic_cmpset_int(&adapter->open_device_map, 1719 (adapter->open_device_map & ~(1<<OFFLOAD_DEVMAP_BIT)), 1720 (adapter->open_device_map | (1<<OFFLOAD_DEVMAP_BIT))) == 0) 1721 return (0); 1722 1723 1724 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1725 printf("offload_open: DEVMAP_BIT did not get set 0x%x\n", adapter->open_device_map); 1726 ADAPTER_LOCK(pi->adapter); 1727 if (!adap_up) 1728 err = cxgb_up(adapter); 1729 ADAPTER_UNLOCK(pi->adapter); 1730 if (err) 1731 return (err); 1732 1733 t3_tp_set_offload_mode(adapter, 1); 1734 tdev->lldev = pi->ifp; 1735 err = cxgb_offload_activate(adapter); 1736 if (err) 1737 goto out; 1738 1739 init_port_mtus(adapter); 1740 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1741 adapter->params.b_wnd, 1742 adapter->params.rev == 0 ? 1743 adapter->port[0].ifp->if_mtu : 0xffff); 1744 init_smt(adapter); 1745 1746 /* Call back all registered clients */ 1747 cxgb_add_clients(tdev); 1748 1749 out: 1750 /* restore them in case the offload module has changed them */ 1751 if (err) { 1752 t3_tp_set_offload_mode(adapter, 0); 1753 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1754 cxgb_set_dummy_ops(tdev); 1755 } 1756 return (err); 1757 } 1758 1759 static int 1760 offload_close(struct t3cdev *tdev) 1761 { 1762 struct adapter *adapter = tdev2adap(tdev); 1763 1764 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1765 return (0); 1766 1767 /* Call back all registered clients */ 1768 cxgb_remove_clients(tdev); 1769 tdev->lldev = NULL; 1770 cxgb_set_dummy_ops(tdev); 1771 t3_tp_set_offload_mode(adapter, 0); 1772 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1773 1774 ADAPTER_LOCK(adapter); 1775 if (!adapter->open_device_map) 1776 cxgb_down_locked(adapter); 1777 else 1778 ADAPTER_UNLOCK(adapter); 1779 return (0); 1780 } 1781 1782 1783 static void 1784 cxgb_init(void *arg) 1785 { 1786 struct port_info *p = arg; 1787 1788 PORT_LOCK(p); 1789 cxgb_init_locked(p); 1790 PORT_UNLOCK(p); 1791 } 1792 1793 static void 1794 cxgb_init_locked(struct port_info *p) 1795 { 1796 struct ifnet *ifp; 1797 adapter_t *sc = p->adapter; 1798 int err; 1799 1800 PORT_LOCK_ASSERT_OWNED(p); 1801 ifp = p->ifp; 1802 1803 ADAPTER_LOCK(p->adapter); 1804 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1805 ADAPTER_UNLOCK(p->adapter); 1806 cxgb_stop_locked(p); 1807 return; 1808 } 1809 if (p->adapter->open_device_map == 0) { 1810 t3_intr_clear(sc); 1811 } 1812 setbit(&p->adapter->open_device_map, p->port_id); 1813 ADAPTER_UNLOCK(p->adapter); 1814 1815 if (is_offload(sc) && !ofld_disable) { 1816 err = offload_open(p); 1817 if (err) 1818 log(LOG_WARNING, 1819 "Could not initialize offload capabilities\n"); 1820 } 1821 #if !defined(LINK_ATTACH) 1822 cxgb_link_start(p); 1823 t3_link_changed(sc, p->port_id); 1824 #endif 1825 ifp->if_baudrate = p->link_config.speed * 1000000; 1826 1827 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1828 t3_port_intr_enable(sc, p->port_id); 1829 1830 t3_sge_reset_adapter(sc); 1831 1832 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1833 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1834 } 1835 1836 static void 1837 cxgb_set_rxmode(struct port_info *p) 1838 { 1839 struct t3_rx_mode rm; 1840 struct cmac *mac = &p->mac; 1841 1842 t3_init_rx_mode(&rm, p); 1843 mtx_lock(&p->adapter->mdio_lock); 1844 t3_mac_set_rx_mode(mac, &rm); 1845 mtx_unlock(&p->adapter->mdio_lock); 1846 } 1847 1848 static void 1849 cxgb_stop_locked(struct port_info *pi) 1850 { 1851 struct ifnet *ifp; 1852 1853 PORT_LOCK_ASSERT_OWNED(pi); 1854 ADAPTER_LOCK_ASSERT_NOTOWNED(pi->adapter); 1855 1856 ifp = pi->ifp; 1857 t3_port_intr_disable(pi->adapter, pi->port_id); 1858 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1859 1860 /* disable pause frames */ 1861 t3_set_reg_field(pi->adapter, A_XGM_TX_CFG + pi->mac.offset, 1862 F_TXPAUSEEN, 0); 1863 1864 /* Reset RX FIFO HWM */ 1865 t3_set_reg_field(pi->adapter, A_XGM_RXFIFO_CFG + pi->mac.offset, 1866 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1867 1868 1869 ADAPTER_LOCK(pi->adapter); 1870 clrbit(&pi->adapter->open_device_map, pi->port_id); 1871 1872 if (pi->adapter->open_device_map == 0) { 1873 cxgb_down_locked(pi->adapter); 1874 } else 1875 ADAPTER_UNLOCK(pi->adapter); 1876 1877 #if !defined(LINK_ATTACH) 1878 DELAY(100); 1879 1880 /* Wait for TXFIFO empty */ 1881 t3_wait_op_done(pi->adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 1882 F_TXFIFO_EMPTY, 1, 20, 5); 1883 1884 DELAY(100); 1885 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1886 1887 pi->phy.ops->power_down(&pi->phy, 1); 1888 #endif 1889 1890 } 1891 1892 static int 1893 cxgb_set_mtu(struct port_info *p, int mtu) 1894 { 1895 struct ifnet *ifp = p->ifp; 1896 int error = 0; 1897 1898 if ((mtu < ETHERMIN) || (mtu > ETHER_MAX_LEN_JUMBO)) 1899 error = EINVAL; 1900 else if (ifp->if_mtu != mtu) { 1901 PORT_LOCK(p); 1902 ifp->if_mtu = mtu; 1903 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1904 cxgb_stop_locked(p); 1905 cxgb_init_locked(p); 1906 } 1907 PORT_UNLOCK(p); 1908 } 1909 return (error); 1910 } 1911 1912 static int 1913 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1914 { 1915 struct port_info *p = ifp->if_softc; 1916 struct ifaddr *ifa = (struct ifaddr *)data; 1917 struct ifreq *ifr = (struct ifreq *)data; 1918 int flags, error = 0; 1919 uint32_t mask; 1920 1921 /* 1922 * XXX need to check that we aren't in the middle of an unload 1923 */ 1924 switch (command) { 1925 case SIOCSIFMTU: 1926 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1927 break; 1928 case SIOCSIFADDR: 1929 if (ifa->ifa_addr->sa_family == AF_INET) { 1930 ifp->if_flags |= IFF_UP; 1931 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1932 PORT_LOCK(p); 1933 cxgb_init_locked(p); 1934 PORT_UNLOCK(p); 1935 } 1936 arp_ifinit(ifp, ifa); 1937 } else 1938 error = ether_ioctl(ifp, command, data); 1939 break; 1940 case SIOCSIFFLAGS: 1941 PORT_LOCK(p); 1942 if (ifp->if_flags & IFF_UP) { 1943 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1944 flags = p->if_flags; 1945 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1946 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1947 cxgb_set_rxmode(p); 1948 } else 1949 cxgb_init_locked(p); 1950 p->if_flags = ifp->if_flags; 1951 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1952 cxgb_stop_locked(p); 1953 1954 PORT_UNLOCK(p); 1955 break; 1956 case SIOCADDMULTI: 1957 case SIOCDELMULTI: 1958 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1959 cxgb_set_rxmode(p); 1960 } 1961 break; 1962 case SIOCSIFMEDIA: 1963 case SIOCGIFMEDIA: 1964 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1965 break; 1966 case SIOCSIFCAP: 1967 PORT_LOCK(p); 1968 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1969 if (mask & IFCAP_TXCSUM) { 1970 if (IFCAP_TXCSUM & ifp->if_capenable) { 1971 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 1972 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 1973 | CSUM_TSO); 1974 } else { 1975 ifp->if_capenable |= IFCAP_TXCSUM; 1976 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1977 } 1978 } else if (mask & IFCAP_RXCSUM) { 1979 if (IFCAP_RXCSUM & ifp->if_capenable) { 1980 ifp->if_capenable &= ~IFCAP_RXCSUM; 1981 } else { 1982 ifp->if_capenable |= IFCAP_RXCSUM; 1983 } 1984 } 1985 if (mask & IFCAP_TSO4) { 1986 if (IFCAP_TSO4 & ifp->if_capenable) { 1987 ifp->if_capenable &= ~IFCAP_TSO4; 1988 ifp->if_hwassist &= ~CSUM_TSO; 1989 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 1990 ifp->if_capenable |= IFCAP_TSO4; 1991 ifp->if_hwassist |= CSUM_TSO; 1992 } else { 1993 if (cxgb_debug) 1994 printf("cxgb requires tx checksum offload" 1995 " be enabled to use TSO\n"); 1996 error = EINVAL; 1997 } 1998 } 1999 PORT_UNLOCK(p); 2000 break; 2001 default: 2002 error = ether_ioctl(ifp, command, data); 2003 break; 2004 } 2005 return (error); 2006 } 2007 2008 static int 2009 cxgb_media_change(struct ifnet *ifp) 2010 { 2011 if_printf(ifp, "media change not supported\n"); 2012 return (ENXIO); 2013 } 2014 2015 static void 2016 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2017 { 2018 struct port_info *p = ifp->if_softc; 2019 2020 ifmr->ifm_status = IFM_AVALID; 2021 ifmr->ifm_active = IFM_ETHER; 2022 2023 if (!p->link_config.link_ok) 2024 return; 2025 2026 ifmr->ifm_status |= IFM_ACTIVE; 2027 2028 switch (p->link_config.speed) { 2029 case 10: 2030 ifmr->ifm_active |= IFM_10_T; 2031 break; 2032 case 100: 2033 ifmr->ifm_active |= IFM_100_TX; 2034 break; 2035 case 1000: 2036 ifmr->ifm_active |= IFM_1000_T; 2037 break; 2038 } 2039 2040 if (p->link_config.duplex) 2041 ifmr->ifm_active |= IFM_FDX; 2042 else 2043 ifmr->ifm_active |= IFM_HDX; 2044 } 2045 2046 static void 2047 cxgb_async_intr(void *data) 2048 { 2049 adapter_t *sc = data; 2050 2051 if (cxgb_debug) 2052 device_printf(sc->dev, "cxgb_async_intr\n"); 2053 /* 2054 * May need to sleep - defer to taskqueue 2055 */ 2056 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2057 } 2058 2059 static void 2060 cxgb_ext_intr_handler(void *arg, int count) 2061 { 2062 adapter_t *sc = (adapter_t *)arg; 2063 2064 if (cxgb_debug) 2065 printf("cxgb_ext_intr_handler\n"); 2066 2067 t3_phy_intr_handler(sc); 2068 2069 /* Now reenable external interrupts */ 2070 ADAPTER_LOCK(sc); 2071 if (sc->slow_intr_mask) { 2072 sc->slow_intr_mask |= F_T3DBG; 2073 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2074 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2075 } 2076 ADAPTER_UNLOCK(sc); 2077 } 2078 2079 static void 2080 check_link_status(adapter_t *sc) 2081 { 2082 int i; 2083 2084 for (i = 0; i < (sc)->params.nports; ++i) { 2085 struct port_info *p = &sc->port[i]; 2086 2087 if (!(p->phy.caps & SUPPORTED_IRQ)) 2088 t3_link_changed(sc, i); 2089 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2090 } 2091 } 2092 2093 static void 2094 check_t3b2_mac(struct adapter *adapter) 2095 { 2096 int i; 2097 2098 if(adapter->flags & CXGB_SHUTDOWN) 2099 return; 2100 2101 for_each_port(adapter, i) { 2102 struct port_info *p = &adapter->port[i]; 2103 struct ifnet *ifp = p->ifp; 2104 int status; 2105 2106 if(adapter->flags & CXGB_SHUTDOWN) 2107 return; 2108 2109 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2110 continue; 2111 2112 status = 0; 2113 PORT_LOCK(p); 2114 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2115 status = t3b2_mac_watchdog_task(&p->mac); 2116 if (status == 1) 2117 p->mac.stats.num_toggled++; 2118 else if (status == 2) { 2119 struct cmac *mac = &p->mac; 2120 2121 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN 2122 + ETHER_VLAN_ENCAP_LEN); 2123 t3_mac_set_address(mac, 0, p->hw_addr); 2124 cxgb_set_rxmode(p); 2125 t3_link_start(&p->phy, mac, &p->link_config); 2126 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2127 t3_port_intr_enable(adapter, p->port_id); 2128 p->mac.stats.num_resets++; 2129 } 2130 PORT_UNLOCK(p); 2131 } 2132 } 2133 2134 static void 2135 cxgb_tick(void *arg) 2136 { 2137 adapter_t *sc = (adapter_t *)arg; 2138 2139 if(sc->flags & CXGB_SHUTDOWN) 2140 return; 2141 2142 taskqueue_enqueue(sc->tq, &sc->tick_task); 2143 callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); 2144 } 2145 2146 static void 2147 cxgb_tick_handler(void *arg, int count) 2148 { 2149 adapter_t *sc = (adapter_t *)arg; 2150 const struct adapter_params *p = &sc->params; 2151 2152 if(sc->flags & CXGB_SHUTDOWN) 2153 return; 2154 2155 ADAPTER_LOCK(sc); 2156 if (p->linkpoll_period) 2157 check_link_status(sc); 2158 2159 /* 2160 * adapter lock can currently only be acquired after the 2161 * port lock 2162 */ 2163 ADAPTER_UNLOCK(sc); 2164 2165 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2166 check_t3b2_mac(sc); 2167 } 2168 2169 static void 2170 touch_bars(device_t dev) 2171 { 2172 /* 2173 * Don't enable yet 2174 */ 2175 #if !defined(__LP64__) && 0 2176 u32 v; 2177 2178 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2179 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2180 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2181 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2182 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2183 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2184 #endif 2185 } 2186 2187 static int 2188 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2189 { 2190 uint8_t *buf; 2191 int err = 0; 2192 u32 aligned_offset, aligned_len, *p; 2193 struct adapter *adapter = pi->adapter; 2194 2195 2196 aligned_offset = offset & ~3; 2197 aligned_len = (len + (offset & 3) + 3) & ~3; 2198 2199 if (aligned_offset != offset || aligned_len != len) { 2200 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2201 if (!buf) 2202 return (ENOMEM); 2203 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2204 if (!err && aligned_len > 4) 2205 err = t3_seeprom_read(adapter, 2206 aligned_offset + aligned_len - 4, 2207 (u32 *)&buf[aligned_len - 4]); 2208 if (err) 2209 goto out; 2210 memcpy(buf + (offset & 3), data, len); 2211 } else 2212 buf = (uint8_t *)(uintptr_t)data; 2213 2214 err = t3_seeprom_wp(adapter, 0); 2215 if (err) 2216 goto out; 2217 2218 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2219 err = t3_seeprom_write(adapter, aligned_offset, *p); 2220 aligned_offset += 4; 2221 } 2222 2223 if (!err) 2224 err = t3_seeprom_wp(adapter, 1); 2225 out: 2226 if (buf != data) 2227 free(buf, M_DEVBUF); 2228 return err; 2229 } 2230 2231 2232 static int 2233 in_range(int val, int lo, int hi) 2234 { 2235 return val < 0 || (val <= hi && val >= lo); 2236 } 2237 2238 static int 2239 cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2240 { 2241 return (0); 2242 } 2243 2244 static int 2245 cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2246 { 2247 return (0); 2248 } 2249 2250 static int 2251 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2252 int fflag, struct thread *td) 2253 { 2254 int mmd, error = 0; 2255 struct port_info *pi = dev->si_drv1; 2256 adapter_t *sc = pi->adapter; 2257 2258 #ifdef PRIV_SUPPORTED 2259 if (priv_check(td, PRIV_DRIVER)) { 2260 if (cxgb_debug) 2261 printf("user does not have access to privileged ioctls\n"); 2262 return (EPERM); 2263 } 2264 #else 2265 if (suser(td)) { 2266 if (cxgb_debug) 2267 printf("user does not have access to privileged ioctls\n"); 2268 return (EPERM); 2269 } 2270 #endif 2271 2272 switch (cmd) { 2273 case SIOCGMIIREG: { 2274 uint32_t val; 2275 struct cphy *phy = &pi->phy; 2276 struct mii_data *mid = (struct mii_data *)data; 2277 2278 if (!phy->mdio_read) 2279 return (EOPNOTSUPP); 2280 if (is_10G(sc)) { 2281 mmd = mid->phy_id >> 8; 2282 if (!mmd) 2283 mmd = MDIO_DEV_PCS; 2284 else if (mmd > MDIO_DEV_XGXS) 2285 return (EINVAL); 2286 2287 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2288 mid->reg_num, &val); 2289 } else 2290 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2291 mid->reg_num & 0x1f, &val); 2292 if (error == 0) 2293 mid->val_out = val; 2294 break; 2295 } 2296 case SIOCSMIIREG: { 2297 struct cphy *phy = &pi->phy; 2298 struct mii_data *mid = (struct mii_data *)data; 2299 2300 if (!phy->mdio_write) 2301 return (EOPNOTSUPP); 2302 if (is_10G(sc)) { 2303 mmd = mid->phy_id >> 8; 2304 if (!mmd) 2305 mmd = MDIO_DEV_PCS; 2306 else if (mmd > MDIO_DEV_XGXS) 2307 return (EINVAL); 2308 2309 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2310 mmd, mid->reg_num, mid->val_in); 2311 } else 2312 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2313 mid->reg_num & 0x1f, 2314 mid->val_in); 2315 break; 2316 } 2317 case CHELSIO_SETREG: { 2318 struct ch_reg *edata = (struct ch_reg *)data; 2319 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2320 return (EFAULT); 2321 t3_write_reg(sc, edata->addr, edata->val); 2322 break; 2323 } 2324 case CHELSIO_GETREG: { 2325 struct ch_reg *edata = (struct ch_reg *)data; 2326 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2327 return (EFAULT); 2328 edata->val = t3_read_reg(sc, edata->addr); 2329 break; 2330 } 2331 case CHELSIO_GET_SGE_CONTEXT: { 2332 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2333 mtx_lock_spin(&sc->sge.reg_lock); 2334 switch (ecntxt->cntxt_type) { 2335 case CNTXT_TYPE_EGRESS: 2336 error = t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2337 ecntxt->data); 2338 break; 2339 case CNTXT_TYPE_FL: 2340 error = t3_sge_read_fl(sc, ecntxt->cntxt_id, 2341 ecntxt->data); 2342 break; 2343 case CNTXT_TYPE_RSP: 2344 error = t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2345 ecntxt->data); 2346 break; 2347 case CNTXT_TYPE_CQ: 2348 error = t3_sge_read_cq(sc, ecntxt->cntxt_id, 2349 ecntxt->data); 2350 break; 2351 default: 2352 error = EINVAL; 2353 break; 2354 } 2355 mtx_unlock_spin(&sc->sge.reg_lock); 2356 break; 2357 } 2358 case CHELSIO_GET_SGE_DESC: { 2359 struct ch_desc *edesc = (struct ch_desc *)data; 2360 int ret; 2361 if (edesc->queue_num >= SGE_QSETS * 6) 2362 return (EINVAL); 2363 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2364 edesc->queue_num % 6, edesc->idx, edesc->data); 2365 if (ret < 0) 2366 return (EINVAL); 2367 edesc->size = ret; 2368 break; 2369 } 2370 case CHELSIO_SET_QSET_PARAMS: { 2371 struct qset_params *q; 2372 struct ch_qset_params *t = (struct ch_qset_params *)data; 2373 int i; 2374 2375 if (t->qset_idx >= SGE_QSETS) 2376 return (EINVAL); 2377 if (!in_range(t->intr_lat, 0, M_NEWTIMER) || 2378 !in_range(t->cong_thres, 0, 255) || 2379 !in_range(t->txq_size[0], MIN_TXQ_ENTRIES, 2380 MAX_TXQ_ENTRIES) || 2381 !in_range(t->txq_size[1], MIN_TXQ_ENTRIES, 2382 MAX_TXQ_ENTRIES) || 2383 !in_range(t->txq_size[2], MIN_CTRL_TXQ_ENTRIES, 2384 MAX_CTRL_TXQ_ENTRIES) || 2385 !in_range(t->fl_size[0], MIN_FL_ENTRIES, MAX_RX_BUFFERS) || 2386 !in_range(t->fl_size[1], MIN_FL_ENTRIES, 2387 MAX_RX_JUMBO_BUFFERS) || 2388 !in_range(t->rspq_size, MIN_RSPQ_ENTRIES, MAX_RSPQ_ENTRIES)) 2389 return (EINVAL); 2390 2391 if ((sc->flags & FULL_INIT_DONE) && t->lro > 0) 2392 for_each_port(sc, i) { 2393 pi = adap2pinfo(sc, i); 2394 if (t->qset_idx >= pi->first_qset && 2395 t->qset_idx < pi->first_qset + pi->nqsets 2396 #if 0 2397 && !pi->rx_csum_offload 2398 #endif 2399 ) 2400 return -EINVAL; 2401 } 2402 if ((sc->flags & FULL_INIT_DONE) && 2403 (t->rspq_size >= 0 || t->fl_size[0] >= 0 || 2404 t->fl_size[1] >= 0 || t->txq_size[0] >= 0 || 2405 t->txq_size[1] >= 0 || t->txq_size[2] >= 0 || 2406 t->polling >= 0 || t->cong_thres >= 0)) 2407 return (EBUSY); 2408 2409 q = &sc->params.sge.qset[t->qset_idx]; 2410 2411 if (t->rspq_size >= 0) 2412 q->rspq_size = t->rspq_size; 2413 if (t->fl_size[0] >= 0) 2414 q->fl_size = t->fl_size[0]; 2415 if (t->fl_size[1] >= 0) 2416 q->jumbo_size = t->fl_size[1]; 2417 if (t->txq_size[0] >= 0) 2418 q->txq_size[0] = t->txq_size[0]; 2419 if (t->txq_size[1] >= 0) 2420 q->txq_size[1] = t->txq_size[1]; 2421 if (t->txq_size[2] >= 0) 2422 q->txq_size[2] = t->txq_size[2]; 2423 if (t->cong_thres >= 0) 2424 q->cong_thres = t->cong_thres; 2425 if (t->intr_lat >= 0) { 2426 struct sge_qset *qs = &sc->sge.qs[t->qset_idx]; 2427 2428 q->coalesce_nsecs = t->intr_lat*1000; 2429 t3_update_qset_coalesce(qs, q); 2430 } 2431 break; 2432 } 2433 case CHELSIO_GET_QSET_PARAMS: { 2434 struct qset_params *q; 2435 struct ch_qset_params *t = (struct ch_qset_params *)data; 2436 2437 if (t->qset_idx >= SGE_QSETS) 2438 return (EINVAL); 2439 2440 q = &(sc)->params.sge.qset[t->qset_idx]; 2441 t->rspq_size = q->rspq_size; 2442 t->txq_size[0] = q->txq_size[0]; 2443 t->txq_size[1] = q->txq_size[1]; 2444 t->txq_size[2] = q->txq_size[2]; 2445 t->fl_size[0] = q->fl_size; 2446 t->fl_size[1] = q->jumbo_size; 2447 t->polling = q->polling; 2448 t->intr_lat = q->coalesce_nsecs / 1000; 2449 t->cong_thres = q->cong_thres; 2450 break; 2451 } 2452 case CHELSIO_SET_QSET_NUM: { 2453 struct ch_reg *edata = (struct ch_reg *)data; 2454 unsigned int port_idx = pi->port_id; 2455 2456 if (sc->flags & FULL_INIT_DONE) 2457 return (EBUSY); 2458 if (edata->val < 1 || 2459 (edata->val > 1 && !(sc->flags & USING_MSIX))) 2460 return (EINVAL); 2461 if (edata->val + sc->port[!port_idx].nqsets > SGE_QSETS) 2462 return (EINVAL); 2463 sc->port[port_idx].nqsets = edata->val; 2464 sc->port[0].first_qset = 0; 2465 /* 2466 * XXX hardcode ourselves to 2 ports just like LEEENUX 2467 */ 2468 sc->port[1].first_qset = sc->port[0].nqsets; 2469 break; 2470 } 2471 case CHELSIO_GET_QSET_NUM: { 2472 struct ch_reg *edata = (struct ch_reg *)data; 2473 edata->val = pi->nqsets; 2474 break; 2475 } 2476 #ifdef notyet 2477 case CHELSIO_LOAD_FW: 2478 case CHELSIO_GET_PM: 2479 case CHELSIO_SET_PM: 2480 return (EOPNOTSUPP); 2481 break; 2482 #endif 2483 case CHELSIO_SETMTUTAB: { 2484 struct ch_mtus *m = (struct ch_mtus *)data; 2485 int i; 2486 2487 if (!is_offload(sc)) 2488 return (EOPNOTSUPP); 2489 if (offload_running(sc)) 2490 return (EBUSY); 2491 if (m->nmtus != NMTUS) 2492 return (EINVAL); 2493 if (m->mtus[0] < 81) /* accommodate SACK */ 2494 return (EINVAL); 2495 2496 /* 2497 * MTUs must be in ascending order 2498 */ 2499 for (i = 1; i < NMTUS; ++i) 2500 if (m->mtus[i] < m->mtus[i - 1]) 2501 return (EINVAL); 2502 2503 memcpy(sc->params.mtus, m->mtus, 2504 sizeof(sc->params.mtus)); 2505 break; 2506 } 2507 case CHELSIO_GETMTUTAB: { 2508 struct ch_mtus *m = (struct ch_mtus *)data; 2509 2510 if (!is_offload(sc)) 2511 return (EOPNOTSUPP); 2512 2513 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2514 m->nmtus = NMTUS; 2515 break; 2516 } 2517 case CHELSIO_DEVUP: 2518 if (!is_offload(sc)) 2519 return (EOPNOTSUPP); 2520 return offload_open(pi); 2521 break; 2522 case CHELSIO_GET_MEM: { 2523 struct ch_mem_range *t = (struct ch_mem_range *)data; 2524 struct mc7 *mem; 2525 uint8_t *useraddr; 2526 u64 buf[32]; 2527 2528 if (!is_offload(sc)) 2529 return (EOPNOTSUPP); 2530 if (!(sc->flags & FULL_INIT_DONE)) 2531 return (EIO); /* need the memory controllers */ 2532 if ((t->addr & 0x7) || (t->len & 0x7)) 2533 return (EINVAL); 2534 if (t->mem_id == MEM_CM) 2535 mem = &sc->cm; 2536 else if (t->mem_id == MEM_PMRX) 2537 mem = &sc->pmrx; 2538 else if (t->mem_id == MEM_PMTX) 2539 mem = &sc->pmtx; 2540 else 2541 return (EINVAL); 2542 2543 /* 2544 * Version scheme: 2545 * bits 0..9: chip version 2546 * bits 10..15: chip revision 2547 */ 2548 t->version = 3 | (sc->params.rev << 10); 2549 2550 /* 2551 * Read 256 bytes at a time as len can be large and we don't 2552 * want to use huge intermediate buffers. 2553 */ 2554 useraddr = (uint8_t *)t->buf; 2555 while (t->len) { 2556 unsigned int chunk = min(t->len, sizeof(buf)); 2557 2558 error = t3_mc7_bd_read(mem, t->addr / 8, chunk / 8, buf); 2559 if (error) 2560 return (-error); 2561 if (copyout(buf, useraddr, chunk)) 2562 return (EFAULT); 2563 useraddr += chunk; 2564 t->addr += chunk; 2565 t->len -= chunk; 2566 } 2567 break; 2568 } 2569 case CHELSIO_READ_TCAM_WORD: { 2570 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2571 2572 if (!is_offload(sc)) 2573 return (EOPNOTSUPP); 2574 if (!(sc->flags & FULL_INIT_DONE)) 2575 return (EIO); /* need MC5 */ 2576 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2577 break; 2578 } 2579 case CHELSIO_SET_TRACE_FILTER: { 2580 struct ch_trace *t = (struct ch_trace *)data; 2581 const struct trace_params *tp; 2582 2583 tp = (const struct trace_params *)&t->sip; 2584 if (t->config_tx) 2585 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2586 t->trace_tx); 2587 if (t->config_rx) 2588 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2589 t->trace_rx); 2590 break; 2591 } 2592 case CHELSIO_SET_PKTSCHED: { 2593 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2594 if (sc->open_device_map == 0) 2595 return (EAGAIN); 2596 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2597 p->binding); 2598 break; 2599 } 2600 case CHELSIO_IFCONF_GETREGS: { 2601 struct ifconf_regs *regs = (struct ifconf_regs *)data; 2602 int reglen = cxgb_get_regs_len(); 2603 uint8_t *buf = malloc(REGDUMP_SIZE, M_DEVBUF, M_NOWAIT); 2604 if (buf == NULL) { 2605 return (ENOMEM); 2606 } if (regs->len > reglen) 2607 regs->len = reglen; 2608 else if (regs->len < reglen) { 2609 error = E2BIG; 2610 goto done; 2611 } 2612 cxgb_get_regs(sc, regs, buf); 2613 error = copyout(buf, regs->data, reglen); 2614 2615 done: 2616 free(buf, M_DEVBUF); 2617 2618 break; 2619 } 2620 case CHELSIO_SET_HW_SCHED: { 2621 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2622 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2623 2624 if ((sc->flags & FULL_INIT_DONE) == 0) 2625 return (EAGAIN); /* need TP to be initialized */ 2626 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2627 !in_range(t->channel, 0, 1) || 2628 !in_range(t->kbps, 0, 10000000) || 2629 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2630 !in_range(t->flow_ipg, 0, 2631 dack_ticks_to_usec(sc, 0x7ff))) 2632 return (EINVAL); 2633 2634 if (t->kbps >= 0) { 2635 error = t3_config_sched(sc, t->kbps, t->sched); 2636 if (error < 0) 2637 return (-error); 2638 } 2639 if (t->class_ipg >= 0) 2640 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2641 if (t->flow_ipg >= 0) { 2642 t->flow_ipg *= 1000; /* us -> ns */ 2643 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2644 } 2645 if (t->mode >= 0) { 2646 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2647 2648 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2649 bit, t->mode ? bit : 0); 2650 } 2651 if (t->channel >= 0) 2652 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2653 1 << t->sched, t->channel << t->sched); 2654 break; 2655 } 2656 default: 2657 return (EOPNOTSUPP); 2658 break; 2659 } 2660 2661 return (error); 2662 } 2663 2664 static __inline void 2665 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2666 unsigned int end) 2667 { 2668 uint32_t *p = (uint32_t *)buf + start; 2669 2670 for ( ; start <= end; start += sizeof(uint32_t)) 2671 *p++ = t3_read_reg(ap, start); 2672 } 2673 2674 #define T3_REGMAP_SIZE (3 * 1024) 2675 static int 2676 cxgb_get_regs_len(void) 2677 { 2678 return T3_REGMAP_SIZE; 2679 } 2680 #undef T3_REGMAP_SIZE 2681 2682 static void 2683 cxgb_get_regs(adapter_t *sc, struct ifconf_regs *regs, uint8_t *buf) 2684 { 2685 2686 /* 2687 * Version scheme: 2688 * bits 0..9: chip version 2689 * bits 10..15: chip revision 2690 * bit 31: set for PCIe cards 2691 */ 2692 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2693 2694 /* 2695 * We skip the MAC statistics registers because they are clear-on-read. 2696 * Also reading multi-register stats would need to synchronize with the 2697 * periodic mac stats accumulation. Hard to justify the complexity. 2698 */ 2699 memset(buf, 0, REGDUMP_SIZE); 2700 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2701 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2702 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2703 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2704 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2705 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2706 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2707 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2708 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2709 } 2710 2711 2712 MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 2713