1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 29 $FreeBSD$ 30 31 ***************************************************************************/ 32 33 34 #ifndef _CXGB_ADAPTER_H_ 35 #define _CXGB_ADAPTER_H_ 36 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sx.h> 40 #include <sys/rman.h> 41 #include <sys/mbuf.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/condvar.h> 45 46 #include <net/ethernet.h> 47 #include <net/if.h> 48 #include <net/if_media.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 53 #include <sys/bus_dma.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #ifdef CONFIG_DEFINED 58 #include <cxgb_osdep.h> 59 #include <t3cdev.h> 60 #include <ulp/toecore/cxgb_toedev.h> 61 #include <sys/mbufq.h> 62 #else 63 #include <dev/cxgb/cxgb_osdep.h> 64 #include <dev/cxgb/t3cdev.h> 65 #include <dev/cxgb/sys/mbufq.h> 66 #include <dev/cxgb/ulp/toecore/cxgb_toedev.h> 67 #endif 68 69 #define USE_SX 70 71 struct adapter; 72 struct sge_qset; 73 extern int cxgb_debug; 74 75 #ifdef DEBUG_LOCKING 76 #define MTX_INIT(lock, lockname, class, flags) \ 77 do { \ 78 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \ 79 mtx_init((lock), lockname, class, flags); \ 80 } while (0) 81 82 #define MTX_DESTROY(lock) \ 83 do { \ 84 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \ 85 mtx_destroy((lock)); \ 86 } while (0) 87 88 #define SX_INIT(lock, lockname) \ 89 do { \ 90 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \ 91 sx_init((lock), lockname); \ 92 } while (0) 93 94 #define SX_DESTROY(lock) \ 95 do { \ 96 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \ 97 sx_destroy((lock)); \ 98 } while (0) 99 #else 100 #define MTX_INIT mtx_init 101 #define MTX_DESTROY mtx_destroy 102 #define SX_INIT sx_init 103 #define SX_DESTROY sx_destroy 104 #endif 105 106 struct port_info { 107 struct adapter *adapter; 108 struct ifnet *ifp; 109 int if_flags; 110 const struct port_type_info *port_type; 111 struct cphy phy; 112 struct cmac mac; 113 struct link_config link_config; 114 struct ifmedia media; 115 #ifdef USE_SX 116 struct sx lock; 117 #else 118 struct mtx lock; 119 #endif 120 uint8_t port_id; 121 uint8_t tx_chan; 122 uint8_t txpkt_intf; 123 uint8_t first_qset; 124 uint32_t nqsets; 125 126 uint8_t hw_addr[ETHER_ADDR_LEN]; 127 struct taskqueue *tq; 128 struct task start_task; 129 struct task timer_reclaim_task; 130 struct cdev *port_cdev; 131 132 #define PORT_LOCK_NAME_LEN 32 133 #define TASKQ_NAME_LEN 32 134 #define PORT_NAME_LEN 32 135 char lockbuf[PORT_LOCK_NAME_LEN]; 136 char taskqbuf[TASKQ_NAME_LEN]; 137 char namebuf[PORT_NAME_LEN]; 138 }; 139 140 enum { /* adapter flags */ 141 FULL_INIT_DONE = (1 << 0), 142 USING_MSI = (1 << 1), 143 USING_MSIX = (1 << 2), 144 QUEUES_BOUND = (1 << 3), 145 FW_UPTODATE = (1 << 4), 146 TPS_UPTODATE = (1 << 5), 147 }; 148 149 #define FL_Q_SIZE 4096 150 #define JUMBO_Q_SIZE 1024 151 #define RSPQ_Q_SIZE 1024 152 #if 0 153 #define TX_ETH_Q_SIZE 1024 154 #else 155 #define TX_ETH_Q_SIZE 64 156 #endif 157 158 enum { TXQ_ETH = 0, 159 TXQ_OFLD = 1, 160 TXQ_CTRL = 2, }; 161 162 163 /* 164 * work request size in bytes 165 */ 166 #define WR_LEN (WR_FLITS * 8) 167 #define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt)) 168 169 170 /* careful, the following are set on priv_flags and must not collide with 171 * IFF_ flags! 172 */ 173 enum { 174 LRO_ACTIVE = (1 << 8), 175 }; 176 177 /* Max concurrent LRO sessions per queue set */ 178 #define MAX_LRO_SES 8 179 180 struct t3_lro_session { 181 struct mbuf *head; 182 struct mbuf *tail; 183 uint32_t seq; 184 uint16_t ip_len; 185 uint16_t mss; 186 uint16_t vtag; 187 uint8_t npkts; 188 }; 189 190 struct lro_state { 191 unsigned short enabled; 192 unsigned short active_idx; 193 unsigned int nactive; 194 struct t3_lro_session sess[MAX_LRO_SES]; 195 }; 196 197 #define RX_BUNDLE_SIZE 8 198 199 struct rsp_desc; 200 201 struct sge_rspq { 202 uint32_t credits; 203 uint32_t size; 204 uint32_t cidx; 205 uint32_t gen; 206 uint32_t polling; 207 uint32_t holdoff_tmr; 208 uint32_t next_holdoff; 209 uint32_t imm_data; 210 uint32_t cntxt_id; 211 uint32_t offload_pkts; 212 uint32_t offload_bundles; 213 uint32_t pure_rsps; 214 uint32_t unhandled_irqs; 215 216 bus_addr_t phys_addr; 217 bus_dma_tag_t desc_tag; 218 bus_dmamap_t desc_map; 219 220 struct t3_mbuf_hdr rspq_mh; 221 struct rsp_desc *desc; 222 struct mtx lock; 223 #define RSPQ_NAME_LEN 32 224 char lockbuf[RSPQ_NAME_LEN]; 225 uint32_t rspq_dump_start; 226 uint32_t rspq_dump_count; 227 }; 228 229 #ifndef DISABLE_MBUF_IOVEC 230 #define rspq_mbuf rspq_mh.mh_head 231 #endif 232 233 struct rx_desc; 234 struct rx_sw_desc; 235 236 struct sge_fl { 237 uint32_t buf_size; 238 uint32_t credits; 239 uint32_t size; 240 uint32_t cidx; 241 uint32_t pidx; 242 uint32_t gen; 243 bus_addr_t phys_addr; 244 uint32_t cntxt_id; 245 uint64_t empty; 246 bus_dma_tag_t desc_tag; 247 bus_dmamap_t desc_map; 248 bus_dma_tag_t entry_tag; 249 uma_zone_t zone; 250 struct rx_desc *desc; 251 struct rx_sw_desc *sdesc; 252 int type; 253 }; 254 255 struct tx_desc; 256 struct tx_sw_desc; 257 258 #define TXQ_TRANSMITTING 0x1 259 260 struct sge_txq { 261 uint64_t flags; 262 uint32_t in_use; 263 uint32_t size; 264 uint32_t processed; 265 uint32_t cleaned; 266 uint32_t stop_thres; 267 uint32_t cidx; 268 uint32_t pidx; 269 uint32_t gen; 270 uint32_t unacked; 271 struct tx_desc *desc; 272 struct tx_sw_desc *sdesc; 273 uint32_t token; 274 bus_addr_t phys_addr; 275 struct task qresume_task; 276 struct task qreclaim_task; 277 struct port_info *port; 278 uint32_t cntxt_id; 279 uint64_t stops; 280 uint64_t restarts; 281 bus_dma_tag_t desc_tag; 282 bus_dmamap_t desc_map; 283 bus_dma_tag_t entry_tag; 284 struct mbuf_head sendq; 285 /* 286 * cleanq should really be an buf_ring to avoid extra 287 * mbuf touches 288 */ 289 struct mbuf_head cleanq; 290 struct buf_ring txq_mr; 291 struct mbuf *immpkt; 292 uint32_t txq_drops; 293 uint32_t txq_skipped; 294 uint32_t txq_coalesced; 295 uint32_t txq_enqueued; 296 uint32_t txq_dump_start; 297 uint32_t txq_dump_count; 298 unsigned long txq_frees; 299 struct mtx lock; 300 struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1]; 301 #define TXQ_NAME_LEN 32 302 char lockbuf[TXQ_NAME_LEN]; 303 }; 304 305 306 enum { 307 SGE_PSTAT_TSO, /* # of TSO requests */ 308 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */ 309 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ 310 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ 311 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ 312 SGE_PSTATS_LRO_QUEUED, /* # of LRO appended packets */ 313 SGE_PSTATS_LRO_FLUSHED, /* # of LRO flushed packets */ 314 SGE_PSTATS_LRO_X_STREAMS, /* # of exceeded LRO contexts */ 315 }; 316 317 #define SGE_PSTAT_MAX (SGE_PSTATS_LRO_X_STREAMS+1) 318 319 #define QS_EXITING 0x1 320 #define QS_RUNNING 0x2 321 #define QS_BOUND 0x4 322 323 struct sge_qset { 324 struct sge_rspq rspq; 325 struct sge_fl fl[SGE_RXQ_PER_SET]; 326 struct lro_state lro; 327 struct sge_txq txq[SGE_TXQ_PER_SET]; 328 uint32_t txq_stopped; /* which Tx queues are stopped */ 329 uint64_t port_stats[SGE_PSTAT_MAX]; 330 struct port_info *port; 331 int idx; /* qset # */ 332 int qs_cpuid; 333 int qs_flags; 334 struct cv qs_cv; 335 struct mtx qs_mtx; 336 #define QS_NAME_LEN 32 337 char namebuf[QS_NAME_LEN]; 338 }; 339 340 struct sge { 341 struct sge_qset qs[SGE_QSETS]; 342 struct mtx reg_lock; 343 }; 344 345 struct filter_info; 346 347 struct adapter { 348 device_t dev; 349 int flags; 350 TAILQ_ENTRY(adapter) adapter_entry; 351 352 /* PCI register resources */ 353 int regs_rid; 354 struct resource *regs_res; 355 bus_space_handle_t bh; 356 bus_space_tag_t bt; 357 bus_size_t mmio_len; 358 uint32_t link_width; 359 360 /* DMA resources */ 361 bus_dma_tag_t parent_dmat; 362 bus_dma_tag_t rx_dmat; 363 bus_dma_tag_t rx_jumbo_dmat; 364 bus_dma_tag_t tx_dmat; 365 366 /* Interrupt resources */ 367 struct resource *irq_res; 368 int irq_rid; 369 void *intr_tag; 370 371 uint32_t msix_regs_rid; 372 struct resource *msix_regs_res; 373 374 struct resource *msix_irq_res[SGE_QSETS]; 375 int msix_irq_rid[SGE_QSETS]; 376 void *msix_intr_tag[SGE_QSETS]; 377 uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */ 378 uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */ 379 uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */ 380 union { 381 uint8_t fill[SGE_QSETS]; 382 uint64_t coalesce; 383 } u; 384 385 #define tunq_fill u.fill 386 #define tunq_coalesce u.coalesce 387 388 struct filter_info *filters; 389 390 /* Tasks */ 391 struct task ext_intr_task; 392 struct task slow_intr_task; 393 struct task tick_task; 394 struct task process_responses_task; 395 struct taskqueue *tq; 396 struct callout cxgb_tick_ch; 397 struct callout sge_timer_ch; 398 399 /* Register lock for use by the hardware layer */ 400 struct mtx mdio_lock; 401 struct mtx elmer_lock; 402 403 /* Bookkeeping for the hardware layer */ 404 struct adapter_params params; 405 unsigned int slow_intr_mask; 406 unsigned long irq_stats[IRQ_NUM_STATS]; 407 408 struct sge sge; 409 struct mc7 pmrx; 410 struct mc7 pmtx; 411 struct mc7 cm; 412 struct mc5 mc5; 413 414 struct port_info port[MAX_NPORTS]; 415 device_t portdev[MAX_NPORTS]; 416 struct t3cdev tdev; 417 char fw_version[64]; 418 uint32_t open_device_map; 419 uint32_t registered_device_map; 420 #ifdef USE_SX 421 struct sx lock; 422 #else 423 struct mtx lock; 424 #endif 425 driver_intr_t *cxgb_intr; 426 int msi_count; 427 428 #define ADAPTER_LOCK_NAME_LEN 32 429 char lockbuf[ADAPTER_LOCK_NAME_LEN]; 430 char reglockbuf[ADAPTER_LOCK_NAME_LEN]; 431 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN]; 432 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN]; 433 }; 434 435 struct t3_rx_mode { 436 437 uint32_t idx; 438 struct port_info *port; 439 }; 440 441 442 #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock) 443 #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock) 444 #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock) 445 #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock) 446 447 448 #ifdef USE_SX 449 #define PORT_LOCK(port) sx_xlock(&(port)->lock); 450 #define PORT_UNLOCK(port) sx_xunlock(&(port)->lock); 451 #define PORT_LOCK_INIT(port, name) SX_INIT(&(port)->lock, name) 452 #define PORT_LOCK_DEINIT(port) SX_DESTROY(&(port)->lock) 453 #define PORT_LOCK_ASSERT_OWNED(port) sx_assert(&(port)->lock, SA_LOCKED) 454 455 #define ADAPTER_LOCK(adap) sx_xlock(&(adap)->lock); 456 #define ADAPTER_UNLOCK(adap) sx_xunlock(&(adap)->lock); 457 #define ADAPTER_LOCK_INIT(adap, name) SX_INIT(&(adap)->lock, name) 458 #define ADAPTER_LOCK_DEINIT(adap) SX_DESTROY(&(adap)->lock) 459 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) sx_assert(&(adap)->lock, SA_UNLOCKED) 460 #else 461 #define PORT_LOCK(port) mtx_lock(&(port)->lock); 462 #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock); 463 #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF) 464 #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock) 465 #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED) 466 467 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock); 468 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock); 469 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF) 470 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock) 471 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MO_NOTOWNED) 472 #endif 473 474 475 static __inline uint32_t 476 t3_read_reg(adapter_t *adapter, uint32_t reg_addr) 477 { 478 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr)); 479 } 480 481 static __inline void 482 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) 483 { 484 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val); 485 } 486 487 static __inline void 488 t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val) 489 { 490 *val = pci_read_config(adapter->dev, reg, 4); 491 } 492 493 static __inline void 494 t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val) 495 { 496 pci_write_config(adapter->dev, reg, val, 4); 497 } 498 499 static __inline void 500 t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val) 501 { 502 *val = pci_read_config(adapter->dev, reg, 2); 503 } 504 505 static __inline void 506 t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val) 507 { 508 pci_write_config(adapter->dev, reg, val, 2); 509 } 510 511 static __inline uint8_t * 512 t3_get_next_mcaddr(struct t3_rx_mode *rm) 513 { 514 uint8_t *macaddr = NULL; 515 516 if (rm->idx == 0) 517 macaddr = (uint8_t *)rm->port->hw_addr; 518 519 rm->idx++; 520 return (macaddr); 521 } 522 523 static __inline void 524 t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port) 525 { 526 rm->idx = 0; 527 rm->port = port; 528 } 529 530 static __inline struct port_info * 531 adap2pinfo(struct adapter *adap, int idx) 532 { 533 return &adap->port[idx]; 534 } 535 536 int t3_os_find_pci_capability(adapter_t *adapter, int cap); 537 int t3_os_pci_save_state(struct adapter *adapter); 538 int t3_os_pci_restore_state(struct adapter *adapter); 539 void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, 540 int speed, int duplex, int fc); 541 void t3_sge_err_intr_handler(adapter_t *adapter); 542 int t3_offload_tx(struct t3cdev *, struct mbuf *); 543 void t3_os_ext_intr_handler(adapter_t *adapter); 544 void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]); 545 int t3_mgmt_tx(adapter_t *adap, struct mbuf *m); 546 547 548 int t3_sge_alloc(struct adapter *); 549 int t3_sge_free(struct adapter *); 550 int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *, 551 int, struct port_info *); 552 void t3_free_sge_resources(adapter_t *); 553 void t3_sge_start(adapter_t *); 554 void t3_sge_stop(adapter_t *); 555 void t3b_intr(void *data); 556 void t3_intr_msi(void *data); 557 void t3_intr_msix(void *data); 558 int t3_encap(struct sge_qset *, struct mbuf **, int); 559 560 int t3_sge_init_adapter(adapter_t *); 561 int t3_sge_reset_adapter(adapter_t *); 562 int t3_sge_init_port(struct port_info *); 563 void t3_sge_deinit_sw(adapter_t *); 564 void t3_free_tx_desc(struct sge_txq *q, int n); 565 void t3_free_tx_desc_all(struct sge_txq *q); 566 567 void t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct mbuf *m, 568 int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro); 569 void t3_rx_eth(struct adapter *adap, struct sge_rspq *rq, struct mbuf *m, int ethpad); 570 void t3_lro_flush(adapter_t *adap, struct sge_qset *qs, struct lro_state *state); 571 572 void t3_add_attach_sysctls(adapter_t *sc); 573 void t3_add_configured_sysctls(adapter_t *sc); 574 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, 575 unsigned char *data); 576 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); 577 /* 578 * XXX figure out how we can return this to being private to sge 579 */ 580 #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC)) 581 582 #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field))) 583 584 static __inline struct sge_qset * 585 fl_to_qset(struct sge_fl *q, int qidx) 586 { 587 return container_of(q, struct sge_qset, fl[qidx]); 588 } 589 590 static __inline struct sge_qset * 591 rspq_to_qset(struct sge_rspq *q) 592 { 593 return container_of(q, struct sge_qset, rspq); 594 } 595 596 static __inline struct sge_qset * 597 txq_to_qset(struct sge_txq *q, int qidx) 598 { 599 return container_of(q, struct sge_qset, txq[qidx]); 600 } 601 602 static __inline struct adapter * 603 tdev2adap(struct t3cdev *d) 604 { 605 return container_of(d, struct adapter, tdev); 606 } 607 608 #undef container_of 609 610 #define OFFLOAD_DEVMAP_BIT 15 611 static inline int offload_running(adapter_t *adapter) 612 { 613 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 614 } 615 616 int cxgb_pcpu_enqueue_packet(struct ifnet *ifp, struct mbuf *m); 617 int cxgb_pcpu_start(struct ifnet *ifp, struct mbuf *m); 618 void cxgb_pcpu_shutdown_threads(struct adapter *sc); 619 void cxgb_pcpu_startup_threads(struct adapter *sc); 620 621 int process_responses(adapter_t *adap, struct sge_qset *qs, int budget); 622 void t3_free_qset(adapter_t *sc, struct sge_qset *q); 623 void cxgb_start(struct ifnet *ifp); 624 void refill_fl_service(adapter_t *adap, struct sge_fl *fl); 625 #endif 626