1 /************************************************************************** 2 3 Copyright (c) 2007-2009, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 32 33 #ifndef _CXGB_ADAPTER_H_ 34 #define _CXGB_ADAPTER_H_ 35 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/condvar.h> 43 #include <sys/buf_ring.h> 44 #include <sys/taskqueue.h> 45 46 #include <net/ethernet.h> 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/if_media.h> 50 #include <net/if_dl.h> 51 #include <netinet/in.h> 52 #include <netinet/tcp_lro.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 #include <sys/bus_dma.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 61 #include <cxgb_osdep.h> 62 #include <sys/mbufq.h> 63 64 struct adapter; 65 struct sge_qset; 66 extern int cxgb_debug; 67 68 #ifdef DEBUG_LOCKING 69 #define MTX_INIT(lock, lockname, class, flags) \ 70 do { \ 71 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \ 72 mtx_init((lock), lockname, class, flags); \ 73 } while (0) 74 75 #define MTX_DESTROY(lock) \ 76 do { \ 77 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \ 78 mtx_destroy((lock)); \ 79 } while (0) 80 81 #else 82 #define MTX_INIT mtx_init 83 #define MTX_DESTROY mtx_destroy 84 #endif 85 86 enum { 87 LF_NO = 0, 88 LF_MAYBE, 89 LF_YES 90 }; 91 92 struct port_info { 93 struct adapter *adapter; 94 struct ifnet *ifp; 95 int if_flags; 96 int flags; 97 const struct port_type_info *port_type; 98 struct cphy phy; 99 struct cmac mac; 100 struct timeval last_refreshed; 101 struct link_config link_config; 102 struct ifmedia media; 103 struct mtx lock; 104 uint32_t port_id; 105 uint32_t tx_chan; 106 uint32_t txpkt_intf; 107 uint32_t first_qset; 108 uint32_t nqsets; 109 int link_fault; 110 111 uint8_t hw_addr[ETHER_ADDR_LEN]; 112 struct callout link_check_ch; 113 struct task link_check_task; 114 struct task timer_reclaim_task; 115 struct cdev *port_cdev; 116 117 #define PORT_LOCK_NAME_LEN 32 118 #define PORT_NAME_LEN 32 119 char lockbuf[PORT_LOCK_NAME_LEN]; 120 char namebuf[PORT_NAME_LEN]; 121 } __aligned(L1_CACHE_BYTES); 122 123 enum { 124 /* adapter flags */ 125 FULL_INIT_DONE = (1 << 0), 126 USING_MSI = (1 << 1), 127 USING_MSIX = (1 << 2), 128 QUEUES_BOUND = (1 << 3), 129 FW_UPTODATE = (1 << 4), 130 TPS_UPTODATE = (1 << 5), 131 CXGB_SHUTDOWN = (1 << 6), 132 CXGB_OFLD_INIT = (1 << 7), 133 TP_PARITY_INIT = (1 << 8), 134 CXGB_BUSY = (1 << 9), 135 TOM_INIT_DONE = (1 << 10), 136 137 /* port flags */ 138 DOOMED = (1 << 0), 139 }; 140 #define IS_DOOMED(p) (p->flags & DOOMED) 141 #define SET_DOOMED(p) do {p->flags |= DOOMED;} while (0) 142 #define IS_BUSY(sc) (sc->flags & CXGB_BUSY) 143 #define SET_BUSY(sc) do {sc->flags |= CXGB_BUSY;} while (0) 144 #define CLR_BUSY(sc) do {sc->flags &= ~CXGB_BUSY;} while (0) 145 146 #define FL_Q_SIZE 4096 147 #define JUMBO_Q_SIZE 1024 148 #define RSPQ_Q_SIZE 2048 149 #define TX_ETH_Q_SIZE 1024 150 #define TX_OFLD_Q_SIZE 1024 151 #define TX_CTRL_Q_SIZE 256 152 153 enum { TXQ_ETH = 0, 154 TXQ_OFLD = 1, 155 TXQ_CTRL = 2, }; 156 157 158 /* 159 * work request size in bytes 160 */ 161 #define WR_LEN (WR_FLITS * 8) 162 #define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt_lso)) 163 164 struct lro_state { 165 unsigned short enabled; 166 struct lro_ctrl ctrl; 167 }; 168 169 #define RX_BUNDLE_SIZE 8 170 171 struct rsp_desc; 172 173 struct sge_rspq { 174 uint32_t credits; 175 uint32_t size; 176 uint32_t cidx; 177 uint32_t gen; 178 uint32_t polling; 179 uint32_t holdoff_tmr; 180 uint32_t next_holdoff; 181 uint32_t imm_data; 182 uint32_t async_notif; 183 uint32_t cntxt_id; 184 uint32_t offload_pkts; 185 uint32_t pure_rsps; 186 uint32_t unhandled_irqs; 187 uint32_t starved; 188 189 bus_addr_t phys_addr; 190 bus_dma_tag_t desc_tag; 191 bus_dmamap_t desc_map; 192 193 struct t3_mbuf_hdr rspq_mh; 194 struct rsp_desc *desc; 195 struct mtx lock; 196 #define RSPQ_NAME_LEN 32 197 char lockbuf[RSPQ_NAME_LEN]; 198 uint32_t rspq_dump_start; 199 uint32_t rspq_dump_count; 200 }; 201 202 struct rx_desc; 203 struct rx_sw_desc; 204 205 struct sge_fl { 206 uint32_t buf_size; 207 uint32_t credits; 208 uint32_t size; 209 uint32_t cidx; 210 uint32_t pidx; 211 uint32_t gen; 212 uint32_t db_pending; 213 bus_addr_t phys_addr; 214 uint32_t cntxt_id; 215 uint32_t empty; 216 bus_dma_tag_t desc_tag; 217 bus_dmamap_t desc_map; 218 bus_dma_tag_t entry_tag; 219 uma_zone_t zone; 220 struct rx_desc *desc; 221 struct rx_sw_desc *sdesc; 222 int type; 223 }; 224 225 struct tx_desc; 226 struct tx_sw_desc; 227 228 #define TXQ_TRANSMITTING 0x1 229 230 struct sge_txq { 231 uint64_t flags; 232 uint32_t in_use; 233 uint32_t size; 234 uint32_t processed; 235 uint32_t cleaned; 236 uint32_t stop_thres; 237 uint32_t cidx; 238 uint32_t pidx; 239 uint32_t gen; 240 uint32_t unacked; 241 uint32_t db_pending; 242 struct tx_desc *desc; 243 struct tx_sw_desc *sdesc; 244 uint32_t token; 245 bus_addr_t phys_addr; 246 struct task qresume_task; 247 struct task qreclaim_task; 248 uint32_t cntxt_id; 249 uint64_t stops; 250 uint64_t restarts; 251 bus_dma_tag_t desc_tag; 252 bus_dmamap_t desc_map; 253 bus_dma_tag_t entry_tag; 254 struct mbuf_head sendq; 255 256 struct buf_ring *txq_mr; 257 struct ifaltq *txq_ifq; 258 struct callout txq_timer; 259 struct callout txq_watchdog; 260 uint64_t txq_coalesced; 261 uint32_t txq_skipped; 262 uint32_t txq_enqueued; 263 uint32_t txq_dump_start; 264 uint32_t txq_dump_count; 265 uint64_t txq_direct_packets; 266 uint64_t txq_direct_bytes; 267 uint64_t txq_frees; 268 struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1]; 269 }; 270 271 #define SGE_PSTAT_MAX (SGE_PSTAT_VLANINS+1) 272 273 #define QS_EXITING 0x1 274 #define QS_RUNNING 0x2 275 #define QS_BOUND 0x4 276 #define QS_FLUSHING 0x8 277 #define QS_TIMEOUT 0x10 278 279 struct sge_qset { 280 struct sge_rspq rspq; 281 struct sge_fl fl[SGE_RXQ_PER_SET]; 282 struct lro_state lro; 283 struct sge_txq txq[SGE_TXQ_PER_SET]; 284 uint32_t txq_stopped; /* which Tx queues are stopped */ 285 struct port_info *port; 286 struct adapter *adap; 287 int idx; /* qset # */ 288 int qs_flags; 289 int coalescing; 290 struct cv qs_cv; 291 struct mtx lock; 292 #define QS_NAME_LEN 32 293 char namebuf[QS_NAME_LEN]; 294 }; 295 296 struct sge { 297 struct sge_qset qs[SGE_QSETS]; 298 struct mtx reg_lock; 299 }; 300 301 struct filter_info; 302 303 typedef int (*cpl_handler_t)(struct sge_qset *, struct rsp_desc *, 304 struct mbuf *); 305 306 struct adapter { 307 SLIST_ENTRY(adapter) link; 308 device_t dev; 309 int flags; 310 311 /* PCI register resources */ 312 int regs_rid; 313 struct resource *regs_res; 314 int udbs_rid; 315 struct resource *udbs_res; 316 bus_space_handle_t bh; 317 bus_space_tag_t bt; 318 bus_size_t mmio_len; 319 uint32_t link_width; 320 321 /* DMA resources */ 322 bus_dma_tag_t parent_dmat; 323 bus_dma_tag_t rx_dmat; 324 bus_dma_tag_t rx_jumbo_dmat; 325 bus_dma_tag_t tx_dmat; 326 327 /* Interrupt resources */ 328 struct resource *irq_res; 329 int irq_rid; 330 void *intr_tag; 331 332 uint32_t msix_regs_rid; 333 struct resource *msix_regs_res; 334 335 struct resource *msix_irq_res[SGE_QSETS]; 336 int msix_irq_rid[SGE_QSETS]; 337 void *msix_intr_tag[SGE_QSETS]; 338 uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */ 339 uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */ 340 uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */ 341 union { 342 uint8_t fill[SGE_QSETS]; 343 uint64_t coalesce; 344 } u; 345 346 #define tunq_fill u.fill 347 #define tunq_coalesce u.coalesce 348 349 struct filter_info *filters; 350 351 /* Tasks */ 352 struct task slow_intr_task; 353 struct task tick_task; 354 struct taskqueue *tq; 355 struct callout cxgb_tick_ch; 356 struct callout sge_timer_ch; 357 358 /* Register lock for use by the hardware layer */ 359 struct mtx mdio_lock; 360 struct mtx elmer_lock; 361 362 /* Bookkeeping for the hardware layer */ 363 struct adapter_params params; 364 unsigned int slow_intr_mask; 365 unsigned long irq_stats[IRQ_NUM_STATS]; 366 367 struct sge sge; 368 struct mc7 pmrx; 369 struct mc7 pmtx; 370 struct mc7 cm; 371 struct mc5 mc5; 372 373 struct port_info port[MAX_NPORTS]; 374 device_t portdev[MAX_NPORTS]; 375 #ifdef TCP_OFFLOAD 376 void *tom_softc; 377 void *iwarp_softc; 378 #endif 379 char fw_version[64]; 380 char port_types[MAX_NPORTS + 1]; 381 uint32_t open_device_map; 382 #ifdef TCP_OFFLOAD 383 int offload_map; 384 #endif 385 struct mtx lock; 386 driver_intr_t *cxgb_intr; 387 int msi_count; 388 389 #define ADAPTER_LOCK_NAME_LEN 32 390 char lockbuf[ADAPTER_LOCK_NAME_LEN]; 391 char reglockbuf[ADAPTER_LOCK_NAME_LEN]; 392 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN]; 393 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN]; 394 395 int timestamp; 396 397 #ifdef TCP_OFFLOAD 398 #define NUM_CPL_HANDLERS 0xa7 399 cpl_handler_t cpl_handler[NUM_CPL_HANDLERS] __aligned(CACHE_LINE_SIZE); 400 #endif 401 }; 402 403 struct t3_rx_mode { 404 405 uint32_t idx; 406 struct port_info *port; 407 }; 408 409 #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock) 410 #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock) 411 #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock) 412 #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock) 413 414 415 #define PORT_LOCK(port) mtx_lock(&(port)->lock); 416 #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock); 417 #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF) 418 #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock) 419 #define PORT_LOCK_ASSERT_NOTOWNED(port) mtx_assert(&(port)->lock, MA_NOTOWNED) 420 #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED) 421 422 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock); 423 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock); 424 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF) 425 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock) 426 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED) 427 #define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED) 428 429 430 static __inline uint32_t 431 t3_read_reg(adapter_t *adapter, uint32_t reg_addr) 432 { 433 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr)); 434 } 435 436 static __inline void 437 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) 438 { 439 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val); 440 } 441 442 static __inline void 443 t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val) 444 { 445 *val = pci_read_config(adapter->dev, reg, 4); 446 } 447 448 static __inline void 449 t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val) 450 { 451 pci_write_config(adapter->dev, reg, val, 4); 452 } 453 454 static __inline void 455 t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val) 456 { 457 *val = pci_read_config(adapter->dev, reg, 2); 458 } 459 460 static __inline void 461 t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val) 462 { 463 pci_write_config(adapter->dev, reg, val, 2); 464 } 465 466 static __inline uint8_t * 467 t3_get_next_mcaddr(struct t3_rx_mode *rm) 468 { 469 uint8_t *macaddr = NULL; 470 struct ifnet *ifp = rm->port->ifp; 471 struct ifmultiaddr *ifma; 472 int i = 0; 473 474 if_maddr_rlock(ifp); 475 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 476 if (ifma->ifma_addr->sa_family != AF_LINK) 477 continue; 478 if (i == rm->idx) { 479 macaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 480 break; 481 } 482 i++; 483 } 484 if_maddr_runlock(ifp); 485 486 rm->idx++; 487 return (macaddr); 488 } 489 490 static __inline void 491 t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port) 492 { 493 rm->idx = 0; 494 rm->port = port; 495 } 496 497 static __inline struct port_info * 498 adap2pinfo(struct adapter *adap, int idx) 499 { 500 return &adap->port[idx]; 501 } 502 503 int t3_os_find_pci_capability(adapter_t *adapter, int cap); 504 int t3_os_pci_save_state(struct adapter *adapter); 505 int t3_os_pci_restore_state(struct adapter *adapter); 506 void t3_os_link_intr(struct port_info *); 507 void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, 508 int speed, int duplex, int fc, int mac_was_reset); 509 void t3_os_phymod_changed(struct adapter *adap, int port_id); 510 void t3_sge_err_intr_handler(adapter_t *adapter); 511 #ifdef TCP_OFFLOAD 512 int t3_offload_tx(struct adapter *, struct mbuf *); 513 #endif 514 void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]); 515 int t3_mgmt_tx(adapter_t *adap, struct mbuf *m); 516 int t3_register_cpl_handler(struct adapter *, int, cpl_handler_t); 517 518 int t3_sge_alloc(struct adapter *); 519 int t3_sge_free(struct adapter *); 520 int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *, 521 int, struct port_info *); 522 void t3_free_sge_resources(adapter_t *, int); 523 void t3_sge_start(adapter_t *); 524 void t3_sge_stop(adapter_t *); 525 void t3b_intr(void *data); 526 void t3_intr_msi(void *data); 527 void t3_intr_msix(void *data); 528 529 int t3_sge_init_adapter(adapter_t *); 530 int t3_sge_reset_adapter(adapter_t *); 531 int t3_sge_init_port(struct port_info *); 532 void t3_free_tx_desc(struct sge_qset *qs, int n, int qid); 533 534 void t3_rx_eth(struct adapter *adap, struct mbuf *m, int ethpad); 535 536 void t3_add_attach_sysctls(adapter_t *sc); 537 void t3_add_configured_sysctls(adapter_t *sc); 538 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, 539 unsigned char *data); 540 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); 541 542 /* 543 * XXX figure out how we can return this to being private to sge 544 */ 545 #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC)) 546 547 #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field))) 548 549 static __inline struct sge_qset * 550 fl_to_qset(struct sge_fl *q, int qidx) 551 { 552 return container_of(q, struct sge_qset, fl[qidx]); 553 } 554 555 static __inline struct sge_qset * 556 rspq_to_qset(struct sge_rspq *q) 557 { 558 return container_of(q, struct sge_qset, rspq); 559 } 560 561 static __inline struct sge_qset * 562 txq_to_qset(struct sge_txq *q, int qidx) 563 { 564 return container_of(q, struct sge_qset, txq[qidx]); 565 } 566 567 #undef container_of 568 569 #define OFFLOAD_DEVMAP_BIT (1 << MAX_NPORTS) 570 static inline int offload_running(adapter_t *adapter) 571 { 572 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 573 } 574 575 void cxgb_tx_watchdog(void *arg); 576 int cxgb_transmit(struct ifnet *ifp, struct mbuf *m); 577 void cxgb_qflush(struct ifnet *ifp); 578 void t3_iterate(void (*)(struct adapter *, void *), void *); 579 void cxgb_refresh_stats(struct port_info *); 580 #endif 581