1 /************************************************************************** 2 3 Copyright (c) 2007-2009, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 32 33 #ifndef _CXGB_ADAPTER_H_ 34 #define _CXGB_ADAPTER_H_ 35 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/condvar.h> 43 #include <sys/buf_ring.h> 44 #include <sys/taskqueue.h> 45 46 #include <net/ethernet.h> 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/if_media.h> 50 #include <net/if_dl.h> 51 #include <netinet/in.h> 52 #include <netinet/tcp_lro.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 #include <sys/bus_dma.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 61 #include <cxgb_osdep.h> 62 63 struct adapter; 64 struct sge_qset; 65 extern int cxgb_debug; 66 67 #ifdef DEBUG_LOCKING 68 #define MTX_INIT(lock, lockname, class, flags) \ 69 do { \ 70 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \ 71 mtx_init((lock), lockname, class, flags); \ 72 } while (0) 73 74 #define MTX_DESTROY(lock) \ 75 do { \ 76 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \ 77 mtx_destroy((lock)); \ 78 } while (0) 79 80 #else 81 #define MTX_INIT mtx_init 82 #define MTX_DESTROY mtx_destroy 83 #endif 84 85 enum { 86 LF_NO = 0, 87 LF_MAYBE, 88 LF_YES 89 }; 90 91 struct port_info { 92 struct adapter *adapter; 93 struct ifnet *ifp; 94 int if_flags; 95 int flags; 96 const struct port_type_info *port_type; 97 struct cphy phy; 98 struct cmac mac; 99 struct timeval last_refreshed; 100 struct link_config link_config; 101 struct ifmedia media; 102 struct mtx lock; 103 uint32_t port_id; 104 uint32_t tx_chan; 105 uint32_t txpkt_intf; 106 uint32_t first_qset; 107 uint32_t nqsets; 108 int link_fault; 109 110 uint8_t hw_addr[ETHER_ADDR_LEN]; 111 struct callout link_check_ch; 112 struct task link_check_task; 113 struct task timer_reclaim_task; 114 struct cdev *port_cdev; 115 116 #define PORT_LOCK_NAME_LEN 32 117 #define PORT_NAME_LEN 32 118 char lockbuf[PORT_LOCK_NAME_LEN]; 119 char namebuf[PORT_NAME_LEN]; 120 } __aligned(L1_CACHE_BYTES); 121 122 enum { 123 /* adapter flags */ 124 FULL_INIT_DONE = (1 << 0), 125 USING_MSI = (1 << 1), 126 USING_MSIX = (1 << 2), 127 QUEUES_BOUND = (1 << 3), 128 FW_UPTODATE = (1 << 4), 129 TPS_UPTODATE = (1 << 5), 130 CXGB_SHUTDOWN = (1 << 6), 131 CXGB_OFLD_INIT = (1 << 7), 132 TP_PARITY_INIT = (1 << 8), 133 CXGB_BUSY = (1 << 9), 134 TOM_INIT_DONE = (1 << 10), 135 136 /* port flags */ 137 DOOMED = (1 << 0), 138 }; 139 #define IS_DOOMED(p) (p->flags & DOOMED) 140 #define SET_DOOMED(p) do {p->flags |= DOOMED;} while (0) 141 #define IS_BUSY(sc) (sc->flags & CXGB_BUSY) 142 #define SET_BUSY(sc) do {sc->flags |= CXGB_BUSY;} while (0) 143 #define CLR_BUSY(sc) do {sc->flags &= ~CXGB_BUSY;} while (0) 144 145 #define FL_Q_SIZE 4096 146 #define JUMBO_Q_SIZE 1024 147 #define RSPQ_Q_SIZE 2048 148 #define TX_ETH_Q_SIZE 1024 149 #define TX_OFLD_Q_SIZE 1024 150 #define TX_CTRL_Q_SIZE 256 151 152 enum { TXQ_ETH = 0, 153 TXQ_OFLD = 1, 154 TXQ_CTRL = 2, }; 155 156 157 /* 158 * work request size in bytes 159 */ 160 #define WR_LEN (WR_FLITS * 8) 161 #define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt_lso)) 162 163 struct lro_state { 164 unsigned short enabled; 165 struct lro_ctrl ctrl; 166 }; 167 168 #define RX_BUNDLE_SIZE 8 169 170 struct rsp_desc; 171 172 struct sge_rspq { 173 uint32_t credits; 174 uint32_t size; 175 uint32_t cidx; 176 uint32_t gen; 177 uint32_t polling; 178 uint32_t holdoff_tmr; 179 uint32_t next_holdoff; 180 uint32_t imm_data; 181 uint32_t async_notif; 182 uint32_t cntxt_id; 183 uint32_t offload_pkts; 184 uint32_t pure_rsps; 185 uint32_t unhandled_irqs; 186 uint32_t starved; 187 188 bus_addr_t phys_addr; 189 bus_dma_tag_t desc_tag; 190 bus_dmamap_t desc_map; 191 192 struct t3_mbuf_hdr rspq_mh; 193 struct rsp_desc *desc; 194 struct mtx lock; 195 #define RSPQ_NAME_LEN 32 196 char lockbuf[RSPQ_NAME_LEN]; 197 uint32_t rspq_dump_start; 198 uint32_t rspq_dump_count; 199 }; 200 201 struct rx_desc; 202 struct rx_sw_desc; 203 204 struct sge_fl { 205 uint32_t buf_size; 206 uint32_t credits; 207 uint32_t size; 208 uint32_t cidx; 209 uint32_t pidx; 210 uint32_t gen; 211 uint32_t db_pending; 212 bus_addr_t phys_addr; 213 uint32_t cntxt_id; 214 uint32_t empty; 215 bus_dma_tag_t desc_tag; 216 bus_dmamap_t desc_map; 217 bus_dma_tag_t entry_tag; 218 uma_zone_t zone; 219 struct rx_desc *desc; 220 struct rx_sw_desc *sdesc; 221 int type; 222 }; 223 224 struct tx_desc; 225 struct tx_sw_desc; 226 227 #define TXQ_TRANSMITTING 0x1 228 229 struct sge_txq { 230 uint64_t flags; 231 uint32_t in_use; 232 uint32_t size; 233 uint32_t processed; 234 uint32_t cleaned; 235 uint32_t stop_thres; 236 uint32_t cidx; 237 uint32_t pidx; 238 uint32_t gen; 239 uint32_t unacked; 240 uint32_t db_pending; 241 struct tx_desc *desc; 242 struct tx_sw_desc *sdesc; 243 uint32_t token; 244 bus_addr_t phys_addr; 245 struct task qresume_task; 246 struct task qreclaim_task; 247 uint32_t cntxt_id; 248 uint64_t stops; 249 uint64_t restarts; 250 bus_dma_tag_t desc_tag; 251 bus_dmamap_t desc_map; 252 bus_dma_tag_t entry_tag; 253 struct mbufq sendq; 254 255 struct buf_ring *txq_mr; 256 struct ifaltq *txq_ifq; 257 struct callout txq_timer; 258 struct callout txq_watchdog; 259 uint64_t txq_coalesced; 260 uint32_t txq_skipped; 261 uint32_t txq_enqueued; 262 uint32_t txq_dump_start; 263 uint32_t txq_dump_count; 264 uint64_t txq_direct_packets; 265 uint64_t txq_direct_bytes; 266 uint64_t txq_frees; 267 struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1]; 268 }; 269 270 #define SGE_PSTAT_MAX (SGE_PSTAT_VLANINS+1) 271 272 #define QS_EXITING 0x1 273 #define QS_RUNNING 0x2 274 #define QS_BOUND 0x4 275 #define QS_FLUSHING 0x8 276 #define QS_TIMEOUT 0x10 277 278 struct sge_qset { 279 struct sge_rspq rspq; 280 struct sge_fl fl[SGE_RXQ_PER_SET]; 281 struct lro_state lro; 282 struct sge_txq txq[SGE_TXQ_PER_SET]; 283 uint32_t txq_stopped; /* which Tx queues are stopped */ 284 struct port_info *port; 285 struct adapter *adap; 286 int idx; /* qset # */ 287 int qs_flags; 288 int coalescing; 289 struct cv qs_cv; 290 struct mtx lock; 291 #define QS_NAME_LEN 32 292 char namebuf[QS_NAME_LEN]; 293 }; 294 295 struct sge { 296 struct sge_qset qs[SGE_QSETS]; 297 struct mtx reg_lock; 298 }; 299 300 struct filter_info; 301 302 typedef int (*cpl_handler_t)(struct sge_qset *, struct rsp_desc *, 303 struct mbuf *); 304 305 struct adapter { 306 SLIST_ENTRY(adapter) link; 307 device_t dev; 308 int flags; 309 310 /* PCI register resources */ 311 int regs_rid; 312 struct resource *regs_res; 313 int udbs_rid; 314 struct resource *udbs_res; 315 bus_space_handle_t bh; 316 bus_space_tag_t bt; 317 bus_size_t mmio_len; 318 uint32_t link_width; 319 320 /* DMA resources */ 321 bus_dma_tag_t parent_dmat; 322 bus_dma_tag_t rx_dmat; 323 bus_dma_tag_t rx_jumbo_dmat; 324 bus_dma_tag_t tx_dmat; 325 326 /* Interrupt resources */ 327 struct resource *irq_res; 328 int irq_rid; 329 void *intr_tag; 330 331 uint32_t msix_regs_rid; 332 struct resource *msix_regs_res; 333 334 struct resource *msix_irq_res[SGE_QSETS]; 335 int msix_irq_rid[SGE_QSETS]; 336 void *msix_intr_tag[SGE_QSETS]; 337 uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */ 338 uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */ 339 uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */ 340 union { 341 uint8_t fill[SGE_QSETS]; 342 uint64_t coalesce; 343 } u; 344 345 #define tunq_fill u.fill 346 #define tunq_coalesce u.coalesce 347 348 struct filter_info *filters; 349 350 /* Tasks */ 351 struct task slow_intr_task; 352 struct task tick_task; 353 struct taskqueue *tq; 354 struct callout cxgb_tick_ch; 355 struct callout sge_timer_ch; 356 357 /* Register lock for use by the hardware layer */ 358 struct mtx mdio_lock; 359 struct mtx elmer_lock; 360 361 /* Bookkeeping for the hardware layer */ 362 struct adapter_params params; 363 unsigned int slow_intr_mask; 364 unsigned long irq_stats[IRQ_NUM_STATS]; 365 366 struct sge sge; 367 struct mc7 pmrx; 368 struct mc7 pmtx; 369 struct mc7 cm; 370 struct mc5 mc5; 371 372 struct port_info port[MAX_NPORTS]; 373 device_t portdev[MAX_NPORTS]; 374 #ifdef TCP_OFFLOAD 375 void *tom_softc; 376 void *iwarp_softc; 377 #endif 378 char fw_version[64]; 379 char port_types[MAX_NPORTS + 1]; 380 uint32_t open_device_map; 381 #ifdef TCP_OFFLOAD 382 int offload_map; 383 #endif 384 struct mtx lock; 385 driver_intr_t *cxgb_intr; 386 int msi_count; 387 388 #define ADAPTER_LOCK_NAME_LEN 32 389 char lockbuf[ADAPTER_LOCK_NAME_LEN]; 390 char reglockbuf[ADAPTER_LOCK_NAME_LEN]; 391 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN]; 392 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN]; 393 394 int timestamp; 395 396 #ifdef TCP_OFFLOAD 397 #define NUM_CPL_HANDLERS 0xa7 398 cpl_handler_t cpl_handler[NUM_CPL_HANDLERS] __aligned(CACHE_LINE_SIZE); 399 #endif 400 }; 401 402 struct t3_rx_mode { 403 404 uint32_t idx; 405 struct port_info *port; 406 }; 407 408 #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock) 409 #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock) 410 #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock) 411 #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock) 412 413 414 #define PORT_LOCK(port) mtx_lock(&(port)->lock); 415 #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock); 416 #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF) 417 #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock) 418 #define PORT_LOCK_ASSERT_NOTOWNED(port) mtx_assert(&(port)->lock, MA_NOTOWNED) 419 #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED) 420 421 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock); 422 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock); 423 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF) 424 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock) 425 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED) 426 #define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED) 427 428 429 static __inline uint32_t 430 t3_read_reg(adapter_t *adapter, uint32_t reg_addr) 431 { 432 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr)); 433 } 434 435 static __inline void 436 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) 437 { 438 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val); 439 } 440 441 static __inline void 442 t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val) 443 { 444 *val = pci_read_config(adapter->dev, reg, 4); 445 } 446 447 static __inline void 448 t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val) 449 { 450 pci_write_config(adapter->dev, reg, val, 4); 451 } 452 453 static __inline void 454 t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val) 455 { 456 *val = pci_read_config(adapter->dev, reg, 2); 457 } 458 459 static __inline void 460 t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val) 461 { 462 pci_write_config(adapter->dev, reg, val, 2); 463 } 464 465 static __inline uint8_t * 466 t3_get_next_mcaddr(struct t3_rx_mode *rm) 467 { 468 uint8_t *macaddr = NULL; 469 struct ifnet *ifp = rm->port->ifp; 470 struct ifmultiaddr *ifma; 471 int i = 0; 472 473 if_maddr_rlock(ifp); 474 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 475 if (ifma->ifma_addr->sa_family != AF_LINK) 476 continue; 477 if (i == rm->idx) { 478 macaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 479 break; 480 } 481 i++; 482 } 483 if_maddr_runlock(ifp); 484 485 rm->idx++; 486 return (macaddr); 487 } 488 489 static __inline void 490 t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port) 491 { 492 rm->idx = 0; 493 rm->port = port; 494 } 495 496 static __inline struct port_info * 497 adap2pinfo(struct adapter *adap, int idx) 498 { 499 return &adap->port[idx]; 500 } 501 502 int t3_os_find_pci_capability(adapter_t *adapter, int cap); 503 int t3_os_pci_save_state(struct adapter *adapter); 504 int t3_os_pci_restore_state(struct adapter *adapter); 505 void t3_os_link_intr(struct port_info *); 506 void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, 507 int speed, int duplex, int fc, int mac_was_reset); 508 void t3_os_phymod_changed(struct adapter *adap, int port_id); 509 void t3_sge_err_intr_handler(adapter_t *adapter); 510 #ifdef TCP_OFFLOAD 511 int t3_offload_tx(struct adapter *, struct mbuf *); 512 #endif 513 void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]); 514 int t3_mgmt_tx(adapter_t *adap, struct mbuf *m); 515 int t3_register_cpl_handler(struct adapter *, int, cpl_handler_t); 516 517 int t3_sge_alloc(struct adapter *); 518 int t3_sge_free(struct adapter *); 519 int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *, 520 int, struct port_info *); 521 void t3_free_sge_resources(adapter_t *, int); 522 void t3_sge_start(adapter_t *); 523 void t3_sge_stop(adapter_t *); 524 void t3b_intr(void *data); 525 void t3_intr_msi(void *data); 526 void t3_intr_msix(void *data); 527 528 int t3_sge_init_adapter(adapter_t *); 529 int t3_sge_reset_adapter(adapter_t *); 530 int t3_sge_init_port(struct port_info *); 531 void t3_free_tx_desc(struct sge_qset *qs, int n, int qid); 532 533 void t3_rx_eth(struct adapter *adap, struct mbuf *m, int ethpad); 534 535 void t3_add_attach_sysctls(adapter_t *sc); 536 void t3_add_configured_sysctls(adapter_t *sc); 537 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, 538 unsigned char *data); 539 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); 540 541 /* 542 * XXX figure out how we can return this to being private to sge 543 */ 544 #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC)) 545 546 #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field))) 547 548 static __inline struct sge_qset * 549 fl_to_qset(struct sge_fl *q, int qidx) 550 { 551 return container_of(q, struct sge_qset, fl[qidx]); 552 } 553 554 static __inline struct sge_qset * 555 rspq_to_qset(struct sge_rspq *q) 556 { 557 return container_of(q, struct sge_qset, rspq); 558 } 559 560 static __inline struct sge_qset * 561 txq_to_qset(struct sge_txq *q, int qidx) 562 { 563 return container_of(q, struct sge_qset, txq[qidx]); 564 } 565 566 #undef container_of 567 568 #define OFFLOAD_DEVMAP_BIT (1 << MAX_NPORTS) 569 static inline int offload_running(adapter_t *adapter) 570 { 571 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 572 } 573 574 void cxgb_tx_watchdog(void *arg); 575 int cxgb_transmit(struct ifnet *ifp, struct mbuf *m); 576 void cxgb_qflush(struct ifnet *ifp); 577 void t3_iterate(void (*)(struct adapter *, void *), void *); 578 void cxgb_refresh_stats(struct port_info *); 579 #endif 580